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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Uwe Hermannffec5f32007-08-23 16:08:21 +000069/**
70 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000071 *
72 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +000073 * - Agami Aruma
74 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000075 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000076static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000077{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000078 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000079
Uwe Hermann372eeb52007-12-04 21:49:06 +000080 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000081 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000082 fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000083 name, sio_read(port, 0x20));
84 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000085 return -1;
86 }
87
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000088 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000089 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000090
Uwe Hermann372eeb52007-12-04 21:49:06 +000091 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000092 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000093
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000094 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
95 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
96 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
97 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000098
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000099 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000100
101 return 0;
102}
103
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000104static int w83627hf_gpio24_raise_2e(const char *name)
105{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000106 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000107}
108
109/**
110 * Winbond W83627THF: GPIO 4, bit 4
111 *
112 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000113 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000114 * - MSI K8N-NEO3
115 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000116static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000117{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000119
120 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000122 fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 name, sio_read(port, 0x20));
124 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000125 return -1;
126 }
127
128 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
129
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000130 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
131 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
132 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
133 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
134 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000135
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000136 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000137
138 return 0;
139}
140
Peter Stugecce26822008-07-21 17:48:40 +0000141static int w83627thf_gpio4_4_raise_2e(const char *name)
142{
143 return w83627thf_gpio4_4_raise(0x2e, name);
144}
145
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146static int w83627thf_gpio4_4_raise_4e(const char *name)
147{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000149}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000150
Uwe Hermannffec5f32007-08-23 16:08:21 +0000151/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000152 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000153 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000154static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000155{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000156 w836xx_ext_enter(port);
157 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000158 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000160 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000161 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000162}
163
164/**
165 * Common routine for several VT823x based boards.
166 */
167static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev)
168{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000169 uint8_t val;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000170
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000171 /* All memory cycles, not just ROM ones, go to LPC. */
172 val = pci_read_byte(dev, 0x59);
173 val &= ~0x80;
174 pci_write_byte(dev, 0x59, val);
175}
176
177/**
178 * VT823x: Set one of the GPIO pins.
179 */
180static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
181{
182 uint16_t base;
183 uint8_t val, bit;
184
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000185 if ((gpio >= 12) && (gpio <= 15)) {
186 /* GPIO12-15 -> output */
187 val = pci_read_byte(dev, 0xE4);
188 val |= 0x10;
189 pci_write_byte(dev, 0xE4, val);
190 } else if (gpio == 9) {
191 /* GPIO9 -> Output */
192 val = pci_read_byte(dev, 0xE4);
193 val |= 0x20;
194 pci_write_byte(dev, 0xE4, val);
195 } else {
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000196 fprintf(stderr, "\nERROR: "
197 "VT823x GPIO%02d is not implemented.\n", gpio);
198 return;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000199 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000200
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000201 /* Now raise/drop the GPIO line itself. */
202 bit = 0x01 << (gpio - 8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000203
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000204 /* We need the I/O Base Address for this board's flash enable. */
205 base = pci_read_word(dev, 0x88) & 0xff80;
206
Andriy Gapon65c1b862008-05-22 13:22:45 +0000207 val = INB(base + 0x4D);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000208 if (raise)
209 val |= bit;
210 else
211 val &= ~bit;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000212 OUTB(val, base + 0x4D);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000213}
214
215/**
216 * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
217 *
218 * We don't need to do this when using coreboot, GPIO15 is never lowered there.
219 */
220static int board_via_epia_m(const char *name)
221{
222 struct pci_dev *dev;
223
224 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
225 if (!dev) {
226 fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
227 return -1;
228 }
229
230 /* GPIO15 is connected to write protect. */
231 vt823x_gpio_set(dev, 15, 1);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000232
Uwe Hermanna7e05482007-05-09 10:17:44 +0000233 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000234}
235
Uwe Hermannffec5f32007-08-23 16:08:21 +0000236/**
Luc Verhaegen32707542007-07-04 17:51:49 +0000237 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000238 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000239 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000240 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000241static int board_asus_a7v8x_mx(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000242{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000243 struct pci_dev *dev;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000244
Uwe Hermanna7e05482007-05-09 10:17:44 +0000245 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
Luc Verhaegen32707542007-07-04 17:51:49 +0000246 if (!dev)
247 dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000248 if (!dev) {
Luc Verhaegen32707542007-07-04 17:51:49 +0000249 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000250 return -1;
251 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000252
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000253 vt823x_set_all_writes_to_lpc(dev);
254 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000255
Uwe Hermanna7e05482007-05-09 10:17:44 +0000256 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000257}
258
Uwe Hermannffec5f32007-08-23 16:08:21 +0000259/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000260 * Suited for VIAs EPIA SP and EPIA CN.
Luc Verhaegen97866082008-02-09 02:03:06 +0000261 */
262static int board_via_epia_sp(const char *name)
263{
264 struct pci_dev *dev;
Luc Verhaegen97866082008-02-09 02:03:06 +0000265
266 dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
267 if (!dev) {
268 fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
269 return -1;
270 }
271
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000272 vt823x_set_all_writes_to_lpc(dev);
273
274 return 0;
275}
276
277/**
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000278 * Suited for VIAs EPIA N & NL.
279 */
280static int board_via_epia_n(const char *name)
281{
282 struct pci_dev *dev;
283
284 dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
285 if (!dev) {
286 fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
287 return -1;
288 }
289
290 /* All memory cycles, not just ROM ones, go to LPC */
291 vt823x_set_all_writes_to_lpc(dev);
292
293 /* GPIO9 -> output */
294 vt823x_gpio_set(dev, 9, 1);
295
296 return 0;
297}
298
299/**
Luc Verhaegenb0d0f632009-06-09 18:29:30 +0000300 * Suited for EPoX EP-8K5A2 and Albatron PM266A.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000301 */
302static int board_epox_ep_8k5a2(const char *name)
303{
304 struct pci_dev *dev;
305
306 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
307 if (!dev) {
308 fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
309 return -1;
310 }
311
312 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000313
314 return 0;
315}
316
317/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000318 * Suited for ASUS P5A.
319 *
320 * This is rather nasty code, but there's no way to do this cleanly.
321 * We're basically talking to some unknown device on SMBus, my guess
322 * is that it is the Winbond W83781D that lives near the DIP BIOS.
323 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000324static int board_asus_p5a(const char *name)
325{
326 uint8_t tmp;
327 int i;
328
329#define ASUSP5A_LOOP 5000
330
Andriy Gapon65c1b862008-05-22 13:22:45 +0000331 OUTB(0x00, 0xE807);
332 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000333
Andriy Gapon65c1b862008-05-22 13:22:45 +0000334 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000335
336 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000337 OUTB(0xE1, 0xFF);
338 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000339 break;
340 }
341
342 if (i == ASUSP5A_LOOP) {
343 printf("%s: Unable to contact device.\n", name);
344 return -1;
345 }
346
Andriy Gapon65c1b862008-05-22 13:22:45 +0000347 OUTB(0x20, 0xE801);
348 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000349
Andriy Gapon65c1b862008-05-22 13:22:45 +0000350 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000351
352 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000353 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000354 if (tmp & 0x70)
355 break;
356 }
357
358 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
359 printf("%s: failed to read device.\n", name);
360 return -1;
361 }
362
Andriy Gapon65c1b862008-05-22 13:22:45 +0000363 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000364 tmp &= ~0x02;
365
Andriy Gapon65c1b862008-05-22 13:22:45 +0000366 OUTB(0x00, 0xE807);
367 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000368
Andriy Gapon65c1b862008-05-22 13:22:45 +0000369 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000370
Andriy Gapon65c1b862008-05-22 13:22:45 +0000371 OUTB(0xFF, 0xE800);
372 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000373
Andriy Gapon65c1b862008-05-22 13:22:45 +0000374 OUTB(0x20, 0xE801);
375 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000376
Andriy Gapon65c1b862008-05-22 13:22:45 +0000377 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000378
379 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000380 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000381 if (tmp & 0x70)
382 break;
383 }
384
385 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
386 printf("%s: failed to write to device.\n", name);
387 return -1;
388 }
389
390 return 0;
391}
392
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000393static int board_ibm_x3455(const char *name)
394{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000395 /* Set GPIO lines in the Broadcom HT-1000 southbridge. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000396 /* It's not a superio but it uses the same index/data port method. */
397 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000398
399 return 0;
400}
401
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000402/**
403 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
404 */
405static int board_ga_k8n_sli(const char *name)
406{
407 struct pci_dev *dev;
408 uint32_t base;
409 uint8_t tmp;
410
411 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */
412 if (!dev) {
413 fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n");
414 return -1;
415 }
416
417 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
418
419 /* if anyone knows more about nvidia lpcs, feel free to explain this */
Idwer Volleringfe72cfa2009-06-03 16:41:11 +0000420 tmp = INB(base + 0xE1);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000421 tmp |= 0x05;
Idwer Volleringfe72cfa2009-06-03 16:41:11 +0000422 OUTB(tmp, base + 0xE1);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000423
424 return 0;
425}
426
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000427static int board_hp_dl145_g3_enable(const char *name)
428{
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000429 /* Set GPIO lines in the Broadcom HT-1000 southbridge. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000430 /* GPIO 0 reg from PM regs */
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000431 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000432 /* It's not a superio but it uses the same index/data port method. */
433 sio_mask(0xcd6, 0x44, 0x24, 0x24);
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000434
435 return 0;
436}
437
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000438/**
439 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
440 */
441static int board_epox_ep_bx3(const char *name)
442{
443 uint8_t tmp;
444
445 /* Raise GPIO22. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000446 tmp = INB(0x4036);
447 OUTB(tmp, 0xEB);
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000448
449 tmp |= 0x40;
450
Andriy Gapon65c1b862008-05-22 13:22:45 +0000451 OUTB(tmp, 0x4036);
452 OUTB(tmp, 0xEB);
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000453
454 return 0;
455}
456
Uwe Hermannffec5f32007-08-23 16:08:21 +0000457/**
Uwe Hermann372eeb52007-12-04 21:49:06 +0000458 * Suited for Acorp 6A815EPD.
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000459 */
460static int board_acorp_6a815epd(const char *name)
461{
462 struct pci_dev *dev;
463 uint16_t port;
464 uint8_t val;
465
Uwe Hermann394131e2008-10-18 21:14:13 +0000466 dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000467 if (!dev) {
468 fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n");
469 return -1;
470 }
471
472 /* Use GPIOBASE register to find where the GPIO is mapped. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000473 port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE;
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000474
Andriy Gapon65c1b862008-05-22 13:22:45 +0000475 val = INB(port);
Uwe Hermann394131e2008-10-18 21:14:13 +0000476 val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
477 val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000478 OUTB(val, port);
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000479
480 return 0;
481}
482
483/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000484 * Suited for Artec Group DBE61 and DBE62.
485 */
486static int board_artecgroup_dbe6x(const char *name)
487{
488#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
489#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
490#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
491#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
492#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
493#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
494#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
495#define DBE6x_BOOT_LOC_FLASH (2)
496#define DBE6x_BOOT_LOC_FWHUB (3)
497
498 unsigned long msr[2];
499 int msr_fd;
500 unsigned long boot_loc;
501
502 msr_fd = open("/dev/cpu/0/msr", O_RDWR);
503 if (msr_fd == -1) {
504 perror("open /dev/cpu/0/msr");
505 return -1;
506 }
507
508 if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
509 perror("lseek");
510 close(msr_fd);
511 return -1;
512 }
513
Uwe Hermann394131e2008-10-18 21:14:13 +0000514 if (read(msr_fd, (void *)msr, 8) != 8) {
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000515 perror("read");
516 close(msr_fd);
517 return -1;
518 }
519
520 if ((msr[0] & (DBE6x_BOOT_OP_LATCHED)) ==
521 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
522 boot_loc = DBE6x_BOOT_LOC_FWHUB;
523 else
524 boot_loc = DBE6x_BOOT_LOC_FLASH;
525
526 msr[0] &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
527 msr[0] |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000528 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000529
530 if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
531 perror("lseek");
532 close(msr_fd);
533 return -1;
534 }
535
Uwe Hermann394131e2008-10-18 21:14:13 +0000536 if (write(msr_fd, (void *)msr, 8) != 8) {
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000537 perror("write");
538 close(msr_fd);
539 return -1;
540 }
541
542 close(msr_fd);
543 return 0;
544}
545
Uwe Hermann93f66db2008-05-22 21:19:38 +0000546/**
547 * Set the specified GPIO on the specified ICHx southbridge to high.
548 *
549 * @param name The name of this board.
550 * @param ich_vendor PCI vendor ID of the specified ICHx southbridge.
551 * @param ich_device PCI device ID of the specified ICHx southbridge.
552 * @param gpiobase_reg GPIOBASE register offset in the LPC bridge.
553 * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE.
554 * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0).
555 * @param gpio_bit The bit (GPIO) which shall be set to high.
556 * @return If the write-enable was successful return 0, otherwise return -1.
557 */
558static int ich_gpio_raise(const char *name, uint16_t ich_vendor,
559 uint16_t ich_device, uint8_t gpiobase_reg,
560 uint8_t gp_lvl, uint32_t gp_lvl_bitmask,
561 unsigned int gpio_bit)
562{
563 struct pci_dev *dev;
564 uint16_t gpiobar;
565 uint32_t reg32;
566
Uwe Hermann394131e2008-10-18 21:14:13 +0000567 dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */
Uwe Hermann93f66db2008-05-22 21:19:38 +0000568 if (!dev) {
569 fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n",
570 ich_vendor, ich_device);
571 return -1;
572 }
573
574 /* Use GPIOBASE register to find the I/O space for GPIO. */
575 gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask;
576
577 /* Set specified GPIO to high. */
578 reg32 = INL(gpiobar + gp_lvl);
579 reg32 |= (1 << gpio_bit);
580 OUTL(reg32, gpiobar + gp_lvl);
581
582 return 0;
583}
584
585/**
586 * Suited for ASUS P4B266.
587 */
588static int ich2_gpio22_raise(const char *name)
589{
590 return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22);
591}
592
Peter Stuge09c13332009-02-02 22:55:26 +0000593/**
594 * Suited for MSI MS-7046.
595 */
596static int ich6_gpio19_raise(const char *name)
597{
598 return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19);
599}
600
Stefan Reinauerac378972008-03-17 22:59:40 +0000601static int board_kontron_986lcd_m(const char *name)
602{
603 struct pci_dev *dev;
604 uint16_t gpiobar;
605 uint32_t val;
606
607#define ICH7_GPIO_LVL2 0x38
608
Uwe Hermann394131e2008-10-18 21:14:13 +0000609 dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */
Stefan Reinauerac378972008-03-17 22:59:40 +0000610 if (!dev) {
611 // This will never happen on this board
612 fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n");
613 return -1;
614 }
615
616 /* Use GPIOBASE register to find where the GPIO is mapped. */
617 gpiobar = pci_read_word(dev, 0x48) & 0xfffc;
618
Andriy Gapon65c1b862008-05-22 13:22:45 +0000619 val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */
Stefan Reinauerac378972008-03-17 22:59:40 +0000620 printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val);
621
622 /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1
623 * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0
624 * bit 3 (0x08) = 0 #WP --> block locking = 1
625 * bit 3 (0x08) = 1 #WP --> block locking = 0
626 *
627 * To enable full block locking, you would do:
628 * val &= ~ ((1 << 2) | (1 << 3));
629 */
630 val |= (1 << 2) | (1 << 3);
631
Andriy Gapon65c1b862008-05-22 13:22:45 +0000632 OUTL(val, gpiobar + ICH7_GPIO_LVL2);
Stefan Reinauerac378972008-03-17 22:59:40 +0000633
634 return 0;
635}
636
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000637/**
Peter Stuge4aa71562008-06-11 02:22:42 +0000638 * Suited for:
639 * - BioStar P4M80-M4: Intel P4 + VIA P4M800 + VT8237
Peter Stuge663f1712008-06-13 01:39:45 +0000640 * - GIGABYTE GA-7VT600: AMD K7 + VIA KT600 + VT8237
Peter Stuge4aa71562008-06-11 02:22:42 +0000641 */
642static int board_biostar_p4m80_m4(const char *name)
643{
644 /* enter IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000645 enter_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000646
647 /* select right flash chip */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000648 sio_mask(0x2e, 0x22, 0x80, 0x80);
Peter Stuge4aa71562008-06-11 02:22:42 +0000649
650 /* bit 3: flash chip write enable
651 * bit 7: map flash chip at 1MB-128K (why though? ignoring this.)
652 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000653 sio_mask(0x2e, 0x24, 0x04, 0x04);
Peter Stuge4aa71562008-06-11 02:22:42 +0000654
655 /* exit IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000656 exit_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000657
658 return 0;
659}
660
661/**
Sean Nelsonb20953c2008-08-19 21:51:39 +0000662 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
663 *
664 * Suited for:
665 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
Uwe Hermannab60a432009-05-23 00:56:49 +0000666 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Sean Nelsonb20953c2008-08-19 21:51:39 +0000667 * - MSI KT3 Ultra2: AMD K7 + VIA KT333 + VT8235
668 */
669static int board_msi_kt4v(const char *name)
670{
671 struct pci_dev *dev;
672 uint8_t val;
Sean Nelsonb20953c2008-08-19 21:51:39 +0000673
674 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
675 if (!dev) {
676 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
677 return -1;
678 }
679
680 val = pci_read_byte(dev, 0x59);
681 val &= 0x0c;
682 pci_write_byte(dev, 0x59, val);
683
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000684 vt823x_gpio_set(dev, 12, 1);
685 w836xx_memw_enable(0x2E);
Sean Nelsonb20953c2008-08-19 21:51:39 +0000686
687 return 0;
688}
689
690/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000691 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
692 */
693static int board_soyo_sy_7vca(const char *name)
694{
695 struct pci_dev *dev;
696 uint32_t base;
697 uint8_t tmp;
698
699 /* VT82C686 Power management */
700 dev = pci_dev_find(0x1106, 0x3057);
701 if (!dev) {
702 fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
703 return -1;
704 }
705
706 /* GPO0 output from PM IO base + 0x4C */
707 tmp = pci_read_byte(dev, 0x54);
708 tmp &= ~0x03;
709 pci_write_byte(dev, 0x54, tmp);
710
711 /* PM IO base */
712 base = pci_read_long(dev, 0x48) & 0x0000FF00;
713
714 /* Drop GPO0 */
715 tmp = INB(base + 0x4C);
716 tmp &= ~0x01;
717 OUTB(tmp, base + 0x4C);
718
719 return 0;
720}
721
Uwe Hermann265e7552009-06-21 15:45:34 +0000722static int it8705f_write_enable(uint8_t port, const char *name)
723{
724 enter_conf_mode_ite(port);
725 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
726 exit_conf_mode_ite(port);
727
728 return 0;
729}
730
731/**
Uwe Hermann5ab88892009-06-21 20:50:22 +0000732 * Suited for:
733 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
734 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
Uwe Hermann265e7552009-06-21 15:45:34 +0000735 */
736static int it8705f_write_enable_2e(const char *name)
737{
738 return it8705f_write_enable(0x2e, name);
739}
740
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000741/**
Michael Gold6d52e472009-06-19 13:00:24 +0000742 * Find the runtime registers of an SMSC Super I/O, after verifying its
743 * chip ID.
744 *
745 * Returns the base port of the runtime register block, or 0 on error.
746 */
747static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
748 uint8_t logical_device)
749{
750 uint16_t rt_port = 0;
751
752 /* Verify the chip ID. */
753 OUTB(0x55, sio_port); /* enable configuration */
754 if (sio_read(sio_port, 0x20) != chip_id) {
755 fprintf(stderr, "\nERROR: SMSC super I/O not found.\n");
756 goto out;
757 }
758
759 /* If the runtime block is active, get its address. */
760 sio_write(sio_port, 0x07, logical_device);
761 if (sio_read(sio_port, 0x30) & 1) {
762 rt_port = (sio_read(sio_port, 0x60) << 8)
763 | sio_read(sio_port, 0x61);
764 }
765
766 if (rt_port == 0) {
767 fprintf(stderr, "\nERROR: "
768 "Super I/O runtime interface not available.\n");
769 }
770out:
771 OUTB(0xaa, sio_port); /* disable configuration */
772 return rt_port;
773}
774
775/**
776 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
777 * connected to GP30 on the Super I/O, and TBL# is always high.
778 */
779static int board_mitac_6513wu(const char *name)
780{
781 struct pci_dev *dev;
782 uint16_t rt_port;
783 uint8_t val;
784
785 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
786 if (!dev) {
787 fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
788 return -1;
789 }
790
791 rt_port = smsc_find_runtime(0x4e, 0x54, 0xa);
792 if (rt_port == 0)
793 return -1;
794
795 /* Configure the GPIO pin. */
796 val = INB(rt_port + 0x33); /* GP30 config */
797 val &= ~0x87; /* output, non-inverted, GPIO, push/pull */
798 OUTB(val, rt_port + 0x33);
799
800 /* Disable write protection. */
801 val = INB(rt_port + 0x4d); /* GP3 values */
802 val |= 0x01; /* set GP30 high */
803 OUTB(val, rt_port + 0x4d);
804
805 return 0;
806}
807
808/**
Uwe Hermannffec5f32007-08-23 16:08:21 +0000809 * We use 2 sets of IDs here, you're free to choose which is which. This
810 * is to provide a very high degree of certainty when matching a board on
811 * the basis of subsystem/card IDs. As not every vendor handles
812 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000813 *
Luc Verhaegenc5210162009-04-20 12:38:17 +0000814 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
815 * NULLed if they don't identify the board fully. But please take care to
816 * provide an as complete set of pci ids as possible; autodetection is the
817 * preferred behaviour and we would like to make sure that matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000818 *
Luc Verhaegenc5210162009-04-20 12:38:17 +0000819 * The coreboot ids are used two fold. When running with a coreboot firmware,
820 * the ids uniquely matches the coreboot board identification string. When a
821 * legacy bios is installed and when autodetection is not possible, these ids
822 * can be used to identify the board through the -m command line argument.
823 *
824 * When a board is identified through its coreboot ids (in both cases), the
825 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000826 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000827
Uwe Hermanndeeebe22009-05-08 16:23:34 +0000828/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000829struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermannab60a432009-05-23 00:56:49 +0000830 /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */
831 {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000832 {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e},
Luc Verhaegenb0d0f632009-06-09 18:29:30 +0000833 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", board_epox_ep_8k5a2},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000834 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x},
835 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x},
836 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8-MX SE", board_asus_a7v8x_mx},
837 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise},
838 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a},
839 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "BioStar", "P4M80-M4", board_biostar_p4m80_m4},
Uwe Hermann5ab88892009-06-21 20:50:22 +0000840 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000841 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2},
842 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
843 {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash},
844 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4},
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000845 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000846 {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash},
847 {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash},
Uwe Hermann0495c942009-05-18 22:27:53 +0000848 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash},
849 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash},
Uwe Hermanndeeebe22009-05-08 16:23:34 +0000850 /* SB600 LPC, RD790 North. Neither are specific to the GA-MA790FX-DQ6. The coreboot ID is here to be able to trigger the board enable more easily. */
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000851 {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, "gigabyte", "ma790fx-dq6", "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash},
852 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable},
853 {0x1166, 0x0205, 0x1014, 0x0347, 0, 0, 0, 0, "ibm", "x3455", "IBM", "x3455", board_ibm_x3455},
854 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi},
855 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e},
856 /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */
857 {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m},
858 {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m},
Michael Gold6d52e472009-06-19 13:00:24 +0000859 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu},
Uwe Hermann0b0cc162009-06-19 19:00:48 +0000860 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v},
Uwe Hermannd1129ac2009-05-28 15:07:42 +0000861 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e},
862 {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000863 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise},
Uwe Hermann0b0cc162009-06-19 19:00:48 +0000864 {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
Uwe Hermann265e7552009-06-21 15:45:34 +0000865 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e},
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000866 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000867 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
868 {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},
869 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m},
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000870 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000871 {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp},
872 {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash},
Uwe Hermann5ab88892009-06-21 20:50:22 +0000873
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000874 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000875};
876
Uwe Hermann05fab752009-05-16 23:42:17 +0000877/* Please keep this list alphabetically ordered by vendor/board. */
878const struct board_info boards_ok[] = {
879 /* Verified working boards that don't need write-enables. */
880 { "Abit", "AX8", },
881 { "Advantech", "PCM-5820", },
882 { "ASI", "MB-5BLMP", },
Uwe Hermann24bd1bd2009-06-18 18:25:39 +0000883 { "ASRock", "A770CrossFire", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000884 { "ASUS", "A7N8X Deluxe", },
885 { "ASUS", "A7N8X-E Deluxe", },
886 { "ASUS", "A7V400-MX", },
887 { "ASUS", "A7V8X-MX", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000888 { "ASUS", "A8N-E", },
889 { "ASUS", "A8NE-FM/S", },
Uwe Hermann265c8382009-06-02 13:39:42 +0000890 { "ASUS", "A8N-SLI", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000891 { "ASUS", "A8N-SLI Premium", },
892 { "ASUS", "A8V-E Deluxe", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000893 { "ASUS", "A8V-E SE", },
894 { "ASUS", "M2A-MX", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000895 { "ASUS", "M2A-VM", },
896 { "ASUS", "M2N-E", },
Uwe Hermann50d3f3e2009-05-28 00:00:23 +0000897 { "ASUS", "M2V", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000898 { "ASUS", "P2B", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000899 { "ASUS", "P2B-D", },
900 { "ASUS", "P2B-DS", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000901 { "ASUS", "P2B-F", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000902 { "ASUS", "P2L97-S", },
Uwe Hermann690bcba2009-05-21 17:11:25 +0000903 { "ASUS", "P5B-Deluxe", },
904 { "ASUS", "P6T Deluxe V2", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000905 { "A-Trend", "ATC-6220", },
906 { "BCOM", "WinNET100", },
907 { "GIGABYTE", "GA-6BXC", },
908 { "GIGABYTE", "GA-6BXDU", },
Uwe Hermann690bcba2009-05-21 17:11:25 +0000909 { "GIGABYTE", "GA-6ZMA", },
Uwe Hermannbca6aa12009-06-22 01:37:06 +0000910 { "GIGABYTE", "GA-7ZM", },
Uwe Hermann690bcba2009-05-21 17:11:25 +0000911 { "Intel", "EP80759", },
Uwe Hermann50d3f3e2009-05-28 00:00:23 +0000912 { "Jetway", "J7F4K1G5D-PB", },
Uwe Hermannd1129ac2009-05-28 15:07:42 +0000913 { "MSI", "MS-6570 (K7N2)", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000914 { "MSI", "MS-7065", },
Uwe Hermann690bcba2009-05-21 17:11:25 +0000915 { "MSI", "MS-7168 (Orion)", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000916 { "MSI", "MS-7236 (945PL Neo3)", },
Uwe Hermann265c8382009-06-02 13:39:42 +0000917 { "MSI", "MS-7255 (P4M890M)", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000918 { "MSI", "MS-7345 (P35 Neo2-FIR)", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000919 { "NEC", "PowerMate 2000", },
920 { "PC Engines", "Alix.1c", },
921 { "PC Engines", "Alix.2c2", },
922 { "PC Engines", "Alix.2c3", },
923 { "PC Engines", "Alix.3c3", },
Uwe Hermann50d3f3e2009-05-28 00:00:23 +0000924 { "PC Engines", "Alix.3d3", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000925 { "RCA", "RM4100", },
926 { "Sun", "Blade x6250", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000927 { "Supermicro", "H8QC8", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000928 { "Thomson", "IP1000", },
929 { "T-Online", "S-100", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000930 { "Tyan", "iS5375-1U", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000931 { "Tyan", "S1846", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000932 { "Tyan", "S2881", },
933 { "Tyan", "S2882", },
934 { "Tyan", "S2882-D", },
Uwe Hermanne615e512009-05-18 15:31:10 +0000935 { "Tyan", "S2891", },
936 { "Tyan", "S2892", },
937 { "Tyan", "S2895", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000938 { "Tyan", "S3095", },
939 { "Tyan", "S5180", },
940 { "Tyan", "S5191", },
941 { "Tyan", "S5197", },
942 { "Tyan", "S5211", },
943 { "Tyan", "S5211-1U", },
944 { "Tyan", "S5220", },
945 { "Tyan", "S5375", },
Uwe Hermannab60a432009-05-23 00:56:49 +0000946 { "Tyan", "S5376G2NR/S5376WAG2NR", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000947 { "Tyan", "S5377", },
948 { "Tyan", "S5397", },
Uwe Hermann0b0cc162009-06-19 19:00:48 +0000949 { "VIA", "EPIA-EX15000G", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000950 { "VIA", "EPIA-LN", },
Uwe Hermann0b0cc162009-06-19 19:00:48 +0000951 { "VIA", "EPIA-NX15000G", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000952 { "VIA", "NAB74X0", },
953 { "VIA", "pc2500e", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000954 { "VIA", "VB700X", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000955
956 {},
957};
958
959/* Please keep this list alphabetically ordered by vendor/board. */
960const struct board_info boards_bad[] = {
961 /* Verified non-working boards (for now). */
Uwe Hermann690bcba2009-05-21 17:11:25 +0000962 { "Abit", "IS-10", },
Uwe Hermann50d3f3e2009-05-28 00:00:23 +0000963 { "ASUS", "M3N78 Pro", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000964 { "ASUS", "MEW-AM", },
965 { "ASUS", "MEW-VM", },
966 { "ASUS", "P3B-F", },
Uwe Hermann690bcba2009-05-21 17:11:25 +0000967 { "ASUS", "P5B", },
968 { "ASUS", "P5BV-M", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000969 { "Biostar", "M6TBA", },
Uwe Hermann690bcba2009-05-21 17:11:25 +0000970 { "Boser", "HS-6637", },
Uwe Hermann50d3f3e2009-05-28 00:00:23 +0000971 { "DFI", "855GME-MGF", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000972 { "FIC", "VA-502", },
Uwe Hermann50d3f3e2009-05-28 00:00:23 +0000973 { "MSI", "MS-6178", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000974 { "MSI", "MS-7260 (K9N Neo)", },
975 { "PCCHIPS", "M537DMA33", },
976 { "Soyo", "SY-5VD", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000977 { "Sun", "Fire x4150", },
978 { "Sun", "Fire x4200", },
Uwe Hermann65287d92009-06-04 19:25:54 +0000979 { "Sun", "Fire x4540", },
Uwe Hermann05fab752009-05-16 23:42:17 +0000980 { "Sun", "Fire x4600", },
981
982 {},
983};
984
Uwe Hermanne1aa75e2009-06-18 14:04:44 +0000985/* Please keep this list alphabetically ordered by vendor/board. */
986const struct board_info laptops_ok[] = {
987 /* Verified working laptops. */
988 { "Lenovo", "3000 V100 TF05Cxx", },
989
990 {},
991};
992
993/* Please keep this list alphabetically ordered by vendor/board. */
994const struct board_info laptops_bad[] = {
Uwe Hermann0b0cc162009-06-19 19:00:48 +0000995 /* Verified non-working laptops (for now). */
Uwe Hermanne1aa75e2009-06-18 14:04:44 +0000996 { "Acer", "Aspire One", },
997 { "Dell", "Latitude CPi A366XT", },
Uwe Hermann24bd1bd2009-06-18 18:25:39 +0000998 { "HP/Compaq", "nx9010", },
Uwe Hermanne1aa75e2009-06-18 14:04:44 +0000999 { "IBM/Lenovo", "Thinkpad T40p", },
1000 { "IBM/Lenovo", "240", },
1001
1002 {},
1003};
1004
Uwe Hermannffec5f32007-08-23 16:08:21 +00001005/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001006 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001007 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001008 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001009static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1010 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001011{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001012 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001013 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001014
Uwe Hermanna93045c2009-05-09 00:47:04 +00001015 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001016 if (vendor && (!board->lb_vendor
1017 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001018 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001019
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001020 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001021 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001022
Uwe Hermanna7e05482007-05-09 10:17:44 +00001023 if (!pci_dev_find(board->first_vendor, board->first_device))
1024 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001025
Uwe Hermanna7e05482007-05-09 10:17:44 +00001026 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001027 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001028 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001029
1030 if (vendor)
1031 return board;
1032
1033 if (partmatch) {
1034 /* a second entry has a matching part name */
1035 printf("AMBIGUOUS BOARD NAME: %s\n", part);
1036 printf("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001037 partmatch->lb_vendor, board->lb_vendor);
Peter Stuge6b53fed2008-01-27 16:21:21 +00001038 printf("Please use the full -m vendor:part syntax.\n");
1039 return NULL;
1040 }
1041 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001042 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001043
Peter Stuge6b53fed2008-01-27 16:21:21 +00001044 if (partmatch)
1045 return partmatch;
1046
Peter Stuge00019d92008-07-02 00:59:29 +00001047 printf("\nUnknown vendor:board from coreboot table or -m option: %s:%s\n\n", vendor, part);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001048 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001049}
1050
Uwe Hermannffec5f32007-08-23 16:08:21 +00001051/**
1052 * Match boards on PCI IDs and subsystem IDs.
1053 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001054 */
1055static struct board_pciid_enable *board_match_pci_card_ids(void)
1056{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001057 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001058
Uwe Hermanna93045c2009-05-09 00:47:04 +00001059 for (; board->vendor_name; board++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +00001060 if (!board->first_card_vendor || !board->first_card_device)
1061 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001062
Uwe Hermanna7e05482007-05-09 10:17:44 +00001063 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001064 board->first_card_vendor,
1065 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001066 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001067
Uwe Hermanna7e05482007-05-09 10:17:44 +00001068 if (board->second_vendor) {
1069 if (board->second_card_vendor) {
1070 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001071 board->second_device,
1072 board->second_card_vendor,
1073 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001074 continue;
1075 } else {
1076 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001077 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001078 continue;
1079 }
1080 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001081
Uwe Hermanna7e05482007-05-09 10:17:44 +00001082 return board;
1083 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001084
Uwe Hermanna7e05482007-05-09 10:17:44 +00001085 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001086}
1087
Uwe Hermann372eeb52007-12-04 21:49:06 +00001088int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001089{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001090 struct board_pciid_enable *board = NULL;
1091 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001092
Peter Stuge6b53fed2008-01-27 16:21:21 +00001093 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001094 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001095
Uwe Hermanna7e05482007-05-09 10:17:44 +00001096 if (!board)
1097 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001098
Uwe Hermanna7e05482007-05-09 10:17:44 +00001099 if (board) {
Uwe Hermanna93045c2009-05-09 00:47:04 +00001100 printf("Found board \"%s %s\", enabling flash write... ",
1101 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001102
Uwe Hermanna93045c2009-05-09 00:47:04 +00001103 ret = board->enable(board->vendor_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001104 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001105 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001106 else
1107 printf("OK.\n");
1108 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001109
Uwe Hermanna7e05482007-05-09 10:17:44 +00001110 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001111}