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Nico Huber83693c82016-10-08 22:17:55 +02001--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +02006-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +02008--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
Nico Huber75a707f2018-06-18 16:28:33 +020015with HW.GFX.GMA.Config;
Nico Huber9e96a452019-09-22 20:25:17 +020016with HW.GFX.GMA.Config_Helpers;
Nico Huber83693c82016-10-08 22:17:55 +020017with HW.GFX.GMA.Registers;
18
Nico Huber47ff0692016-11-04 14:29:39 +010019
Nico Huber83693c82016-10-08 22:17:55 +020020private package HW.GFX.GMA.Pipe_Setup
21is
22
Nico Huber83693c82016-10-08 22:17:55 +020023 procedure On
Nico Huberf3e23662016-12-05 21:33:03 +010024 (Pipe : Pipe_Index;
Nico Huber4d592b42026-06-23 12:21:37 +000025 Pipe_Cfg : Pipe_Config;
26 Port_Cfg : Port_Config)
Nico Huber47ff0692016-11-04 14:29:39 +010027 with
Nico Huber4d592b42026-06-23 12:21:37 +000028 Pre => Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Port_Cfg.Mode);
Nico Huber83693c82016-10-08 22:17:55 +020029
Nico Huber7ad2d652016-12-07 15:19:32 +010030 procedure Off (Pipe : Pipe_Index);
Nico Huber83693c82016-10-08 22:17:55 +020031
Nico Huber33912aa2016-12-06 20:36:23 +010032 procedure Legacy_VGA_Off;
33
Nico Huber83693c82016-10-08 22:17:55 +020034 procedure All_Off;
35
Nico Huber4d592b42026-06-23 12:21:37 +000036 -- TODO: Passing `Pipe_Cfg` and `Mode` seems redundant. However,
37 -- the `Pipe_Cfg.Mode` is what the user requested and we
38 -- may have altered that in `Mode`. This should be refac-
39 -- tored to always have a single, synchronized `Mode`.
Nico Huberf7f537e2018-01-02 14:15:43 +010040 procedure Setup_FB
41 (Pipe : Pipe_Index;
Nico Huber4d592b42026-06-23 12:21:37 +000042 Pipe_Cfg : Pipe_Config;
43 Mode : Mode_Type)
Nico Huberf7f537e2018-01-02 14:15:43 +010044 with
Nico Huber4d592b42026-06-23 12:21:37 +000045 Pre => Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Mode);
Nico Huber83693c82016-10-08 22:17:55 +020046
Nico Huber4dc4c612018-01-10 15:55:09 +010047 procedure Update_Cursor
48 (Pipe : Pipe_Index;
49 FB : Framebuffer_Type;
50 Cursor : Cursor_Type);
51 procedure Place_Cursor
52 (Pipe : Pipe_Index;
53 FB : Framebuffer_Type;
Nico Huber1dae2202020-10-05 13:31:25 +020054 Cursor : Cursor_Type;
Nico Huber5903f922020-10-05 14:15:57 +020055 Center : Cursor_Coord;
56 Update : Boolean := False);
Nico Huber4dc4c612018-01-10 15:55:09 +010057
Nico Huber9a4c4c32019-09-16 22:05:11 +020058 type Scaler_Reservation is private;
59 Null_Scaler_Reservation : constant Scaler_Reservation;
60 procedure Reserve_Scaler
61 (Success : out Boolean;
62 Reservation : in out Scaler_Reservation;
63 Pipe : in Pipe_Index);
Nico Huberf361ec82018-06-02 18:01:45 +020064
Nico Huber83693c82016-10-08 22:17:55 +020065private
66
Nico Huber9a4c4c32019-09-16 22:05:11 +020067 type Scaler_Reservation is record
68 Reserved : Boolean;
69 Pipe : Pipe_Index;
70 end record;
71 Null_Scaler_Reservation : constant Scaler_Reservation :=
72 (Reserved => False, Pipe => Pipe_Index'First);
73
Nico Huber83693c82016-10-08 22:17:55 +020074 subtype WM_Levels is Natural range 0 .. 7;
75 type PLANE_WM_Type is array (WM_Levels) of Registers.Registers_Index;
76
77 type Controller_Type is
78 record
Nico Huberf3e23662016-12-05 21:33:03 +010079 Pipe : Pipe_Index;
Nico Huber83693c82016-10-08 22:17:55 +020080 PIPESRC : Registers.Registers_Index;
81 PIPEMISC : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +010082 PF_CTRL : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020083 PF_WIN_POS : Registers.Registers_Index;
84 PF_WIN_SZ : Registers.Registers_Index;
85 DSPCNTR : Registers.Registers_Index;
86 DSPLINOFF : Registers.Registers_Index;
87 DSPSTRIDE : Registers.Registers_Index;
88 DSPSURF : Registers.Registers_Index;
89 DSPTILEOFF : Registers.Registers_Index;
Arthur Heymans960e2392026-03-03 19:45:24 +010090 DSPSIZE : Registers.Registers_Index;
91 DSPPOS : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020092 -- Skylake registers (partially aliased)
93 PLANE_CTL : Registers.Registers_Index;
94 PLANE_OFFSET : Registers.Registers_Index;
95 PLANE_POS : Registers.Registers_Index;
96 PLANE_SIZE : Registers.Registers_Index;
97 PLANE_STRIDE : Registers.Registers_Index;
98 PLANE_SURF : Registers.Registers_Index;
99 PS_CTRL_1 : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +0100100 PS_WIN_POS_1 : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200101 PS_WIN_SZ_1 : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +0100102 PS_CTRL_2 : Registers.Registers_Invalid_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200103 PS_WIN_SZ_2 : Registers.Registers_Invalid_Index;
104 WM_LINETIME : Registers.Registers_Index;
105 PLANE_BUF_CFG : Registers.Registers_Index;
Nico Huber07aab5a2020-10-01 15:06:53 +0200106 PLANE_COLOR_CTL : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200107 PLANE_WM : PLANE_WM_Type;
Nico Huber07aab5a2020-10-01 15:06:53 +0200108 PLANE_2_CTL : Registers.Registers_Index;
109 PLANE_2_OFFSET : Registers.Registers_Index;
110 PLANE_2_POS : Registers.Registers_Index;
111 PLANE_2_SIZE : Registers.Registers_Index;
112 PLANE_2_STRIDE : Registers.Registers_Index;
113 PLANE_2_SURF : Registers.Registers_Index;
114 PLANE_2_BUF_CFG : Registers.Registers_Index;
115 PLANE_2_COLOR_CTL : Registers.Registers_Index;
116 PLANE_2_WM : PLANE_WM_Type;
Nico Huber4dc4c612018-01-10 15:55:09 +0100117 CUR_BUF_CFG : Registers.Registers_Index;
118 CUR_WM : PLANE_WM_Type;
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600119 MBUS_DBOX_CTL : Registers.Registers_Index;
120 PIPE_CHICKEN : Registers.Registers_Index;
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600121 PLANE_AUX_DIST : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200122 end record;
123
Nico Huberf3e23662016-12-05 21:33:03 +0100124 type Controller_Array is array (Pipe_Index) of Controller_Type;
125
Arthur Heymans960e2392026-03-03 19:45:24 +0100126 -- On Gen3 (i945), FBC only works with Plane A, but LVDS and the
127 -- panel fitter are hooked to Pipe B. Hence we want Plane A feeding
128 -- Pipe B, which means swapping the plane register assignments:
129 -- Primary (Pipe A) gets Plane B, Secondary (Pipe B) gets Plane A.
130
Nico Huberf3e23662016-12-05 21:33:03 +0100131 Controllers : constant Controller_Array :=
132 (Primary => Controller_Type'
133 (Pipe => Primary,
Nico Huber83693c82016-10-08 22:17:55 +0200134 PIPESRC => Registers.PIPEASRC,
135 PIPEMISC => Registers.PIPEAMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100136 PF_CTRL => Registers.PFA_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200137 PF_WIN_POS => Registers.PFA_WIN_POS,
138 PF_WIN_SZ => Registers.PFA_WIN_SZ,
Arthur Heymans960e2392026-03-03 19:45:24 +0100139 DSPCNTR =>
140 (if Config.Planes_Pipes_Swapped
141 then Registers.DSPBCNTR else Registers.DSPACNTR),
142 DSPLINOFF =>
143 (if Config.Planes_Pipes_Swapped
144 then Registers.DSPBLINOFF else Registers.DSPALINOFF),
145 DSPSTRIDE =>
146 (if Config.Planes_Pipes_Swapped
147 then Registers.DSPBSTRIDE else Registers.DSPASTRIDE),
148 DSPSURF =>
149 (if Config.Planes_Pipes_Swapped
150 then Registers.DSPBSURF else Registers.DSPASURF),
151 DSPTILEOFF =>
152 (if Config.Planes_Pipes_Swapped
153 then Registers.DSPBTILEOFF else Registers.DSPATILEOFF),
154 DSPSIZE =>
155 (if Config.Planes_Pipes_Swapped
156 then Registers.PLANE_SIZE_1_B else Registers.PLANE_SIZE_1_A),
157 DSPPOS =>
158 (if Config.Planes_Pipes_Swapped
159 then Registers.PLANE_POS_1_B else Registers.PLANE_POS_1_A),
Nico Huber83693c82016-10-08 22:17:55 +0200160 PLANE_CTL => Registers.DSPACNTR,
161 PLANE_OFFSET => Registers.DSPATILEOFF,
162 PLANE_POS => Registers.PLANE_POS_1_A,
163 PLANE_SIZE => Registers.PLANE_SIZE_1_A,
164 PLANE_STRIDE => Registers.DSPASTRIDE,
165 PLANE_SURF => Registers.DSPASURF,
166 PS_CTRL_1 => Registers.PS_CTRL_1_A,
Nico Huber4916e342016-11-04 14:37:53 +0100167 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200168 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_A,
Nico Huber4916e342016-11-04 14:37:53 +0100169 PS_CTRL_2 => Registers.PS_CTRL_2_A,
Nico Huber83693c82016-10-08 22:17:55 +0200170 PS_WIN_SZ_2 => Registers.PS_WIN_SZ_2_A,
171 WM_LINETIME => Registers.WM_LINETIME_A,
172 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_A,
Nico Huber07aab5a2020-10-01 15:06:53 +0200173 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200174 PLANE_WM => PLANE_WM_Type'(
175 Registers.PLANE_WM_1_A_0,
176 Registers.PLANE_WM_1_A_1,
177 Registers.PLANE_WM_1_A_2,
178 Registers.PLANE_WM_1_A_3,
179 Registers.PLANE_WM_1_A_4,
180 Registers.PLANE_WM_1_A_5,
181 Registers.PLANE_WM_1_A_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100182 Registers.PLANE_WM_1_A_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200183 PLANE_2_CTL => Registers.PLANE_CTL_2_A,
184 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_A,
185 PLANE_2_POS => Registers.PLANE_POS_2_A,
186 PLANE_2_SIZE => Registers.PLANE_SIZE_2_A,
187 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_A,
188 PLANE_2_SURF => Registers.PLANE_SURF_2_A,
189 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_A,
190 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_A,
191 PLANE_2_WM => PLANE_WM_Type'(
192 Registers.PLANE_WM_2_A_0,
193 Registers.PLANE_WM_2_A_1,
194 Registers.PLANE_WM_2_A_2,
195 Registers.PLANE_WM_2_A_3,
196 Registers.PLANE_WM_2_A_4,
197 Registers.PLANE_WM_2_A_5,
198 Registers.PLANE_WM_2_A_6,
199 Registers.PLANE_WM_2_A_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100200 CUR_BUF_CFG => Registers.CUR_BUF_CFG_A,
201 CUR_WM => PLANE_WM_Type'(
202 Registers.CUR_WM_A_0,
203 Registers.CUR_WM_A_1,
204 Registers.CUR_WM_A_2,
205 Registers.CUR_WM_A_3,
206 Registers.CUR_WM_A_4,
207 Registers.CUR_WM_A_5,
208 Registers.CUR_WM_A_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600209 Registers.CUR_WM_A_7),
210 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_A,
211 PIPE_CHICKEN => Registers.PIPEA_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600212 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_A),
Nico Huberf3e23662016-12-05 21:33:03 +0100213 Secondary => Controller_Type'
214 (Pipe => Secondary,
Nico Huber83693c82016-10-08 22:17:55 +0200215 PIPESRC => Registers.PIPEBSRC,
216 PIPEMISC => Registers.PIPEBMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100217 PF_CTRL => Registers.PFB_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200218 PF_WIN_POS => Registers.PFB_WIN_POS,
219 PF_WIN_SZ => Registers.PFB_WIN_SZ,
Arthur Heymans960e2392026-03-03 19:45:24 +0100220 DSPCNTR =>
221 (if Config.Planes_Pipes_Swapped
222 then Registers.DSPACNTR else Registers.DSPBCNTR),
223 DSPLINOFF =>
224 (if Config.Planes_Pipes_Swapped
225 then Registers.DSPALINOFF else Registers.DSPBLINOFF),
226 DSPSTRIDE =>
227 (if Config.Planes_Pipes_Swapped
228 then Registers.DSPASTRIDE else Registers.DSPBSTRIDE),
229 DSPSURF =>
230 (if Config.Planes_Pipes_Swapped
231 then Registers.DSPASURF else Registers.DSPBSURF),
232 DSPTILEOFF =>
233 (if Config.Planes_Pipes_Swapped
234 then Registers.DSPATILEOFF else Registers.DSPBTILEOFF),
235 DSPSIZE =>
236 (if Config.Planes_Pipes_Swapped
237 then Registers.PLANE_SIZE_1_A else Registers.PLANE_SIZE_1_B),
238 DSPPOS =>
239 (if Config.Planes_Pipes_Swapped
240 then Registers.PLANE_POS_1_A else Registers.PLANE_POS_1_B),
Nico Huber83693c82016-10-08 22:17:55 +0200241 PLANE_CTL => Registers.DSPBCNTR,
242 PLANE_OFFSET => Registers.DSPBTILEOFF,
243 PLANE_POS => Registers.PLANE_POS_1_B,
244 PLANE_SIZE => Registers.PLANE_SIZE_1_B,
245 PLANE_STRIDE => Registers.DSPBSTRIDE,
246 PLANE_SURF => Registers.DSPBSURF,
247 PS_CTRL_1 => Registers.PS_CTRL_1_B,
Nico Huber4916e342016-11-04 14:37:53 +0100248 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200249 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_B,
Nico Huber4916e342016-11-04 14:37:53 +0100250 PS_CTRL_2 => Registers.PS_CTRL_2_B,
Nico Huber83693c82016-10-08 22:17:55 +0200251 PS_WIN_SZ_2 => Registers.PS_WIN_SZ_2_B,
252 WM_LINETIME => Registers.WM_LINETIME_B,
253 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_B,
Nico Huber07aab5a2020-10-01 15:06:53 +0200254 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200255 PLANE_WM => PLANE_WM_Type'(
256 Registers.PLANE_WM_1_B_0,
257 Registers.PLANE_WM_1_B_1,
258 Registers.PLANE_WM_1_B_2,
259 Registers.PLANE_WM_1_B_3,
260 Registers.PLANE_WM_1_B_4,
261 Registers.PLANE_WM_1_B_5,
262 Registers.PLANE_WM_1_B_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100263 Registers.PLANE_WM_1_B_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200264 PLANE_2_CTL => Registers.PLANE_CTL_2_B,
265 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_B,
266 PLANE_2_POS => Registers.PLANE_POS_2_B,
267 PLANE_2_SIZE => Registers.PLANE_SIZE_2_B,
268 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_B,
269 PLANE_2_SURF => Registers.PLANE_SURF_2_B,
270 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_B,
271 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_B,
272 PLANE_2_WM => PLANE_WM_Type'(
273 Registers.PLANE_WM_2_B_0,
274 Registers.PLANE_WM_2_B_1,
275 Registers.PLANE_WM_2_B_2,
276 Registers.PLANE_WM_2_B_3,
277 Registers.PLANE_WM_2_B_4,
278 Registers.PLANE_WM_2_B_5,
279 Registers.PLANE_WM_2_B_6,
280 Registers.PLANE_WM_2_B_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100281 CUR_BUF_CFG => Registers.CUR_BUF_CFG_B,
282 CUR_WM => PLANE_WM_Type'(
283 Registers.CUR_WM_B_0,
284 Registers.CUR_WM_B_1,
285 Registers.CUR_WM_B_2,
286 Registers.CUR_WM_B_3,
287 Registers.CUR_WM_B_4,
288 Registers.CUR_WM_B_5,
289 Registers.CUR_WM_B_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600290 Registers.CUR_WM_B_7),
291 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_B,
292 PIPE_CHICKEN => Registers.PIPEB_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600293 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_B),
Nico Huberf3e23662016-12-05 21:33:03 +0100294 Tertiary => Controller_Type'
295 (Pipe => Tertiary,
Nico Huber83693c82016-10-08 22:17:55 +0200296 PIPESRC => Registers.PIPECSRC,
297 PIPEMISC => Registers.PIPECMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100298 PF_CTRL => Registers.PFC_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200299 PF_WIN_POS => Registers.PFC_WIN_POS,
300 PF_WIN_SZ => Registers.PFC_WIN_SZ,
301 DSPCNTR => Registers.DSPCCNTR,
302 DSPLINOFF => Registers.DSPCLINOFF,
303 DSPSTRIDE => Registers.DSPCSTRIDE,
304 DSPSURF => Registers.DSPCSURF,
305 DSPTILEOFF => Registers.DSPCTILEOFF,
Arthur Heymans960e2392026-03-03 19:45:24 +0100306 DSPSIZE => Registers.PLANE_SIZE_1_C,
307 DSPPOS => Registers.PLANE_POS_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200308 PLANE_CTL => Registers.DSPCCNTR,
309 PLANE_OFFSET => Registers.DSPCTILEOFF,
310 PLANE_POS => Registers.PLANE_POS_1_C,
311 PLANE_SIZE => Registers.PLANE_SIZE_1_C,
312 PLANE_STRIDE => Registers.DSPCSTRIDE,
313 PLANE_SURF => Registers.DSPCSURF,
314 PS_CTRL_1 => Registers.PS_CTRL_1_C,
Nico Huber4916e342016-11-04 14:37:53 +0100315 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200316 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_C,
Nico Huber4916e342016-11-04 14:37:53 +0100317 PS_CTRL_2 => Registers.Invalid_Register,
Nico Huber83693c82016-10-08 22:17:55 +0200318 PS_WIN_SZ_2 => Registers.Invalid_Register,
319 WM_LINETIME => Registers.WM_LINETIME_C,
320 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_C,
Nico Huber07aab5a2020-10-01 15:06:53 +0200321 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200322 PLANE_WM => PLANE_WM_Type'(
323 Registers.PLANE_WM_1_C_0,
324 Registers.PLANE_WM_1_C_1,
325 Registers.PLANE_WM_1_C_2,
326 Registers.PLANE_WM_1_C_3,
327 Registers.PLANE_WM_1_C_4,
328 Registers.PLANE_WM_1_C_5,
329 Registers.PLANE_WM_1_C_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100330 Registers.PLANE_WM_1_C_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200331 PLANE_2_CTL => Registers.PLANE_CTL_2_C,
332 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_C,
333 PLANE_2_POS => Registers.PLANE_POS_2_C,
334 PLANE_2_SIZE => Registers.PLANE_SIZE_2_C,
335 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_C,
336 PLANE_2_SURF => Registers.PLANE_SURF_2_C,
337 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_C,
338 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_C,
339 PLANE_2_WM => PLANE_WM_Type'(
340 Registers.PLANE_WM_2_C_0,
341 Registers.PLANE_WM_2_C_1,
342 Registers.PLANE_WM_2_C_2,
343 Registers.PLANE_WM_2_C_3,
344 Registers.PLANE_WM_2_C_4,
345 Registers.PLANE_WM_2_C_5,
346 Registers.PLANE_WM_2_C_6,
347 Registers.PLANE_WM_2_C_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100348 CUR_BUF_CFG => Registers.CUR_BUF_CFG_C,
349 CUR_WM => PLANE_WM_Type'(
350 Registers.CUR_WM_C_0,
351 Registers.CUR_WM_C_1,
352 Registers.CUR_WM_C_2,
353 Registers.CUR_WM_C_3,
354 Registers.CUR_WM_C_4,
355 Registers.CUR_WM_C_5,
356 Registers.CUR_WM_C_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600357 Registers.CUR_WM_C_7),
358 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_C,
359 PIPE_CHICKEN => Registers.PIPEC_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600360 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_C));
Nico Huber83693c82016-10-08 22:17:55 +0200361
Nico Huber75a707f2018-06-18 16:28:33 +0200362 type Cursor_Regs is record
363 CTL : Registers.Registers_Index;
364 BASE : Registers.Registers_Index;
365 POS : Registers.Registers_Index;
366 FBC_CTL : Registers.Registers_Invalid_Index;
367 end record;
368
369 function Cursors (Pipe : Pipe_Index) return Cursor_Regs is
370 (if not Config.Has_Ivybridge_Cursors then
371 (if Pipe = Primary then
372 (CTL => Registers.CURACNTR,
373 BASE => Registers.CURABASE,
374 POS => Registers.CURAPOS,
375 FBC_CTL => Registers.Invalid_Register)
376 else
377 (CTL => Registers.CURBCNTR,
378 BASE => Registers.CURBBASE,
379 POS => Registers.CURBPOS,
380 FBC_CTL => Registers.Invalid_Register))
381 else
382 (if Pipe = Primary then
383 (CTL => Registers.CUR_CTL_A,
384 BASE => Registers.CUR_BASE_A,
385 POS => Registers.CUR_POS_A,
386 FBC_CTL => Registers.CUR_FBC_CTL_A)
387 elsif Pipe = Secondary then
388 (CTL => Registers.CUR_CTL_B,
389 BASE => Registers.CUR_BASE_B,
390 POS => Registers.CUR_POS_B,
391 FBC_CTL => Registers.CUR_FBC_CTL_B)
392 else
393 (CTL => Registers.CUR_CTL_C,
394 BASE => Registers.CUR_BASE_C,
395 POS => Registers.CUR_POS_C,
396 FBC_CTL => Registers.CUR_FBC_CTL_C)));
397
Nico Huber83693c82016-10-08 22:17:55 +0200398end HW.GFX.GMA.Pipe_Setup;