commit 0da761a02127cef9dbf78a8ac270aa9e5b5de61d
author Tim Wawrzynczak <twawrzynczak@chromium.org> Fri Sep 09 10:42:36 2022 -0600
committer Nico Huber <nico.h@gmx.de> Sat Jun 06 10:28:13 2026 +0000
tree eda6294bfa545e4e5fa9f4e803b2d46f3e08642f
parent 8b381fc278d7ce59d30f9f0d09b795f0e0ca4899

gma pipe_setup: Update for TGL & ADL

Tiger Lake requires some differences in plane programming over prior
generations, including new chicken bits, wider watermarks, MBUS DBOX
programming and a few bits moved around. Alder Lake brings some more
chicken bits and requires arb-slot programming.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I93329c0a012da83abc379d6782fabe257dc180f3
Reviewed-on: https://review.sourcearcade.org/c/libgfxinit/+/458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>

common/hw-gfx-gma-pipe_setup.ads

diff --git a/common/hw-gfx-gma-pipe_setup.ads b/common/hw-gfx-gma-pipe_setup.ads
index f047a64..bdb1700 100644
--- a/common/hw-gfx-gma-pipe_setup.ads
+++ b/common/hw-gfx-gma-pipe_setup.ads
@@ -102,6 +102,10 @@
          PLANE_WM          : PLANE_WM_Type;
          CUR_BUF_CFG       : Registers.Registers_Index;
          CUR_WM            : PLANE_WM_Type;
+         MBUS_DBOX_CTL     : Registers.Registers_Index;
+         PIPE_CHICKEN      : Registers.Registers_Index;
+         PLANE_COLOR_CTL   : Registers.Registers_Index;
+         PLANE_AUX_DIST    : Registers.Registers_Index;
       end record;
 
    type Controller_Array is array (Pipe_Index) of Controller_Type;
@@ -172,7 +176,11 @@
                               Registers.CUR_WM_A_4,
                               Registers.CUR_WM_A_5,
                               Registers.CUR_WM_A_6,
-                              Registers.CUR_WM_A_7)),
+                              Registers.CUR_WM_A_7),
+         MBUS_DBOX_CTL     => Registers.PIPE_MBUS_DBOX_CTL_A,
+         PIPE_CHICKEN      => Registers.PIPEA_CHICKEN,
+         PLANE_COLOR_CTL   => Registers.PLANE_COLOR_CTL_1_A,
+         PLANE_AUX_DIST    => Registers.PLANE_AUX_DIST_1_A),
       Secondary => Controller_Type'
         (Pipe              => Secondary,
          PIPESRC           => Registers.PIPEBSRC,
@@ -233,7 +241,11 @@
                               Registers.CUR_WM_B_4,
                               Registers.CUR_WM_B_5,
                               Registers.CUR_WM_B_6,
-                              Registers.CUR_WM_B_7)),
+                              Registers.CUR_WM_B_7),
+         MBUS_DBOX_CTL     => Registers.PIPE_MBUS_DBOX_CTL_B,
+         PIPE_CHICKEN      => Registers.PIPEB_CHICKEN,
+         PLANE_COLOR_CTL   => Registers.PLANE_COLOR_CTL_1_B,
+         PLANE_AUX_DIST    => Registers.PLANE_AUX_DIST_1_B),
       Tertiary => Controller_Type'
         (Pipe              => Tertiary,
          PIPESRC           => Registers.PIPECSRC,
@@ -280,7 +292,11 @@
                               Registers.CUR_WM_C_4,
                               Registers.CUR_WM_C_5,
                               Registers.CUR_WM_C_6,
-                              Registers.CUR_WM_C_7)));
+                              Registers.CUR_WM_C_7),
+         MBUS_DBOX_CTL     => Registers.PIPE_MBUS_DBOX_CTL_C,
+         PIPE_CHICKEN      => Registers.PIPEC_CHICKEN,
+         PLANE_COLOR_CTL   => Registers.PLANE_COLOR_CTL_1_C,
+         PLANE_AUX_DIST    => Registers.PLANE_AUX_DIST_1_C));
 
    type Cursor_Regs is record
       CTL      : Registers.Registers_Index;