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Nico Huber83693c82016-10-08 22:17:55 +02001--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +02006-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +02008--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
Nico Huber75a707f2018-06-18 16:28:33 +020015with HW.GFX.GMA.Config;
Nico Huber9e96a452019-09-22 20:25:17 +020016with HW.GFX.GMA.Config_Helpers;
Nico Huber83693c82016-10-08 22:17:55 +020017with HW.GFX.GMA.Registers;
18
Nico Huber47ff0692016-11-04 14:29:39 +010019
Nico Huber83693c82016-10-08 22:17:55 +020020private package HW.GFX.GMA.Pipe_Setup
21is
22
Nico Huber83693c82016-10-08 22:17:55 +020023 procedure On
Nico Huberf3e23662016-12-05 21:33:03 +010024 (Pipe : Pipe_Index;
Nico Huber4d592b42026-06-23 12:21:37 +000025 Pipe_Cfg : Pipe_Config;
26 Port_Cfg : Port_Config)
Nico Huber47ff0692016-11-04 14:29:39 +010027 with
Nico Huber4d592b42026-06-23 12:21:37 +000028 Pre => Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Port_Cfg.Mode);
Nico Huber83693c82016-10-08 22:17:55 +020029
Nico Huber7ad2d652016-12-07 15:19:32 +010030 procedure Off (Pipe : Pipe_Index);
Nico Huber83693c82016-10-08 22:17:55 +020031
Nico Huber33912aa2016-12-06 20:36:23 +010032 procedure Legacy_VGA_Off;
33
Nico Huber83693c82016-10-08 22:17:55 +020034 procedure All_Off;
35
Nico Huber4d592b42026-06-23 12:21:37 +000036 -- TODO: Passing `Pipe_Cfg` and `Mode` seems redundant. However,
37 -- the `Pipe_Cfg.Mode` is what the user requested and we
38 -- may have altered that in `Mode`. This should be refac-
39 -- tored to always have a single, synchronized `Mode`.
Nico Huberf7f537e2018-01-02 14:15:43 +010040 procedure Setup_FB
41 (Pipe : Pipe_Index;
Nico Huber4d592b42026-06-23 12:21:37 +000042 Pipe_Cfg : Pipe_Config;
43 Mode : Mode_Type)
Nico Huberf7f537e2018-01-02 14:15:43 +010044 with
Nico Huber4d592b42026-06-23 12:21:37 +000045 Pre => Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Mode);
Nico Huber83693c82016-10-08 22:17:55 +020046
Nico Huber4dc4c612018-01-10 15:55:09 +010047 procedure Update_Cursor
48 (Pipe : Pipe_Index;
49 FB : Framebuffer_Type;
50 Cursor : Cursor_Type);
51 procedure Place_Cursor
52 (Pipe : Pipe_Index;
53 FB : Framebuffer_Type;
Nico Huber1dae2202020-10-05 13:31:25 +020054 Cursor : Cursor_Type;
55 Center : Cursor_Coord);
Nico Huber4dc4c612018-01-10 15:55:09 +010056
Nico Huber9a4c4c32019-09-16 22:05:11 +020057 type Scaler_Reservation is private;
58 Null_Scaler_Reservation : constant Scaler_Reservation;
59 procedure Reserve_Scaler
60 (Success : out Boolean;
61 Reservation : in out Scaler_Reservation;
62 Pipe : in Pipe_Index);
Nico Huberf361ec82018-06-02 18:01:45 +020063
Nico Huber83693c82016-10-08 22:17:55 +020064private
65
Nico Huber9a4c4c32019-09-16 22:05:11 +020066 type Scaler_Reservation is record
67 Reserved : Boolean;
68 Pipe : Pipe_Index;
69 end record;
70 Null_Scaler_Reservation : constant Scaler_Reservation :=
71 (Reserved => False, Pipe => Pipe_Index'First);
72
Nico Huber83693c82016-10-08 22:17:55 +020073 subtype WM_Levels is Natural range 0 .. 7;
74 type PLANE_WM_Type is array (WM_Levels) of Registers.Registers_Index;
75
76 type Controller_Type is
77 record
Nico Huberf3e23662016-12-05 21:33:03 +010078 Pipe : Pipe_Index;
Nico Huber83693c82016-10-08 22:17:55 +020079 PIPESRC : Registers.Registers_Index;
80 PIPEMISC : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +010081 PF_CTRL : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020082 PF_WIN_POS : Registers.Registers_Index;
83 PF_WIN_SZ : Registers.Registers_Index;
84 DSPCNTR : Registers.Registers_Index;
85 DSPLINOFF : Registers.Registers_Index;
86 DSPSTRIDE : Registers.Registers_Index;
87 DSPSURF : Registers.Registers_Index;
88 DSPTILEOFF : Registers.Registers_Index;
Arthur Heymans960e2392026-03-03 19:45:24 +010089 DSPSIZE : Registers.Registers_Index;
90 DSPPOS : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020091 -- Skylake registers (partially aliased)
92 PLANE_CTL : Registers.Registers_Index;
93 PLANE_OFFSET : Registers.Registers_Index;
94 PLANE_POS : Registers.Registers_Index;
95 PLANE_SIZE : Registers.Registers_Index;
96 PLANE_STRIDE : Registers.Registers_Index;
97 PLANE_SURF : Registers.Registers_Index;
98 PS_CTRL_1 : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +010099 PS_WIN_POS_1 : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200100 PS_WIN_SZ_1 : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +0100101 PS_CTRL_2 : Registers.Registers_Invalid_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200102 PS_WIN_SZ_2 : Registers.Registers_Invalid_Index;
103 WM_LINETIME : Registers.Registers_Index;
104 PLANE_BUF_CFG : Registers.Registers_Index;
Nico Huber07aab5a2020-10-01 15:06:53 +0200105 PLANE_COLOR_CTL : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200106 PLANE_WM : PLANE_WM_Type;
Nico Huber07aab5a2020-10-01 15:06:53 +0200107 PLANE_2_CTL : Registers.Registers_Index;
108 PLANE_2_OFFSET : Registers.Registers_Index;
109 PLANE_2_POS : Registers.Registers_Index;
110 PLANE_2_SIZE : Registers.Registers_Index;
111 PLANE_2_STRIDE : Registers.Registers_Index;
112 PLANE_2_SURF : Registers.Registers_Index;
113 PLANE_2_BUF_CFG : Registers.Registers_Index;
114 PLANE_2_COLOR_CTL : Registers.Registers_Index;
115 PLANE_2_WM : PLANE_WM_Type;
Nico Huber4dc4c612018-01-10 15:55:09 +0100116 CUR_BUF_CFG : Registers.Registers_Index;
117 CUR_WM : PLANE_WM_Type;
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600118 MBUS_DBOX_CTL : Registers.Registers_Index;
119 PIPE_CHICKEN : Registers.Registers_Index;
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600120 PLANE_AUX_DIST : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200121 end record;
122
Nico Huberf3e23662016-12-05 21:33:03 +0100123 type Controller_Array is array (Pipe_Index) of Controller_Type;
124
Arthur Heymans960e2392026-03-03 19:45:24 +0100125 -- On Gen3 (i945), FBC only works with Plane A, but LVDS and the
126 -- panel fitter are hooked to Pipe B. Hence we want Plane A feeding
127 -- Pipe B, which means swapping the plane register assignments:
128 -- Primary (Pipe A) gets Plane B, Secondary (Pipe B) gets Plane A.
129
Nico Huberf3e23662016-12-05 21:33:03 +0100130 Controllers : constant Controller_Array :=
131 (Primary => Controller_Type'
132 (Pipe => Primary,
Nico Huber83693c82016-10-08 22:17:55 +0200133 PIPESRC => Registers.PIPEASRC,
134 PIPEMISC => Registers.PIPEAMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100135 PF_CTRL => Registers.PFA_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200136 PF_WIN_POS => Registers.PFA_WIN_POS,
137 PF_WIN_SZ => Registers.PFA_WIN_SZ,
Arthur Heymans960e2392026-03-03 19:45:24 +0100138 DSPCNTR =>
139 (if Config.Planes_Pipes_Swapped
140 then Registers.DSPBCNTR else Registers.DSPACNTR),
141 DSPLINOFF =>
142 (if Config.Planes_Pipes_Swapped
143 then Registers.DSPBLINOFF else Registers.DSPALINOFF),
144 DSPSTRIDE =>
145 (if Config.Planes_Pipes_Swapped
146 then Registers.DSPBSTRIDE else Registers.DSPASTRIDE),
147 DSPSURF =>
148 (if Config.Planes_Pipes_Swapped
149 then Registers.DSPBSURF else Registers.DSPASURF),
150 DSPTILEOFF =>
151 (if Config.Planes_Pipes_Swapped
152 then Registers.DSPBTILEOFF else Registers.DSPATILEOFF),
153 DSPSIZE =>
154 (if Config.Planes_Pipes_Swapped
155 then Registers.PLANE_SIZE_1_B else Registers.PLANE_SIZE_1_A),
156 DSPPOS =>
157 (if Config.Planes_Pipes_Swapped
158 then Registers.PLANE_POS_1_B else Registers.PLANE_POS_1_A),
Nico Huber83693c82016-10-08 22:17:55 +0200159 PLANE_CTL => Registers.DSPACNTR,
160 PLANE_OFFSET => Registers.DSPATILEOFF,
161 PLANE_POS => Registers.PLANE_POS_1_A,
162 PLANE_SIZE => Registers.PLANE_SIZE_1_A,
163 PLANE_STRIDE => Registers.DSPASTRIDE,
164 PLANE_SURF => Registers.DSPASURF,
165 PS_CTRL_1 => Registers.PS_CTRL_1_A,
Nico Huber4916e342016-11-04 14:37:53 +0100166 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200167 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_A,
Nico Huber4916e342016-11-04 14:37:53 +0100168 PS_CTRL_2 => Registers.PS_CTRL_2_A,
Nico Huber83693c82016-10-08 22:17:55 +0200169 PS_WIN_SZ_2 => Registers.PS_WIN_SZ_2_A,
170 WM_LINETIME => Registers.WM_LINETIME_A,
171 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_A,
Nico Huber07aab5a2020-10-01 15:06:53 +0200172 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200173 PLANE_WM => PLANE_WM_Type'(
174 Registers.PLANE_WM_1_A_0,
175 Registers.PLANE_WM_1_A_1,
176 Registers.PLANE_WM_1_A_2,
177 Registers.PLANE_WM_1_A_3,
178 Registers.PLANE_WM_1_A_4,
179 Registers.PLANE_WM_1_A_5,
180 Registers.PLANE_WM_1_A_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100181 Registers.PLANE_WM_1_A_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200182 PLANE_2_CTL => Registers.PLANE_CTL_2_A,
183 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_A,
184 PLANE_2_POS => Registers.PLANE_POS_2_A,
185 PLANE_2_SIZE => Registers.PLANE_SIZE_2_A,
186 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_A,
187 PLANE_2_SURF => Registers.PLANE_SURF_2_A,
188 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_A,
189 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_A,
190 PLANE_2_WM => PLANE_WM_Type'(
191 Registers.PLANE_WM_2_A_0,
192 Registers.PLANE_WM_2_A_1,
193 Registers.PLANE_WM_2_A_2,
194 Registers.PLANE_WM_2_A_3,
195 Registers.PLANE_WM_2_A_4,
196 Registers.PLANE_WM_2_A_5,
197 Registers.PLANE_WM_2_A_6,
198 Registers.PLANE_WM_2_A_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100199 CUR_BUF_CFG => Registers.CUR_BUF_CFG_A,
200 CUR_WM => PLANE_WM_Type'(
201 Registers.CUR_WM_A_0,
202 Registers.CUR_WM_A_1,
203 Registers.CUR_WM_A_2,
204 Registers.CUR_WM_A_3,
205 Registers.CUR_WM_A_4,
206 Registers.CUR_WM_A_5,
207 Registers.CUR_WM_A_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600208 Registers.CUR_WM_A_7),
209 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_A,
210 PIPE_CHICKEN => Registers.PIPEA_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600211 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_A),
Nico Huberf3e23662016-12-05 21:33:03 +0100212 Secondary => Controller_Type'
213 (Pipe => Secondary,
Nico Huber83693c82016-10-08 22:17:55 +0200214 PIPESRC => Registers.PIPEBSRC,
215 PIPEMISC => Registers.PIPEBMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100216 PF_CTRL => Registers.PFB_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200217 PF_WIN_POS => Registers.PFB_WIN_POS,
218 PF_WIN_SZ => Registers.PFB_WIN_SZ,
Arthur Heymans960e2392026-03-03 19:45:24 +0100219 DSPCNTR =>
220 (if Config.Planes_Pipes_Swapped
221 then Registers.DSPACNTR else Registers.DSPBCNTR),
222 DSPLINOFF =>
223 (if Config.Planes_Pipes_Swapped
224 then Registers.DSPALINOFF else Registers.DSPBLINOFF),
225 DSPSTRIDE =>
226 (if Config.Planes_Pipes_Swapped
227 then Registers.DSPASTRIDE else Registers.DSPBSTRIDE),
228 DSPSURF =>
229 (if Config.Planes_Pipes_Swapped
230 then Registers.DSPASURF else Registers.DSPBSURF),
231 DSPTILEOFF =>
232 (if Config.Planes_Pipes_Swapped
233 then Registers.DSPATILEOFF else Registers.DSPBTILEOFF),
234 DSPSIZE =>
235 (if Config.Planes_Pipes_Swapped
236 then Registers.PLANE_SIZE_1_A else Registers.PLANE_SIZE_1_B),
237 DSPPOS =>
238 (if Config.Planes_Pipes_Swapped
239 then Registers.PLANE_POS_1_A else Registers.PLANE_POS_1_B),
Nico Huber83693c82016-10-08 22:17:55 +0200240 PLANE_CTL => Registers.DSPBCNTR,
241 PLANE_OFFSET => Registers.DSPBTILEOFF,
242 PLANE_POS => Registers.PLANE_POS_1_B,
243 PLANE_SIZE => Registers.PLANE_SIZE_1_B,
244 PLANE_STRIDE => Registers.DSPBSTRIDE,
245 PLANE_SURF => Registers.DSPBSURF,
246 PS_CTRL_1 => Registers.PS_CTRL_1_B,
Nico Huber4916e342016-11-04 14:37:53 +0100247 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200248 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_B,
Nico Huber4916e342016-11-04 14:37:53 +0100249 PS_CTRL_2 => Registers.PS_CTRL_2_B,
Nico Huber83693c82016-10-08 22:17:55 +0200250 PS_WIN_SZ_2 => Registers.PS_WIN_SZ_2_B,
251 WM_LINETIME => Registers.WM_LINETIME_B,
252 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_B,
Nico Huber07aab5a2020-10-01 15:06:53 +0200253 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200254 PLANE_WM => PLANE_WM_Type'(
255 Registers.PLANE_WM_1_B_0,
256 Registers.PLANE_WM_1_B_1,
257 Registers.PLANE_WM_1_B_2,
258 Registers.PLANE_WM_1_B_3,
259 Registers.PLANE_WM_1_B_4,
260 Registers.PLANE_WM_1_B_5,
261 Registers.PLANE_WM_1_B_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100262 Registers.PLANE_WM_1_B_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200263 PLANE_2_CTL => Registers.PLANE_CTL_2_B,
264 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_B,
265 PLANE_2_POS => Registers.PLANE_POS_2_B,
266 PLANE_2_SIZE => Registers.PLANE_SIZE_2_B,
267 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_B,
268 PLANE_2_SURF => Registers.PLANE_SURF_2_B,
269 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_B,
270 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_B,
271 PLANE_2_WM => PLANE_WM_Type'(
272 Registers.PLANE_WM_2_B_0,
273 Registers.PLANE_WM_2_B_1,
274 Registers.PLANE_WM_2_B_2,
275 Registers.PLANE_WM_2_B_3,
276 Registers.PLANE_WM_2_B_4,
277 Registers.PLANE_WM_2_B_5,
278 Registers.PLANE_WM_2_B_6,
279 Registers.PLANE_WM_2_B_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100280 CUR_BUF_CFG => Registers.CUR_BUF_CFG_B,
281 CUR_WM => PLANE_WM_Type'(
282 Registers.CUR_WM_B_0,
283 Registers.CUR_WM_B_1,
284 Registers.CUR_WM_B_2,
285 Registers.CUR_WM_B_3,
286 Registers.CUR_WM_B_4,
287 Registers.CUR_WM_B_5,
288 Registers.CUR_WM_B_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600289 Registers.CUR_WM_B_7),
290 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_B,
291 PIPE_CHICKEN => Registers.PIPEB_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600292 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_B),
Nico Huberf3e23662016-12-05 21:33:03 +0100293 Tertiary => Controller_Type'
294 (Pipe => Tertiary,
Nico Huber83693c82016-10-08 22:17:55 +0200295 PIPESRC => Registers.PIPECSRC,
296 PIPEMISC => Registers.PIPECMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100297 PF_CTRL => Registers.PFC_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200298 PF_WIN_POS => Registers.PFC_WIN_POS,
299 PF_WIN_SZ => Registers.PFC_WIN_SZ,
300 DSPCNTR => Registers.DSPCCNTR,
301 DSPLINOFF => Registers.DSPCLINOFF,
302 DSPSTRIDE => Registers.DSPCSTRIDE,
303 DSPSURF => Registers.DSPCSURF,
304 DSPTILEOFF => Registers.DSPCTILEOFF,
Arthur Heymans960e2392026-03-03 19:45:24 +0100305 DSPSIZE => Registers.PLANE_SIZE_1_C,
306 DSPPOS => Registers.PLANE_POS_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200307 PLANE_CTL => Registers.DSPCCNTR,
308 PLANE_OFFSET => Registers.DSPCTILEOFF,
309 PLANE_POS => Registers.PLANE_POS_1_C,
310 PLANE_SIZE => Registers.PLANE_SIZE_1_C,
311 PLANE_STRIDE => Registers.DSPCSTRIDE,
312 PLANE_SURF => Registers.DSPCSURF,
313 PS_CTRL_1 => Registers.PS_CTRL_1_C,
Nico Huber4916e342016-11-04 14:37:53 +0100314 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200315 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_C,
Nico Huber4916e342016-11-04 14:37:53 +0100316 PS_CTRL_2 => Registers.Invalid_Register,
Nico Huber83693c82016-10-08 22:17:55 +0200317 PS_WIN_SZ_2 => Registers.Invalid_Register,
318 WM_LINETIME => Registers.WM_LINETIME_C,
319 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_C,
Nico Huber07aab5a2020-10-01 15:06:53 +0200320 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200321 PLANE_WM => PLANE_WM_Type'(
322 Registers.PLANE_WM_1_C_0,
323 Registers.PLANE_WM_1_C_1,
324 Registers.PLANE_WM_1_C_2,
325 Registers.PLANE_WM_1_C_3,
326 Registers.PLANE_WM_1_C_4,
327 Registers.PLANE_WM_1_C_5,
328 Registers.PLANE_WM_1_C_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100329 Registers.PLANE_WM_1_C_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200330 PLANE_2_CTL => Registers.PLANE_CTL_2_C,
331 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_C,
332 PLANE_2_POS => Registers.PLANE_POS_2_C,
333 PLANE_2_SIZE => Registers.PLANE_SIZE_2_C,
334 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_C,
335 PLANE_2_SURF => Registers.PLANE_SURF_2_C,
336 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_C,
337 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_C,
338 PLANE_2_WM => PLANE_WM_Type'(
339 Registers.PLANE_WM_2_C_0,
340 Registers.PLANE_WM_2_C_1,
341 Registers.PLANE_WM_2_C_2,
342 Registers.PLANE_WM_2_C_3,
343 Registers.PLANE_WM_2_C_4,
344 Registers.PLANE_WM_2_C_5,
345 Registers.PLANE_WM_2_C_6,
346 Registers.PLANE_WM_2_C_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100347 CUR_BUF_CFG => Registers.CUR_BUF_CFG_C,
348 CUR_WM => PLANE_WM_Type'(
349 Registers.CUR_WM_C_0,
350 Registers.CUR_WM_C_1,
351 Registers.CUR_WM_C_2,
352 Registers.CUR_WM_C_3,
353 Registers.CUR_WM_C_4,
354 Registers.CUR_WM_C_5,
355 Registers.CUR_WM_C_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600356 Registers.CUR_WM_C_7),
357 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_C,
358 PIPE_CHICKEN => Registers.PIPEC_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600359 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_C));
Nico Huber83693c82016-10-08 22:17:55 +0200360
Nico Huber75a707f2018-06-18 16:28:33 +0200361 type Cursor_Regs is record
362 CTL : Registers.Registers_Index;
363 BASE : Registers.Registers_Index;
364 POS : Registers.Registers_Index;
365 FBC_CTL : Registers.Registers_Invalid_Index;
366 end record;
367
368 function Cursors (Pipe : Pipe_Index) return Cursor_Regs is
369 (if not Config.Has_Ivybridge_Cursors then
370 (if Pipe = Primary then
371 (CTL => Registers.CURACNTR,
372 BASE => Registers.CURABASE,
373 POS => Registers.CURAPOS,
374 FBC_CTL => Registers.Invalid_Register)
375 else
376 (CTL => Registers.CURBCNTR,
377 BASE => Registers.CURBBASE,
378 POS => Registers.CURBPOS,
379 FBC_CTL => Registers.Invalid_Register))
380 else
381 (if Pipe = Primary then
382 (CTL => Registers.CUR_CTL_A,
383 BASE => Registers.CUR_BASE_A,
384 POS => Registers.CUR_POS_A,
385 FBC_CTL => Registers.CUR_FBC_CTL_A)
386 elsif Pipe = Secondary then
387 (CTL => Registers.CUR_CTL_B,
388 BASE => Registers.CUR_BASE_B,
389 POS => Registers.CUR_POS_B,
390 FBC_CTL => Registers.CUR_FBC_CTL_B)
391 else
392 (CTL => Registers.CUR_CTL_C,
393 BASE => Registers.CUR_BASE_C,
394 POS => Registers.CUR_POS_C,
395 FBC_CTL => Registers.CUR_FBC_CTL_C)));
396
Nico Huber83693c82016-10-08 22:17:55 +0200397end HW.GFX.GMA.Pipe_Setup;