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Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000016 */
17
18/*
19 * Contains the ITE IT87* SPI specific routines
20 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000024#include <string.h>
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +000025#include <stdlib.h>
Vadim Girlin4dd0f902013-08-24 12:18:17 +000026#include <errno.h>
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000027#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000028#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000030#include "hwaccess.h"
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000031#include "spi.h"
32
33#define ITE_SUPERIO_PORT1 0x2e
34#define ITE_SUPERIO_PORT2 0x4e
35
Vadim Girlin4dd0f902013-08-24 12:18:17 +000036static uint16_t it8716f_flashport = 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000037/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000038static int fast_spi = 1;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000039
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000040/* Helper functions for most recent ITE IT87xx Super I/O chips */
41#define CHIP_ID_BYTE1_REG 0x20
42#define CHIP_ID_BYTE2_REG 0x21
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000043#define CHIP_VER_REG 0x22
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000044void enter_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000045{
Andriy Gapon65c1b862008-05-22 13:22:45 +000046 OUTB(0x87, port);
47 OUTB(0x01, port);
48 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000049 if (port == ITE_SUPERIO_PORT1)
Andriy Gapon65c1b862008-05-22 13:22:45 +000050 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000051 else
Andriy Gapon65c1b862008-05-22 13:22:45 +000052 OUTB(0xaa, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000053}
54
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055void exit_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000056{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057 sio_write(port, 0x02, 0x02);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000058}
59
Jacob Garberbeeb8bc2019-06-21 15:24:17 -060060static uint16_t probe_id_ite(uint16_t port)
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000061{
62 uint16_t id;
63
64 enter_conf_mode_ite(port);
65 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
66 id |= sio_read(port, CHIP_ID_BYTE2_REG);
67 exit_conf_mode_ite(port);
68
69 return id;
70}
71
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000072void probe_superio_ite(void)
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000073{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000074 struct superio s = {0};
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000075 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
76 uint16_t *i = ite_ports;
77
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000078 s.vendor = SUPERIO_VENDOR_ITE;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000079 for (; *i; i++) {
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000080 s.port = *i;
81 s.model = probe_id_ite(s.port);
82 switch (s.model >> 8) {
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083 case 0x82:
84 case 0x86:
85 case 0x87:
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000086 /* FIXME: Print revision for all models? */
Stefan Tauner352e50b2013-02-22 15:58:45 +000087 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port 0x%x\n", s.model, s.port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000088 register_superio(s);
89 break;
90 case 0x85:
Stefan Tauner352e50b2013-02-22 15:58:45 +000091 msg_pdbg("Found ITE EC, ID 0x%04hx, Rev 0x%02x on port 0x%x.\n",
92 s.model, sio_read(s.port, CHIP_VER_REG), s.port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000093 register_superio(s);
94 break;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000095 }
96 }
97
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000098 return;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000099}
100
Edward O'Callaghan5eca4272020-04-12 17:27:53 +1000101static int it8716f_spi_send_command(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000102 unsigned int writecnt, unsigned int readcnt,
103 const unsigned char *writearr,
104 unsigned char *readarr);
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000105static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000106 unsigned int start, unsigned int len);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000107static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000108 unsigned int start, unsigned int len);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000109
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000110static const struct spi_master spi_master_it87xx = {
Edward O'Callaghan52916f62020-10-09 13:00:17 +1100111 .max_data_read = 3,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000112 .max_data_write = MAX_DATA_UNSPECIFIED,
113 .command = it8716f_spi_send_command,
114 .multicommand = default_spi_send_multicommand,
115 .read = it8716f_spi_chip_read,
116 .write_256 = it8716f_spi_chip_write_256,
Nico Huber504215b2017-04-22 00:13:15 +0200117 .write_aai = spi_chip_write_1,
Michael Karcherb9dbe482011-05-11 17:07:07 +0000118};
119
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000120static uint16_t it87spi_probe(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000121{
122 uint8_t tmp = 0;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000123 uint16_t flashport = 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000124
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000125 enter_conf_mode_ite(port);
Elyes HAOUAS0cacb112019-02-04 12:16:38 +0100126
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000127 char *param = extract_programmer_param("dualbiosindex");
128 if (param != NULL) {
129 sio_write(port, 0x07, 0x07); /* Select GPIO LDN */
130 tmp = sio_read(port, 0xEF);
131 if (*param == '\0') { /* Print current setting only. */
132 free(param);
133 } else {
134 char *dualbiosindex_suffix;
135 errno = 0;
136 long chip_index = strtol(param, &dualbiosindex_suffix, 0);
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000137 if (errno != 0 || *dualbiosindex_suffix != '\0' || chip_index < 0 || chip_index > 1) {
138 msg_perr("DualBIOS: Invalid chip index requested - choose 0 or 1.\n");
Angel Ponsd92dd502020-10-19 14:20:36 +0200139 free(param);
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000140 exit_conf_mode_ite(port);
141 return 1;
142 }
Angel Ponsd92dd502020-10-19 14:20:36 +0200143 free(param);
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000144 if (chip_index != (tmp & 1)) {
145 msg_pdbg("DualBIOS: Previous chip index: %d\n", tmp & 1);
146 sio_write(port, 0xEF, (tmp & 0xFE) | chip_index);
147 tmp = sio_read(port, 0xEF);
148 if ((tmp & 1) != chip_index) {
149 msg_perr("DualBIOS: Chip selection failed.\n");
150 exit_conf_mode_ite(port);
151 return 1;
152 }
153 }
154 }
155 msg_pinfo("DualBIOS: Selected chip: %d\n", tmp & 1);
156 }
157
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000158 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
159 tmp = sio_read(port, 0x24) & 0xFE;
Carl-Daniel Hailfinger2e681602011-09-08 00:00:29 +0000160 /* Check if LPC->SPI translation is active. */
161 if (!(tmp & 0x0e)) {
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000162 msg_pdbg("No IT87* serial flash segment enabled.\n");
163 exit_conf_mode_ite(port);
164 /* Nothing to do. */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000165 return 0;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000166 }
167 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
168 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
169 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
170 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
171 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
172 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
173 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
174 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
175 msg_pdbg("LPC write to serial flash %sabled\n",
176 (tmp & 1 << 4) ? "en" : "dis");
177 /* The LPC->SPI force write enable below only makes sense for
178 * non-programmer mode.
179 */
180 /* If any serial flash segment is enabled, enable writing. */
181 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
182 msg_pdbg("Enabling LPC write to serial flash\n");
183 tmp |= 1 << 4;
184 sio_write(port, 0x24, tmp);
185 }
186 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
187 /* LDN 0x7, reg 0x64/0x65 */
188 sio_write(port, 0x07, 0x7);
189 flashport = sio_read(port, 0x64) << 8;
190 flashport |= sio_read(port, 0x65);
191 msg_pdbg("Serial flash port 0x%04x\n", flashport);
192 /* Non-default port requested? */
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000193 param = extract_programmer_param("it87spiport");
194 if (param) {
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000195 char *endptr = NULL;
196 unsigned long forced_flashport;
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000197 forced_flashport = strtoul(param, &endptr, 0);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000198 /* Port 0, port >0x1000, unaligned ports and garbage strings
199 * are rejected.
Carl-Daniel Hailfinger01f3ef42010-03-25 02:50:40 +0000200 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000201 if (!forced_flashport || (forced_flashport >= 0x1000) ||
202 (forced_flashport & 0x7) || (*endptr != '\0')) {
203 /* Using ports below 0x100 is a really bad idea, and
204 * should only be done if no port between 0x100 and
205 * 0xff8 works due to routing issues.
206 */
207 msg_perr("Error: it87spiport specified, but no valid "
208 "port specified.\nPort must be a multiple of "
209 "0x8 and lie between 0x100 and 0xff8.\n");
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000210 exit_conf_mode_ite(port);
211 free(param);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000212 return 1;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000213 } else {
214 flashport = (uint16_t)forced_flashport;
215 msg_pinfo("Forcing serial flash port 0x%04x\n",
216 flashport);
217 sio_write(port, 0x64, (flashport >> 8));
218 sio_write(port, 0x65, (flashport & 0xff));
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000219 }
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000220 }
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000221 free(param);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000222 exit_conf_mode_ite(port);
223 it8716f_flashport = flashport;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000224 if (internal_buses_supported & BUS_SPI)
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000225 msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000226 /* FIXME: Add the SPI bus or replace the other buses with it? */
Nico Huber5e08e3e2021-05-11 17:38:14 +0200227 register_spi_master(&spi_master_it87xx, NULL);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000228 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000229}
230
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000231int init_superio_ite(void)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000232{
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +0000233 int i;
234 int ret = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000235
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000236 for (i = 0; i < superio_count; i++) {
237 if (superios[i].vendor != SUPERIO_VENDOR_ITE)
238 continue;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000239
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000240 switch (superios[i].model) {
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000241 case 0x8705:
242 ret |= it8705f_write_enable(superios[i].port);
243 break;
Pete Smith5dc7d942022-05-11 10:01:25 +0000244 case 0x8686:
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000245 case 0x8716:
246 case 0x8718:
247 case 0x8720:
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000248 case 0x8728:
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000249 ret |= it87spi_probe(superios[i].port);
250 break;
251 default:
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000252 msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",
253 superios[i].model);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000254 }
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000255 }
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000256 return ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000257}
258
Uwe Hermann394131e2008-10-18 21:14:13 +0000259/*
260 * The IT8716F only supports commands with length 1,2,4,5 bytes including
261 * command byte and can not read more than 3 bytes from the device.
262 *
263 * This function expects writearr[0] to be the first byte sent to the device,
264 * whereas the IT8716F splits commands internally into address and non-address
265 * commands with the address in inverse wire order. That's why the register
266 * ordering in case 4 and 5 may seem strange.
267 */
Edward O'Callaghan5eca4272020-04-12 17:27:53 +1000268static int it8716f_spi_send_command(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000269 unsigned int writecnt, unsigned int readcnt,
270 const unsigned char *writearr,
271 unsigned char *readarr)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000272{
273 uint8_t busy, writeenc;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000274
275 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000276 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000277 } while (busy);
278 if (readcnt > 3) {
Sean Nelson01e532d2010-01-10 01:09:58 +0000279 msg_pinfo("%s called with unsupported readcnt %i.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000280 __func__, readcnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000281 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000282 }
283 switch (writecnt) {
284 case 1:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000285 OUTB(writearr[0], it8716f_flashport + 1);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000286 writeenc = 0x0;
287 break;
288 case 2:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000289 OUTB(writearr[0], it8716f_flashport + 1);
290 OUTB(writearr[1], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000291 writeenc = 0x1;
292 break;
293 case 4:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000294 OUTB(writearr[0], it8716f_flashport + 1);
295 OUTB(writearr[1], it8716f_flashport + 4);
296 OUTB(writearr[2], it8716f_flashport + 3);
297 OUTB(writearr[3], it8716f_flashport + 2);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000298 writeenc = 0x2;
299 break;
300 case 5:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000301 OUTB(writearr[0], it8716f_flashport + 1);
302 OUTB(writearr[1], it8716f_flashport + 4);
303 OUTB(writearr[2], it8716f_flashport + 3);
304 OUTB(writearr[3], it8716f_flashport + 2);
305 OUTB(writearr[4], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000306 writeenc = 0x3;
307 break;
308 default:
Sean Nelson01e532d2010-01-10 01:09:58 +0000309 msg_pinfo("%s called with unsupported writecnt %i.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000310 __func__, writecnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000311 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000312 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000313 /*
314 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000315 * Note:
316 * We can't use writecnt directly, but have to use a strange encoding.
Uwe Hermann394131e2008-10-18 21:14:13 +0000317 */
318 OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
319 | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000320
321 if (readcnt > 0) {
Nico Huber519be662018-12-23 20:03:35 +0100322 unsigned int i;
323
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000324 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000325 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000326 } while (busy);
327
Uwe Hermann394131e2008-10-18 21:14:13 +0000328 for (i = 0; i < readcnt; i++)
Andriy Gapon65c1b862008-05-22 13:22:45 +0000329 readarr[i] = INB(it8716f_flashport + 5 + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000330 }
331
332 return 0;
333}
334
335/* Page size is usually 256 bytes */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000336static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf, unsigned int start)
Uwe Hermann394131e2008-10-18 21:14:13 +0000337{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000338 unsigned int i;
339 int result;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000340 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000341
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000342 result = spi_write_enable(flash);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000343 if (result)
344 return result;
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000345 /* FIXME: The command below seems to be redundant or wrong. */
Uwe Hermann394131e2008-10-18 21:14:13 +0000346 OUTB(0x06, it8716f_flashport + 1);
Andriy Gapon65c1b862008-05-22 13:22:45 +0000347 OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000348 for (i = 0; i < flash->chip->page_size; i++)
Carl-Daniel Hailfingerccd71c22012-03-01 22:38:27 +0000349 mmio_writeb(buf[i], (void *)(bios + start + i));
Andriy Gapon65c1b862008-05-22 13:22:45 +0000350 OUTB(0, it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000351 /* Wait until the Write-In-Progress bit is cleared.
352 * This usually takes 1-10 ms, so wait in 1 ms steps.
Nikolai Artemievb8a90d02021-10-28 16:18:28 +1100353 *
354 * FIXME: This should timeout after some number of retries.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000355 */
Nikolai Artemievb8a90d02021-10-28 16:18:28 +1100356 while (true) {
357 uint8_t status;
358 int ret = spi_read_register(flash, STATUS1, &status);
359 if (ret)
360 return ret;
361
362 if((status & SPI_SR_WIP) == 0)
363 return 0;
364
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000365 programmer_delay(1000);
Nikolai Artemievb8a90d02021-10-28 16:18:28 +1100366 }
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000367 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000368}
369
370/*
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000371 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
372 * Need to read this big flash using firmware cycles 3 byte at a time.
373 */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000374static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000375 unsigned int start, unsigned int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000376{
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000377 fast_spi = 0;
378
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000379 /* FIXME: Check if someone explicitly requested to use IT87 SPI although
380 * the mainboard does not use IT87 SPI translation. This should be done
381 * via a programmer parameter for the internal programmer.
382 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000383 if ((flash->chip->total_size * 1024 > 512 * 1024)) {
Edward O'Callaghan52916f62020-10-09 13:00:17 +1100384 default_spi_read(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000385 } else {
Carl-Daniel Hailfingerccd71c22012-03-01 22:38:27 +0000386 mmio_readn((void *)(flash->virtual_memory + start), buf, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000387 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000388
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000389 return 0;
390}
391
Mark Marshallf20b7be2014-05-09 21:16:21 +0000392static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000393 unsigned int start, unsigned int len)
Uwe Hermann394131e2008-10-18 21:14:13 +0000394{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000395 const struct flashchip *chip = flash->chip;
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000396 /*
397 * IT8716F only allows maximum of 512 kb SPI chip size for memory
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000398 * mapped access. It also can't write more than 1+3+256 bytes at once,
399 * so page_size > 256 bytes needs a fallback.
400 * FIXME: Split too big page writes into chunks IT87* can handle instead
401 * of degrading to single-byte program.
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000402 * FIXME: Check if someone explicitly requested to use IT87 SPI although
403 * the mainboard does not use IT87 SPI translation. This should be done
404 * via a programmer parameter for the internal programmer.
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000405 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000406 if ((chip->total_size * 1024 > 512 * 1024) || (chip->page_size > 256)) {
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000407 spi_chip_write_1(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000408 } else {
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000409 unsigned int lenhere;
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000410
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000411 if (start % chip->page_size) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000412 /* start to the end of the page or to start + len,
413 * whichever is smaller.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000414 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000415 lenhere = min(len, chip->page_size - start % chip->page_size);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000416 spi_chip_write_1(flash, buf, start, lenhere);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000417 start += lenhere;
418 len -= lenhere;
419 buf += lenhere;
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000420 }
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000421
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000422 while (len >= chip->page_size) {
Nikolai Artemievb8a90d02021-10-28 16:18:28 +1100423 int ret = it8716f_spi_page_program(flash, buf, start);
424 if (ret)
425 return ret;
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000426 start += chip->page_size;
427 len -= chip->page_size;
428 buf += chip->page_size;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000429 }
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000430 if (len)
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000431 spi_chip_write_1(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000432 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000433
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000434 return 0;
435}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000436
437#endif