blob: 2b09d64243afa653db517ca3ac81b165e90e05e3 [file] [log] [blame]
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the ITE IT87* SPI specific routines
24 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000028#include <string.h>
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +000029#include <stdlib.h>
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000030#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000031#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000032#include "programmer.h"
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000033#include "spi.h"
34
35#define ITE_SUPERIO_PORT1 0x2e
36#define ITE_SUPERIO_PORT2 0x4e
37
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000038uint16_t it8716f_flashport = 0;
39/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000040static int fast_spi = 1;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000041
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000042/* Helper functions for most recent ITE IT87xx Super I/O chips */
43#define CHIP_ID_BYTE1_REG 0x20
44#define CHIP_ID_BYTE2_REG 0x21
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000045#define CHIP_VER_REG 0x22
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000046void enter_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000047{
Andriy Gapon65c1b862008-05-22 13:22:45 +000048 OUTB(0x87, port);
49 OUTB(0x01, port);
50 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000051 if (port == ITE_SUPERIO_PORT1)
Andriy Gapon65c1b862008-05-22 13:22:45 +000052 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000053 else
Andriy Gapon65c1b862008-05-22 13:22:45 +000054 OUTB(0xaa, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000055}
56
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057void exit_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000058{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000059 sio_write(port, 0x02, 0x02);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000060}
61
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000062uint16_t probe_id_ite(uint16_t port)
63{
64 uint16_t id;
65
66 enter_conf_mode_ite(port);
67 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
68 id |= sio_read(port, CHIP_ID_BYTE2_REG);
69 exit_conf_mode_ite(port);
70
71 return id;
72}
73
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000074void probe_superio_ite(void)
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000075{
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000076 struct superio s = {};
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000077 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
78 uint16_t *i = ite_ports;
79
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000080 s.vendor = SUPERIO_VENDOR_ITE;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000081 for (; *i; i++) {
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000082 s.port = *i;
83 s.model = probe_id_ite(s.port);
84 switch (s.model >> 8) {
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000085 case 0x82:
86 case 0x86:
87 case 0x87:
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000088 /* FIXME: Print revision for all models? */
89 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
90 "0x%x\n", s.model, s.port);
91 register_superio(s);
92 break;
93 case 0x85:
94 msg_pdbg("Found ITE EC, ID 0x%04hx,"
95 "Rev 0x%02x on port 0x%x.\n",
96 s.model,
97 sio_read(s.port, CHIP_VER_REG),
98 s.port);
99 register_superio(s);
100 break;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000101 }
102 }
103
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000104 return;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000105}
106
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000107static uint16_t it87spi_probe(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000108{
109 uint8_t tmp = 0;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000110 char *portpos = NULL;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000111 uint16_t flashport = 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000112
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000113 enter_conf_mode_ite(port);
114 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
115 tmp = sio_read(port, 0x24) & 0xFE;
116 /* If IT87SPI was not explicitly selected, we want to check
117 * quickly if LPC->SPI translation is active.
118 */
119 if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) {
120 msg_pdbg("No IT87* serial flash segment enabled.\n");
121 exit_conf_mode_ite(port);
122 /* Nothing to do. */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000123 return 0;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000124 }
125 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
126 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
127 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
128 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
129 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
130 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
131 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
132 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
133 msg_pdbg("LPC write to serial flash %sabled\n",
134 (tmp & 1 << 4) ? "en" : "dis");
135 /* The LPC->SPI force write enable below only makes sense for
136 * non-programmer mode.
137 */
138 /* If any serial flash segment is enabled, enable writing. */
139 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
140 msg_pdbg("Enabling LPC write to serial flash\n");
141 tmp |= 1 << 4;
142 sio_write(port, 0x24, tmp);
143 }
144 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
145 /* LDN 0x7, reg 0x64/0x65 */
146 sio_write(port, 0x07, 0x7);
147 flashport = sio_read(port, 0x64) << 8;
148 flashport |= sio_read(port, 0x65);
149 msg_pdbg("Serial flash port 0x%04x\n", flashport);
150 /* Non-default port requested? */
151 portpos = extract_programmer_param("it87spiport");
152 if (portpos) {
153 char *endptr = NULL;
154 unsigned long forced_flashport;
155 forced_flashport = strtoul(portpos, &endptr, 0);
156 /* Port 0, port >0x1000, unaligned ports and garbage strings
157 * are rejected.
Carl-Daniel Hailfinger01f3ef42010-03-25 02:50:40 +0000158 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000159 if (!forced_flashport || (forced_flashport >= 0x1000) ||
160 (forced_flashport & 0x7) || (*endptr != '\0')) {
161 /* Using ports below 0x100 is a really bad idea, and
162 * should only be done if no port between 0x100 and
163 * 0xff8 works due to routing issues.
164 */
165 msg_perr("Error: it87spiport specified, but no valid "
166 "port specified.\nPort must be a multiple of "
167 "0x8 and lie between 0x100 and 0xff8.\n");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000168 free(portpos);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000169 return 1;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000170 } else {
171 flashport = (uint16_t)forced_flashport;
172 msg_pinfo("Forcing serial flash port 0x%04x\n",
173 flashport);
174 sio_write(port, 0x64, (flashport >> 8));
175 sio_write(port, 0x65, (flashport & 0xff));
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000176 }
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000177 }
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000178 free(portpos);
179 exit_conf_mode_ite(port);
180 it8716f_flashport = flashport;
181 if (buses_supported & CHIP_BUSTYPE_SPI)
182 msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
183 spi_controller = SPI_CONTROLLER_IT87XX;
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000184 /* FIXME: Add the SPI bus or replace the other buses with it? */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000185 buses_supported |= CHIP_BUSTYPE_SPI;
186 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000187}
188
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000189int init_superio_ite(void)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000190{
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000191 int i;
192 int ret = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000193
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000194 for (i = 0; i < superio_count; i++) {
195 if (superios[i].vendor != SUPERIO_VENDOR_ITE)
196 continue;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000197
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000198 switch (superios[i].model) {
199 case 0x8500:
200 case 0x8502:
201 case 0x8510:
202 case 0x8511:
203 case 0x8512:
204 /* FIXME: This should be enabled, but we need a check
205 * for laptop whitelisting due to the amount of things
206 * which can go wrong if the EC firmware does not
207 * implement the interface we want.
208 */
209 //it85xx_spi_init(superios[i]);
210 break;
211 case 0x8705:
212 ret |= it8705f_write_enable(superios[i].port);
213 break;
214 case 0x8716:
215 case 0x8718:
216 case 0x8720:
217 ret |= it87spi_probe(superios[i].port);
218 break;
219 default:
220 msg_pdbg("Super I/O ID 0x%04hx is not on the list of "
221 "flash capable controllers.\n",
222 superios[i].model);
223 }
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000224 }
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000225 return ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000226}
227
Uwe Hermann394131e2008-10-18 21:14:13 +0000228/*
229 * The IT8716F only supports commands with length 1,2,4,5 bytes including
230 * command byte and can not read more than 3 bytes from the device.
231 *
232 * This function expects writearr[0] to be the first byte sent to the device,
233 * whereas the IT8716F splits commands internally into address and non-address
234 * commands with the address in inverse wire order. That's why the register
235 * ordering in case 4 and 5 may seem strange.
236 */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000237int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000238 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000239{
240 uint8_t busy, writeenc;
241 int i;
242
243 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000244 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000245 } while (busy);
246 if (readcnt > 3) {
Sean Nelson01e532d2010-01-10 01:09:58 +0000247 msg_pinfo("%s called with unsupported readcnt %i.\n",
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000248 __func__, readcnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000249 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000250 }
251 switch (writecnt) {
252 case 1:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000253 OUTB(writearr[0], it8716f_flashport + 1);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000254 writeenc = 0x0;
255 break;
256 case 2:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000257 OUTB(writearr[0], it8716f_flashport + 1);
258 OUTB(writearr[1], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000259 writeenc = 0x1;
260 break;
261 case 4:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000262 OUTB(writearr[0], it8716f_flashport + 1);
263 OUTB(writearr[1], it8716f_flashport + 4);
264 OUTB(writearr[2], it8716f_flashport + 3);
265 OUTB(writearr[3], it8716f_flashport + 2);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000266 writeenc = 0x2;
267 break;
268 case 5:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000269 OUTB(writearr[0], it8716f_flashport + 1);
270 OUTB(writearr[1], it8716f_flashport + 4);
271 OUTB(writearr[2], it8716f_flashport + 3);
272 OUTB(writearr[3], it8716f_flashport + 2);
273 OUTB(writearr[4], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000274 writeenc = 0x3;
275 break;
276 default:
Sean Nelson01e532d2010-01-10 01:09:58 +0000277 msg_pinfo("%s called with unsupported writecnt %i.\n",
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000278 __func__, writecnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000279 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000280 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000281 /*
282 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000283 * Note:
284 * We can't use writecnt directly, but have to use a strange encoding.
Uwe Hermann394131e2008-10-18 21:14:13 +0000285 */
286 OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
287 | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000288
289 if (readcnt > 0) {
290 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000291 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000292 } while (busy);
293
Uwe Hermann394131e2008-10-18 21:14:13 +0000294 for (i = 0; i < readcnt; i++)
Andriy Gapon65c1b862008-05-22 13:22:45 +0000295 readarr[i] = INB(it8716f_flashport + 5 + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000296 }
297
298 return 0;
299}
300
301/* Page size is usually 256 bytes */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000302static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int start)
Uwe Hermann394131e2008-10-18 21:14:13 +0000303{
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000304 int i;
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000305 int result;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000306 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000307
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000308 result = spi_write_enable();
309 if (result)
310 return result;
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000311 /* FIXME: The command below seems to be redundant or wrong. */
Uwe Hermann394131e2008-10-18 21:14:13 +0000312 OUTB(0x06, it8716f_flashport + 1);
Andriy Gapon65c1b862008-05-22 13:22:45 +0000313 OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000314 for (i = 0; i < flash->page_size; i++) {
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000315 chip_writeb(buf[i], bios + start + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000316 }
Andriy Gapon65c1b862008-05-22 13:22:45 +0000317 OUTB(0, it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000318 /* Wait until the Write-In-Progress bit is cleared.
319 * This usually takes 1-10 ms, so wait in 1 ms steps.
320 */
321 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000322 programmer_delay(1000);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000323 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000324}
325
326/*
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000327 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
328 * Need to read this big flash using firmware cycles 3 byte at a time.
329 */
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000330int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000331{
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000332 fast_spi = 0;
333
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000334 /* FIXME: Check if someone explicitly requested to use IT87 SPI although
335 * the mainboard does not use IT87 SPI translation. This should be done
336 * via a programmer parameter for the internal programmer.
337 */
338 if ((flash->total_size * 1024 > 512 * 1024)) {
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000339 spi_read_chunked(flash, buf, start, len, 3);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000340 } else {
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000341 read_memmapped(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000342 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000343
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000344 return 0;
345}
346
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000347int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
Uwe Hermann394131e2008-10-18 21:14:13 +0000348{
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000349 /*
350 * IT8716F only allows maximum of 512 kb SPI chip size for memory
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000351 * mapped access. It also can't write more than 1+3+256 bytes at once,
352 * so page_size > 256 bytes needs a fallback.
353 * FIXME: Split too big page writes into chunks IT87* can handle instead
354 * of degrading to single-byte program.
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000355 * FIXME: Check if someone explicitly requested to use IT87 SPI although
356 * the mainboard does not use IT87 SPI translation. This should be done
357 * via a programmer parameter for the internal programmer.
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000358 */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000359 if ((flash->total_size * 1024 > 512 * 1024) ||
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000360 (flash->page_size > 256)) {
361 spi_chip_write_1(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000362 } else {
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000363 int lenhere;
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000364
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000365 if (start % flash->page_size) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000366 /* start to the end of the page or to start + len,
367 * whichever is smaller.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000368 */
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000369 lenhere = min(len, flash->page_size - start % flash->page_size);
370 spi_chip_write_1(flash, buf, start, lenhere);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000371 start += lenhere;
372 len -= lenhere;
373 buf += lenhere;
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000374 }
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000375
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000376 while (len >= flash->page_size) {
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000377 it8716f_spi_page_program(flash, buf, start);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000378 start += flash->page_size;
379 len -= flash->page_size;
380 buf += flash->page_size;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000381 }
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000382 if (len)
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000383 spi_chip_write_1(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000384 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000385
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000386 return 0;
387}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000388
389#endif