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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000069/* Not used yet. */
70#if 0
71static int enable_flash_decode_superio(void)
72{
73 int ret;
74 uint8_t tmp;
75
76 switch (superio.vendor) {
77 case SUPERIO_VENDOR_NONE:
78 ret = -1;
79 break;
80 case SUPERIO_VENDOR_ITE:
81 enter_conf_mode_ite(superio.port);
82 /* Enable flash mapping. Works for most old ITE style SuperI/O. */
83 tmp = sio_read(superio.port, 0x24);
84 tmp |= 0xfc;
85 sio_write(superio.port, 0x24, tmp);
86 exit_conf_mode_ite(superio.port);
87 ret = 0;
88 break;
89 default:
90 printf_debug("Unhandled SuperI/O type!\n");
91 ret = -1;
92 break;
93 }
94 return ret;
95}
96#endif
97
Uwe Hermannffec5f32007-08-23 16:08:21 +000098/**
99 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000100 *
101 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000102 * - Agami Aruma
103 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000104 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000105static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000106{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000107 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000108
Uwe Hermann372eeb52007-12-04 21:49:06 +0000109 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000110 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000111 fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000112 name, sio_read(port, 0x20));
113 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000114 return -1;
115 }
116
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000117 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000119
Uwe Hermann372eeb52007-12-04 21:49:06 +0000120 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000122
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
124 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
125 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
126 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000127
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000128 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000129
130 return 0;
131}
132
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000133static int w83627hf_gpio24_raise_2e(const char *name)
134{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000135 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000136}
137
138/**
139 * Winbond W83627THF: GPIO 4, bit 4
140 *
141 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000142 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000143 * - MSI K8N-NEO3
144 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000145static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000147 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148
149 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000150 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000151 fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000152 name, sio_read(port, 0x20));
153 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000154 return -1;
155 }
156
157 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
158
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
160 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
161 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
162 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
163 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000164
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000165 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000166
167 return 0;
168}
169
Peter Stugecce26822008-07-21 17:48:40 +0000170static int w83627thf_gpio4_4_raise_2e(const char *name)
171{
172 return w83627thf_gpio4_4_raise(0x2e, name);
173}
174
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000175static int w83627thf_gpio4_4_raise_4e(const char *name)
176{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000177 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000178}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000179
Uwe Hermannffec5f32007-08-23 16:08:21 +0000180/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000181 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000182 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000183static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000184{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000185 w836xx_ext_enter(port);
186 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000187 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000188 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000189 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000190 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000191}
192
193/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000194 * Suited for:
195 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
196 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
197 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
198 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
199 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000200 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000201static int w836xx_memw_enable_2e(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000202{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000203 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000204
Luc Verhaegen73d21192009-12-23 00:54:26 +0000205 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000206}
207
Luc Verhaegen73d21192009-12-23 00:54:26 +0000208
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000209/**
210 * VT823x: Set one of the GPIO pins.
211 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000212static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000213{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000214 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000215 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000216 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000217
Luc Verhaegen73d21192009-12-23 00:54:26 +0000218 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
219 switch (dev->device_id) {
220 case 0x3177: /* VT8235 */
221 case 0x3227: /* VT8237R */
222 case 0x3337: /* VT8237A */
223 break;
224 default:
225 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
226 return -1;
227 }
228
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000229 if ((gpio >= 12) && (gpio <= 15)) {
230 /* GPIO12-15 -> output */
231 val = pci_read_byte(dev, 0xE4);
232 val |= 0x10;
233 pci_write_byte(dev, 0xE4, val);
234 } else if (gpio == 9) {
235 /* GPIO9 -> Output */
236 val = pci_read_byte(dev, 0xE4);
237 val |= 0x20;
238 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000239 } else if (gpio == 5) {
240 val = pci_read_byte(dev, 0xE4);
241 val |= 0x01;
242 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000243 } else {
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000244 fprintf(stderr, "\nERROR: "
245 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000246 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000247 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000248
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000249 /* We need the I/O Base Address for this board's flash enable. */
250 base = pci_read_word(dev, 0x88) & 0xff80;
251
David Bartleyf58d3642009-12-09 07:53:01 +0000252 offset = 0x4C + gpio / 8;
253 bit = 0x01 << (gpio % 8);
254
255 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000256 if (raise)
257 val |= bit;
258 else
259 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000260 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000261
Uwe Hermanna7e05482007-05-09 10:17:44 +0000262 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000263}
264
Uwe Hermannffec5f32007-08-23 16:08:21 +0000265/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000266 * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000267 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000268static int via_vt823x_gpio5_raise(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000269{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000270 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
271 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000272}
273
274/**
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000275 * Suited for VIAs EPIA N & NL.
276 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000277static int via_vt823x_gpio9_raise(const char *name)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000278{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000279 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000280}
281
282/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000283 * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
284 *
285 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
286 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000287 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000288static int via_vt823x_gpio15_raise(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000289{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000290 return via_vt823x_gpio_set(15, 1);
291}
292
293/**
294 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
295 *
296 * Suited for:
297 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
298 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
299 */
300static int board_msi_kt4v(const char *name)
301{
302 int ret;
303
304 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000305 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000306
Luc Verhaegen73d21192009-12-23 00:54:26 +0000307 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000308}
309
310/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000311 * Suited for ASUS P5A.
312 *
313 * This is rather nasty code, but there's no way to do this cleanly.
314 * We're basically talking to some unknown device on SMBus, my guess
315 * is that it is the Winbond W83781D that lives near the DIP BIOS.
316 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000317static int board_asus_p5a(const char *name)
318{
319 uint8_t tmp;
320 int i;
321
322#define ASUSP5A_LOOP 5000
323
Andriy Gapon65c1b862008-05-22 13:22:45 +0000324 OUTB(0x00, 0xE807);
325 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000326
Andriy Gapon65c1b862008-05-22 13:22:45 +0000327 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000328
329 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000330 OUTB(0xE1, 0xFF);
331 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000332 break;
333 }
334
335 if (i == ASUSP5A_LOOP) {
336 printf("%s: Unable to contact device.\n", name);
337 return -1;
338 }
339
Andriy Gapon65c1b862008-05-22 13:22:45 +0000340 OUTB(0x20, 0xE801);
341 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000342
Andriy Gapon65c1b862008-05-22 13:22:45 +0000343 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000344
345 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000346 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000347 if (tmp & 0x70)
348 break;
349 }
350
351 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
352 printf("%s: failed to read device.\n", name);
353 return -1;
354 }
355
Andriy Gapon65c1b862008-05-22 13:22:45 +0000356 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000357 tmp &= ~0x02;
358
Andriy Gapon65c1b862008-05-22 13:22:45 +0000359 OUTB(0x00, 0xE807);
360 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000361
Andriy Gapon65c1b862008-05-22 13:22:45 +0000362 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000363
Andriy Gapon65c1b862008-05-22 13:22:45 +0000364 OUTB(0xFF, 0xE800);
365 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000366
Andriy Gapon65c1b862008-05-22 13:22:45 +0000367 OUTB(0x20, 0xE801);
368 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000369
Andriy Gapon65c1b862008-05-22 13:22:45 +0000370 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000371
372 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000373 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000374 if (tmp & 0x70)
375 break;
376 }
377
378 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
379 printf("%s: failed to write to device.\n", name);
380 return -1;
381 }
382
383 return 0;
384}
385
Luc Verhaegena7e30502009-12-09 11:39:02 +0000386/*
387 * Set GPIO lines in the Broadcom HT-1000 southbridge.
388 *
389 * It's not a Super I/O but it uses the same index/data port method.
390 */
391static int board_hp_dl145_g3_enable(const char *name)
392{
393 /* GPIO 0 reg from PM regs */
394 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
395 sio_mask(0xcd6, 0x44, 0x24, 0x24);
396
397 return 0;
398}
399
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000400static int board_ibm_x3455(const char *name)
401{
Luc Verhaegena7e30502009-12-09 11:39:02 +0000402 /* raise gpio13 */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000403 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000404
405 return 0;
406}
407
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000408/**
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000409 * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4).
410 */
411static int board_shuttle_fn25(const char *name)
412{
413 struct pci_dev *dev;
414
415 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
416 if (!dev) {
417 fprintf(stderr,
418 "\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
419 return -1;
420 }
421
422 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
423 pci_write_byte(dev, 0x92, 0);
424
425 return 0;
426}
427
428/**
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000429 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000430 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000431static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000432{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000433 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000434 uint16_t base;
435 uint8_t tmp;
436
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000437 if ((gpio < 0) || (gpio >= 0x40)) {
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000438 fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000439 return -1;
440 }
441
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000442 /* First, check the ISA Bridge */
443 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000444 switch (dev->device_id) {
445 case 0x0030: /* CK804 */
446 case 0x0050: /* MCP04 */
447 case 0x0060: /* MCP2 */
448 break;
449 default:
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000450 /* Newer MCPs use the SMBus Controller */
451 dev = pci_dev_find_vendorclass(0x10DE, 0x0C05);
452 switch (dev->device_id) {
453 case 0x0264: /* MCP51 */
454 break;
455 default:
456 fprintf(stderr,
457 "\nERROR: no nVidia LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000458 return -1;
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000459 }
460 break;
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000461 }
462
463 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
464 base += 0xC0;
465
466 tmp = INB(base + gpio);
467 tmp &= ~0x0F; /* null lower nibble */
468 tmp |= 0x04; /* gpio -> output. */
469 if (raise)
470 tmp |= 0x01;
471 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000472
473 return 0;
474}
475
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000476/**
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000477 * Suited for MSI K8N Neo4: nVidia CK804.
478 */
479static int nvidia_mcp_gpio2_raise(const char *name)
480{
481 return nvidia_mcp_gpio_set(0x02, 1);
482}
483
484/**
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000485 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
486 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000487static int nvidia_mcp_gpio10_raise(const char *name)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000488{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000489 return nvidia_mcp_gpio_set(0x10, 1);
490}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000491
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000492/**
493 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
494 */
495static int nvidia_mcp_gpio21_raise(const char *name)
496{
497 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000498}
499
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000500/**
501 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
502 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000503static int nvidia_mcp_gpio31_raise(const char *name)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000504{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000505 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000506}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000507
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000508/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000509 * Suited for Artec Group DBE61 and DBE62.
510 */
511static int board_artecgroup_dbe6x(const char *name)
512{
513#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
514#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
515#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
516#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
517#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
518#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
519#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
520#define DBE6x_BOOT_LOC_FLASH (2)
521#define DBE6x_BOOT_LOC_FWHUB (3)
522
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000523 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000524 unsigned long boot_loc;
525
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000526 /* Geode only has a single core */
527 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000528 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000529
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000530 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000531
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000532 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000533 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
534 boot_loc = DBE6x_BOOT_LOC_FWHUB;
535 else
536 boot_loc = DBE6x_BOOT_LOC_FLASH;
537
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000538 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
539 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000540 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000541
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000542 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000543
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000544 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000545
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000546 return 0;
547}
548
Uwe Hermann93f66db2008-05-22 21:19:38 +0000549/**
Luc Verhaegenf5226912009-12-14 10:41:58 +0000550 * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M}
551 */
552static int intel_piix4_gpo_set(unsigned int gpo, int raise)
553{
554 struct pci_dev *dev;
555 uint32_t tmp, base;
556
557 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
558 if (!dev) {
559 fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n");
560 return -1;
561 }
562
563 /* sanity check */
564 if (gpo > 30) {
565 fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
566 return -1;
567 }
568
569 /* these are dual function pins which are most likely in use already */
570 if (((gpo >= 1) && (gpo <= 7)) ||
571 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
572 fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
573 return -1;
574 }
575
576 /* dual function that need special enable. */
577 if ((gpo >= 22) && (gpo <= 26)) {
578 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
579 switch (gpo) {
580 case 22: /* XBUS: XDIR#/GPO22 */
581 case 23: /* XBUS: XOE#/GPO23 */
582 tmp |= 1 << 28;
583 break;
584 case 24: /* RTCSS#/GPO24 */
585 tmp |= 1 << 29;
586 break;
587 case 25: /* RTCALE/GPO25 */
588 tmp |= 1 << 30;
589 break;
590 case 26: /* KBCSS#/GPO26 */
591 tmp |= 1 << 31;
592 break;
593 }
594 pci_write_long(dev, 0xB0, tmp);
595 }
596
597 /* GPO {0,8,27,28,30} are always available. */
598
599 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
600 if (!dev) {
601 fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n");
602 return -1;
603 }
604
605 /* PM IO base */
606 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
607
608 tmp = INL(base + 0x34); /* GPO register */
609 if (raise)
610 tmp |= 0x01 << gpo;
611 else
612 tmp |= ~(0x01 << gpo);
613 OUTL(tmp, base + 0x34);
614
615 return 0;
616}
617
618/**
619 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
620 */
621static int board_epox_ep_bx3(const char *name)
622{
623 return intel_piix4_gpo_set(22, 1);
624}
625
626/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000627 * Set a GPIO line on a given intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000628 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000629static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000630{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000631 /* table mapping the different intel ICH LPC chipsets. */
632 static struct {
633 uint16_t id;
634 uint8_t base_reg;
635 uint32_t bank0;
636 uint32_t bank1;
637 uint32_t bank2;
638 } intel_ich_gpio_table[] = {
639 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
640 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
641 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
642 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
643 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
644 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
645 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
646 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
647 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
648 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
649 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
650 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
651 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
652 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
653 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
654 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
655 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
656 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
657 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
658 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
659 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
660 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
661 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
662 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
663 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
664 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
665 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
666 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
667 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
668 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
669 {0, 0, 0, 0, 0} /* end marker */
670 };
Uwe Hermann93f66db2008-05-22 21:19:38 +0000671
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000672 struct pci_dev *dev;
673 uint16_t base;
674 uint32_t tmp;
675 int i, allowed;
676
677 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000678 for (dev = pacc->devices; dev; dev = dev->next) {
679 pci_fill_info(dev, PCI_FILL_CLASS);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000680 if ((dev->vendor_id == 0x8086) &&
681 (dev->device_class == 0x0601)) { /* ISA Bridge */
682 /* Is this device in our list? */
683 for (i = 0; intel_ich_gpio_table[i].id; i++)
684 if (dev->device_id == intel_ich_gpio_table[i].id)
685 break;
686
687 if (intel_ich_gpio_table[i].id)
688 break;
689 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000690 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000691
Uwe Hermann93f66db2008-05-22 21:19:38 +0000692 if (!dev) {
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000693 fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +0000694 return -1;
695 }
696
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000697 /* According to the datasheets, all intel ICHs have the gpio bar 5:1
698 strapped to zero. From some mobile ich9 version on, this becomes
699 6:1. The mask below catches all. */
700 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +0000701
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000702 /* check whether the line is allowed */
703 if (gpio < 32)
704 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
705 else if (gpio < 64)
706 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
707 else
708 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
709
710 if (!allowed) {
711 fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow"
712 " setting GPIO%02d\n", gpio);
713 return -1;
714 }
715
716 printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
717 raise ? "Rais" : "Dropp", gpio);
718
719 if (gpio < 32) {
720 /* Set line to GPIO */
721 tmp = INL(base);
722 /* ICH/ICH0 multiplexes 27/28 on the line set. */
723 if ((gpio == 28) &&
724 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
725 tmp |= 1 << 27;
726 else
727 tmp |= 1 << gpio;
728 OUTL(tmp, base);
729
730 /* As soon as we are talking to ICH8 and above, this register
731 decides whether we can set the gpio or not. */
732 if (dev->device_id > 0x2800) {
733 tmp = INL(base);
734 if (!(tmp & (1 << gpio))) {
735 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
736 " does not allow setting GPIO%02d\n",
737 gpio);
738 return -1;
739 }
740 }
741
742 /* Set GPIO to OUTPUT */
743 tmp = INL(base + 0x04);
744 tmp &= ~(1 << gpio);
745 OUTL(tmp, base + 0x04);
746
747 /* Raise GPIO line */
748 tmp = INL(base + 0x0C);
749 if (raise)
750 tmp |= 1 << gpio;
751 else
752 tmp &= ~(1 << gpio);
753 OUTL(tmp, base + 0x0C);
754 } else if (gpio < 64) {
755 gpio -= 32;
756
757 /* Set line to GPIO */
758 tmp = INL(base + 0x30);
759 tmp |= 1 << gpio;
760 OUTL(tmp, base + 0x30);
761
762 /* As soon as we are talking to ICH8 and above, this register
763 decides whether we can set the gpio or not. */
764 if (dev->device_id > 0x2800) {
765 tmp = INL(base + 30);
766 if (!(tmp & (1 << gpio))) {
767 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
768 " does not allow setting GPIO%02d\n",
769 gpio + 32);
770 return -1;
771 }
772 }
773
774 /* Set GPIO to OUTPUT */
775 tmp = INL(base + 0x34);
776 tmp &= ~(1 << gpio);
777 OUTL(tmp, base + 0x34);
778
779 /* Raise GPIO line */
780 tmp = INL(base + 0x38);
781 if (raise)
782 tmp |= 1 << gpio;
783 else
784 tmp &= ~(1 << gpio);
785 OUTL(tmp, base + 0x38);
786 } else {
787 gpio -= 64;
788
789 /* Set line to GPIO */
790 tmp = INL(base + 0x40);
791 tmp |= 1 << gpio;
792 OUTL(tmp, base + 0x40);
793
794 tmp = INL(base + 40);
795 if (!(tmp & (1 << gpio))) {
796 fprintf(stderr, "\nERROR: This Intel LPC Bridge does "
797 "not allow setting GPIO%02d\n", gpio + 64);
798 return -1;
799 }
800
801 /* Set GPIO to OUTPUT */
802 tmp = INL(base + 0x44);
803 tmp &= ~(1 << gpio);
804 OUTL(tmp, base + 0x44);
805
806 /* Raise GPIO line */
807 tmp = INL(base + 0x48);
808 if (raise)
809 tmp |= 1 << gpio;
810 else
811 tmp &= ~(1 << gpio);
812 OUTL(tmp, base + 0x48);
813 }
Uwe Hermann93f66db2008-05-22 21:19:38 +0000814
815 return 0;
816}
817
818/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000819 * Suited for Abit IP35: Intel P35 + ICH9R.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000820 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000821static int intel_ich_gpio16_raise(const char *name)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000822{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000823 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +0000824}
825
Peter Stuge09c13332009-02-02 22:55:26 +0000826/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000827 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000828 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000829static int intel_ich_gpio19_raise(const char *name)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000830{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000831 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000832}
833
834/**
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +0000835 * Suited for:
836 * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
837 * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
Peter Stuge09c13332009-02-02 22:55:26 +0000838 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000839static int intel_ich_gpio21_raise(const char *name)
Peter Stuge09c13332009-02-02 22:55:26 +0000840{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000841 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +0000842}
843
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000844/**
845 * Suited for ASUS P4B266: socket478 + intel 845D + ICH2.
846 */
847static int intel_ich_gpio22_raise(const char *name)
848{
849 return intel_ich_gpio_set(22, 1);
850}
851
852/**
Luc Verhaegen1265d8d2009-11-28 18:16:31 +0000853 * Suited for:
854 * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R.
855 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000856 */
857static int intel_ich_gpio23_raise(const char *name)
858{
859 return intel_ich_gpio_set(23, 1);
860}
861
862/**
863 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
864 */
865static int board_acorp_6a815epd(const char *name)
866{
867 int ret;
868
869 /* Lower Blocks Lock -- pin 7 of PLCC32 */
870 ret = intel_ich_gpio_set(22, 1);
871 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
872 ret = intel_ich_gpio_set(23, 1);
873
874 return ret;
875}
876
877/**
878 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
879 */
Stefan Reinauerac378972008-03-17 22:59:40 +0000880static int board_kontron_986lcd_m(const char *name)
881{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000882 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +0000883
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000884 ret = intel_ich_gpio_set(34, 1); /* #TBL */
885 if (!ret)
886 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +0000887
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000888 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +0000889}
890
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000891/**
Peter Stuge4aa71562008-06-11 02:22:42 +0000892 * Suited for:
Luc Verhaegen11793772009-07-21 01:44:45 +0000893 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
894 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
Luc Verhaegen73d21192009-12-23 00:54:26 +0000895 * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
Luc Verhaegen9892ca62009-12-09 07:43:13 +0000896 *
897 * SIS950 superio probably requires the same flash write enable.
Peter Stuge4aa71562008-06-11 02:22:42 +0000898 */
Luc Verhaegen11793772009-07-21 01:44:45 +0000899static int it8705_rom_write_enable(const char *name)
Peter Stuge4aa71562008-06-11 02:22:42 +0000900{
901 /* enter IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000902 enter_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000903
904 /* select right flash chip */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000905 sio_mask(0x2e, 0x22, 0x80, 0x80);
Peter Stuge4aa71562008-06-11 02:22:42 +0000906
907 /* bit 3: flash chip write enable
908 * bit 7: map flash chip at 1MB-128K (why though? ignoring this.)
909 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000910 sio_mask(0x2e, 0x24, 0x04, 0x04);
Peter Stuge4aa71562008-06-11 02:22:42 +0000911
912 /* exit IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000913 exit_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000914
915 return 0;
916}
917
918/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000919 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
920 */
921static int board_soyo_sy_7vca(const char *name)
922{
923 struct pci_dev *dev;
924 uint32_t base;
925 uint8_t tmp;
926
927 /* VT82C686 Power management */
928 dev = pci_dev_find(0x1106, 0x3057);
929 if (!dev) {
930 fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
931 return -1;
932 }
933
934 /* GPO0 output from PM IO base + 0x4C */
935 tmp = pci_read_byte(dev, 0x54);
936 tmp &= ~0x03;
937 pci_write_byte(dev, 0x54, tmp);
938
939 /* PM IO base */
940 base = pci_read_long(dev, 0x48) & 0x0000FF00;
941
942 /* Drop GPO0 */
943 tmp = INB(base + 0x4C);
944 tmp &= ~0x01;
945 OUTB(tmp, base + 0x4C);
946
947 return 0;
948}
949
Uwe Hermann265e7552009-06-21 15:45:34 +0000950static int it8705f_write_enable(uint8_t port, const char *name)
951{
952 enter_conf_mode_ite(port);
953 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
954 exit_conf_mode_ite(port);
955
956 return 0;
957}
958
959/**
Luc Verhaegenb843e202009-12-18 08:37:55 +0000960 * Suited for:
961 * - Elitegroup K7S6A: SiS745 + ITE IT8705F
962 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
Uwe Hermann265e7552009-06-21 15:45:34 +0000963 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000964static int elitegroup_k7vta3(const char *name)
Uwe Hermann265e7552009-06-21 15:45:34 +0000965{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000966 max_rom_decode.parallel = 256 * 1024;
967 return it8705f_write_enable(0x2e, name);
968}
969
970/**
971 * Suited for: Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
972 */
973static int shuttle_ak38n(const char *name)
974{
975 max_rom_decode.parallel = 256 * 1024;
Uwe Hermann265e7552009-06-21 15:45:34 +0000976 return it8705f_write_enable(0x2e, name);
977}
978
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000979/**
Michael Gold6d52e472009-06-19 13:00:24 +0000980 * Find the runtime registers of an SMSC Super I/O, after verifying its
981 * chip ID.
982 *
983 * Returns the base port of the runtime register block, or 0 on error.
984 */
985static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
986 uint8_t logical_device)
987{
988 uint16_t rt_port = 0;
989
990 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +0000991 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +0000992 if (sio_read(sio_port, 0x20) != chip_id) {
Uwe Hermann1432a602009-06-28 23:26:37 +0000993 fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +0000994 goto out;
995 }
996
997 /* If the runtime block is active, get its address. */
998 sio_write(sio_port, 0x07, logical_device);
999 if (sio_read(sio_port, 0x30) & 1) {
1000 rt_port = (sio_read(sio_port, 0x60) << 8)
1001 | sio_read(sio_port, 0x61);
1002 }
1003
1004 if (rt_port == 0) {
1005 fprintf(stderr, "\nERROR: "
1006 "Super I/O runtime interface not available.\n");
1007 }
1008out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001009 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001010 return rt_port;
1011}
1012
1013/**
1014 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
1015 * connected to GP30 on the Super I/O, and TBL# is always high.
1016 */
1017static int board_mitac_6513wu(const char *name)
1018{
1019 struct pci_dev *dev;
1020 uint16_t rt_port;
1021 uint8_t val;
1022
1023 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1024 if (!dev) {
1025 fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
1026 return -1;
1027 }
1028
Uwe Hermann1432a602009-06-28 23:26:37 +00001029 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001030 if (rt_port == 0)
1031 return -1;
1032
1033 /* Configure the GPIO pin. */
1034 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001035 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001036 OUTB(val, rt_port + 0x33);
1037
1038 /* Disable write protection. */
1039 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001040 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001041 OUTB(val, rt_port + 0x4d);
1042
1043 return 0;
1044}
1045
1046/**
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001047 * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
1048 */
1049static int board_asus_a7v8x(const char *name)
1050{
1051 uint16_t id, base;
1052 uint8_t tmp;
1053
1054 /* find the IT8703F */
1055 w836xx_ext_enter(0x2E);
1056 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1057 w836xx_ext_leave(0x2E);
1058
1059 if (id != 0x8701) {
1060 fprintf(stderr, "\nERROR: IT8703F SuperIO not found.\n");
1061 return -1;
1062 }
1063
1064 /* Get the GP567 IO base */
1065 w836xx_ext_enter(0x2E);
1066 sio_write(0x2E, 0x07, 0x0C);
1067 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1068 w836xx_ext_leave(0x2E);
1069
1070 if (!base) {
1071 fprintf(stderr, "\nERROR: Failed to read IT8703F SuperIO GPIO"
1072 " Base.\n");
1073 return -1;
1074 }
1075
1076 /* Raise GP51. */
1077 tmp = INB(base);
1078 tmp |= 0x02;
1079 OUTB(tmp, base);
1080
1081 return 0;
1082}
1083
Luc Verhaegen72272912009-09-01 21:22:23 +00001084/*
1085 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1086 * There is only some limited checking on the port numbers.
1087 */
1088static int
1089it8712f_gpio_set(unsigned int line, int raise)
1090{
1091 unsigned int port;
1092 uint16_t id, base;
1093 uint8_t tmp;
1094
1095 port = line / 10;
1096 port--;
1097 line %= 10;
1098
1099 /* Check line */
1100 if ((port > 4) || /* also catches unsigned -1 */
1101 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
1102 fprintf(stderr,
1103 "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
1104 return -1;
1105 }
1106
1107 /* find the IT8712F */
1108 enter_conf_mode_ite(0x2E);
1109 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1110 exit_conf_mode_ite(0x2E);
1111
1112 if (id != 0x8712) {
1113 fprintf(stderr, "\nERROR: IT8712F SuperIO not found.\n");
1114 return -1;
1115 }
1116
1117 /* Get the GPIO base */
1118 enter_conf_mode_ite(0x2E);
1119 sio_write(0x2E, 0x07, 0x07);
1120 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1121 exit_conf_mode_ite(0x2E);
1122
1123 if (!base) {
1124 fprintf(stderr, "\nERROR: Failed to read IT8712F SuperIO GPIO"
1125 " Base.\n");
1126 return -1;
1127 }
1128
1129 /* set GPIO. */
1130 tmp = INB(base + port);
1131 if (raise)
1132 tmp |= 1 << line;
1133 else
1134 tmp &= ~(1 << line);
1135 OUTB(tmp, base + port);
1136
1137 return 0;
1138}
1139
1140/**
1141 * Suited for Asus A7V600-X: VIA KT600 + VT8237 + IT8712F
1142 */
1143static int board_asus_a7v600x(const char *name)
1144{
1145 return it8712f_gpio_set(32, 1);
1146}
1147
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001148/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001149 * Below is the list of boards which need a special "board enable" code in
1150 * flashrom before their ROM chip can be accessed/written to.
1151 *
1152 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1153 * to the respective tables in print.c. Thanks!
1154 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001155 * We use 2 sets of IDs here, you're free to choose which is which. This
1156 * is to provide a very high degree of certainty when matching a board on
1157 * the basis of subsystem/card IDs. As not every vendor handles
1158 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001159 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001160 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
1161 * NULLed if they don't identify the board fully. But please take care to
1162 * provide an as complete set of pci ids as possible; autodetection is the
1163 * preferred behaviour and we would like to make sure that matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001164 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001165 * The coreboot ids are used two fold. When running with a coreboot firmware,
1166 * the ids uniquely matches the coreboot board identification string. When a
1167 * legacy bios is installed and when autodetection is not possible, these ids
1168 * can be used to identify the board through the -m command line argument.
1169 *
1170 * When a board is identified through its coreboot ids (in both cases), the
1171 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001172 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001173
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001174/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001175struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermannab60a432009-05-23 00:56:49 +00001176 /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001177 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001178 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, "Acorp", "6A815EPD", board_acorp_6a815epd},
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001179 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001180 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e},
Luc Verhaegen0f9221c2009-11-29 01:19:25 +00001181 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e},
Luc Verhaegen73d21192009-12-23 00:54:26 +00001182 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", it8705_rom_write_enable},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001183 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x},
1184 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x},
Luc Verhaegen72272912009-09-01 21:22:23 +00001185 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x},
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001186 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x},
Luc Verhaegen73d21192009-12-23 00:54:26 +00001187 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e},
1188 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", via_vt823x_gpio5_raise},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001189 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise},
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001190 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001191 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001192 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a},
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001193 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise},
Luc Verhaegen11793772009-07-21 01:44:45 +00001194 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001195 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise},
Luc Verhaegenb843e202009-12-18 08:37:55 +00001196 {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, "Elitegroup", "K7S6A", elitegroup_k7vta3},
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001197 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", elitegroup_k7vta3},
Luc Verhaegen0f9221c2009-11-29 01:19:25 +00001198 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e},
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001199 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001200 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001201 {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash},
Luc Verhaegen11793772009-07-21 01:44:45 +00001202 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable},
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001203 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001204 {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash},
1205 {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash},
Uwe Hermann0495c942009-05-18 22:27:53 +00001206 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash},
1207 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001208 {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001209 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001210 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, "IBM", "x3455", board_ibm_x3455},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001211 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi},
1212 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001213 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m},
Michael Gold6d52e472009-06-19 13:00:24 +00001214 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001215 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v},
Uwe Hermannd1129ac2009-05-28 15:07:42 +00001216 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e},
Luc Verhaegen4802a7b2009-11-28 21:12:58 +00001217 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001218 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001219 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001220 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, "MSI", "K8N Neo4-F", nvidia_mcp_gpio2_raise},
Luc Verhaegen0f9221c2009-11-29 01:19:25 +00001221 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e},
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001222 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n},
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001223 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001224 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
Luc Verhaegen73d21192009-12-23 00:54:26 +00001225 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", w836xx_memw_enable_2e},
1226 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", via_vt823x_gpio15_raise},
1227 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", via_vt823x_gpio9_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001228 {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash},
Uwe Hermann5ab88892009-06-21 20:50:22 +00001229
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001230 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001231};
1232
Uwe Hermannffec5f32007-08-23 16:08:21 +00001233/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001234 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001235 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001236 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001237static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1238 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001239{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001240 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001241 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001242
Uwe Hermanna93045c2009-05-09 00:47:04 +00001243 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001244 if (vendor && (!board->lb_vendor
1245 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001246 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001247
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001248 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001249 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001250
Uwe Hermanna7e05482007-05-09 10:17:44 +00001251 if (!pci_dev_find(board->first_vendor, board->first_device))
1252 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001253
Uwe Hermanna7e05482007-05-09 10:17:44 +00001254 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001255 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001256 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001257
1258 if (vendor)
1259 return board;
1260
1261 if (partmatch) {
1262 /* a second entry has a matching part name */
1263 printf("AMBIGUOUS BOARD NAME: %s\n", part);
1264 printf("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001265 partmatch->lb_vendor, board->lb_vendor);
Peter Stuge6b53fed2008-01-27 16:21:21 +00001266 printf("Please use the full -m vendor:part syntax.\n");
1267 return NULL;
1268 }
1269 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001270 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001271
Peter Stuge6b53fed2008-01-27 16:21:21 +00001272 if (partmatch)
1273 return partmatch;
1274
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001275 if (!partvendor_from_cbtable) {
1276 /* Only warn if the mainboard type was not gathered from the
1277 * coreboot table. If it was, the coreboot implementor is
1278 * expected to fix flashrom, too.
1279 */
1280 printf("\nUnknown vendor:board from -m option: %s:%s\n\n",
1281 vendor, part);
1282 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001283 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001284}
1285
Uwe Hermannffec5f32007-08-23 16:08:21 +00001286/**
1287 * Match boards on PCI IDs and subsystem IDs.
1288 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001289 */
1290static struct board_pciid_enable *board_match_pci_card_ids(void)
1291{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001292 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001293
Uwe Hermanna93045c2009-05-09 00:47:04 +00001294 for (; board->vendor_name; board++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +00001295 if (!board->first_card_vendor || !board->first_card_device)
1296 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001297
Uwe Hermanna7e05482007-05-09 10:17:44 +00001298 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001299 board->first_card_vendor,
1300 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001301 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001302
Uwe Hermanna7e05482007-05-09 10:17:44 +00001303 if (board->second_vendor) {
1304 if (board->second_card_vendor) {
1305 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001306 board->second_device,
1307 board->second_card_vendor,
1308 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001309 continue;
1310 } else {
1311 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001312 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001313 continue;
1314 }
1315 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001316
Uwe Hermanna7e05482007-05-09 10:17:44 +00001317 return board;
1318 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001319
Uwe Hermanna7e05482007-05-09 10:17:44 +00001320 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001321}
1322
Uwe Hermann372eeb52007-12-04 21:49:06 +00001323int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001324{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001325 struct board_pciid_enable *board = NULL;
1326 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001327
Peter Stuge6b53fed2008-01-27 16:21:21 +00001328 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001329 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001330
Uwe Hermanna7e05482007-05-09 10:17:44 +00001331 if (!board)
1332 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001333
Uwe Hermanna7e05482007-05-09 10:17:44 +00001334 if (board) {
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001335 printf("Disabling flash write protection for board \"%s %s\"... ",
Uwe Hermanna93045c2009-05-09 00:47:04 +00001336 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001337
Uwe Hermanna93045c2009-05-09 00:47:04 +00001338 ret = board->enable(board->vendor_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001339 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001340 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001341 else
1342 printf("OK.\n");
1343 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001344
Uwe Hermanna7e05482007-05-09 10:17:44 +00001345 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001346}