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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Uwe Hermannffec5f32007-08-23 16:08:21 +000069/**
70 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000071 *
72 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +000073 * - Agami Aruma
74 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000075 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000076static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000077{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000078 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000079
Uwe Hermann372eeb52007-12-04 21:49:06 +000080 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000081 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000082 fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000083 name, sio_read(port, 0x20));
84 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000085 return -1;
86 }
87
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000088 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000089 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000090
Uwe Hermann372eeb52007-12-04 21:49:06 +000091 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000092 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000093
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000094 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
95 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
96 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
97 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000098
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000099 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000100
101 return 0;
102}
103
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000104static int w83627hf_gpio24_raise_2e(const char *name)
105{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000106 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000107}
108
109/**
110 * Winbond W83627THF: GPIO 4, bit 4
111 *
112 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000113 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000114 * - MSI K8N-NEO3
115 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000116static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000117{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000119
120 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000122 fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 name, sio_read(port, 0x20));
124 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000125 return -1;
126 }
127
128 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
129
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000130 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
131 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
132 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
133 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
134 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000135
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000136 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000137
138 return 0;
139}
140
Peter Stugecce26822008-07-21 17:48:40 +0000141static int w83627thf_gpio4_4_raise_2e(const char *name)
142{
143 return w83627thf_gpio4_4_raise(0x2e, name);
144}
145
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146static int w83627thf_gpio4_4_raise_4e(const char *name)
147{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000149}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000150
Uwe Hermannffec5f32007-08-23 16:08:21 +0000151/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000152 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000153 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000154static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000155{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000156 w836xx_ext_enter(port);
157 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000158 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000160 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000161 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000162}
163
164/**
165 * Common routine for several VT823x based boards.
166 */
167static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev)
168{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000169 uint8_t val;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000170
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000171 /* All memory cycles, not just ROM ones, go to LPC. */
172 val = pci_read_byte(dev, 0x59);
173 val &= ~0x80;
174 pci_write_byte(dev, 0x59, val);
175}
176
177/**
178 * VT823x: Set one of the GPIO pins.
179 */
180static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
181{
182 uint16_t base;
183 uint8_t val, bit;
184
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000185 if ((gpio >= 12) && (gpio <= 15)) {
186 /* GPIO12-15 -> output */
187 val = pci_read_byte(dev, 0xE4);
188 val |= 0x10;
189 pci_write_byte(dev, 0xE4, val);
190 } else if (gpio == 9) {
191 /* GPIO9 -> Output */
192 val = pci_read_byte(dev, 0xE4);
193 val |= 0x20;
194 pci_write_byte(dev, 0xE4, val);
195 } else {
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000196 fprintf(stderr, "\nERROR: "
197 "VT823x GPIO%02d is not implemented.\n", gpio);
198 return;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000199 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000200
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000201 /* Now raise/drop the GPIO line itself. */
202 bit = 0x01 << (gpio - 8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000203
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000204 /* We need the I/O Base Address for this board's flash enable. */
205 base = pci_read_word(dev, 0x88) & 0xff80;
206
Andriy Gapon65c1b862008-05-22 13:22:45 +0000207 val = INB(base + 0x4D);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000208 if (raise)
209 val |= bit;
210 else
211 val &= ~bit;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000212 OUTB(val, base + 0x4D);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000213}
214
215/**
216 * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
217 *
218 * We don't need to do this when using coreboot, GPIO15 is never lowered there.
219 */
220static int board_via_epia_m(const char *name)
221{
222 struct pci_dev *dev;
223
224 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
225 if (!dev) {
226 fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
227 return -1;
228 }
229
230 /* GPIO15 is connected to write protect. */
231 vt823x_gpio_set(dev, 15, 1);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000232
Uwe Hermanna7e05482007-05-09 10:17:44 +0000233 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000234}
235
Uwe Hermannffec5f32007-08-23 16:08:21 +0000236/**
Luc Verhaegen32707542007-07-04 17:51:49 +0000237 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000238 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000239 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000240 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000241static int board_asus_a7v8x_mx(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000242{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000243 struct pci_dev *dev;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000244
Uwe Hermanna7e05482007-05-09 10:17:44 +0000245 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
Luc Verhaegen32707542007-07-04 17:51:49 +0000246 if (!dev)
247 dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000248 if (!dev) {
Luc Verhaegen32707542007-07-04 17:51:49 +0000249 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000250 return -1;
251 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000252
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000253 vt823x_set_all_writes_to_lpc(dev);
254 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000255
Uwe Hermanna7e05482007-05-09 10:17:44 +0000256 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000257}
258
Uwe Hermannffec5f32007-08-23 16:08:21 +0000259/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000260 * Suited for VIAs EPIA SP and EPIA CN.
Luc Verhaegen97866082008-02-09 02:03:06 +0000261 */
262static int board_via_epia_sp(const char *name)
263{
264 struct pci_dev *dev;
Luc Verhaegen97866082008-02-09 02:03:06 +0000265
266 dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
267 if (!dev) {
268 fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
269 return -1;
270 }
271
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000272 vt823x_set_all_writes_to_lpc(dev);
273
274 return 0;
275}
276
277/**
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000278 * Suited for VIAs EPIA N & NL.
279 */
280static int board_via_epia_n(const char *name)
281{
282 struct pci_dev *dev;
283
284 dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
285 if (!dev) {
286 fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
287 return -1;
288 }
289
290 /* All memory cycles, not just ROM ones, go to LPC */
291 vt823x_set_all_writes_to_lpc(dev);
292
293 /* GPIO9 -> output */
294 vt823x_gpio_set(dev, 9, 1);
295
296 return 0;
297}
298
299/**
Uwe Hermann04d5dc42009-07-03 17:12:05 +0000300 * Suited for EPoX EP-8K5A2 and Albatron PM266A Pro.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000301 */
302static int board_epox_ep_8k5a2(const char *name)
303{
304 struct pci_dev *dev;
305
306 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
307 if (!dev) {
308 fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
309 return -1;
310 }
311
312 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000313
314 return 0;
315}
316
317/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000318 * Suited for ASUS P5A.
319 *
320 * This is rather nasty code, but there's no way to do this cleanly.
321 * We're basically talking to some unknown device on SMBus, my guess
322 * is that it is the Winbond W83781D that lives near the DIP BIOS.
323 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000324static int board_asus_p5a(const char *name)
325{
326 uint8_t tmp;
327 int i;
328
329#define ASUSP5A_LOOP 5000
330
Andriy Gapon65c1b862008-05-22 13:22:45 +0000331 OUTB(0x00, 0xE807);
332 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000333
Andriy Gapon65c1b862008-05-22 13:22:45 +0000334 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000335
336 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000337 OUTB(0xE1, 0xFF);
338 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000339 break;
340 }
341
342 if (i == ASUSP5A_LOOP) {
343 printf("%s: Unable to contact device.\n", name);
344 return -1;
345 }
346
Andriy Gapon65c1b862008-05-22 13:22:45 +0000347 OUTB(0x20, 0xE801);
348 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000349
Andriy Gapon65c1b862008-05-22 13:22:45 +0000350 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000351
352 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000353 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000354 if (tmp & 0x70)
355 break;
356 }
357
358 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
359 printf("%s: failed to read device.\n", name);
360 return -1;
361 }
362
Andriy Gapon65c1b862008-05-22 13:22:45 +0000363 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000364 tmp &= ~0x02;
365
Andriy Gapon65c1b862008-05-22 13:22:45 +0000366 OUTB(0x00, 0xE807);
367 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000368
Andriy Gapon65c1b862008-05-22 13:22:45 +0000369 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000370
Andriy Gapon65c1b862008-05-22 13:22:45 +0000371 OUTB(0xFF, 0xE800);
372 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000373
Andriy Gapon65c1b862008-05-22 13:22:45 +0000374 OUTB(0x20, 0xE801);
375 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000376
Andriy Gapon65c1b862008-05-22 13:22:45 +0000377 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000378
379 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000380 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000381 if (tmp & 0x70)
382 break;
383 }
384
385 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
386 printf("%s: failed to write to device.\n", name);
387 return -1;
388 }
389
390 return 0;
391}
392
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000393static int board_ibm_x3455(const char *name)
394{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000395 /* Set GPIO lines in the Broadcom HT-1000 southbridge. */
Uwe Hermann1432a602009-06-28 23:26:37 +0000396 /* It's not a Super I/O but it uses the same index/data port method. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000397 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000398
399 return 0;
400}
401
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000402/**
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000403 * No docs, so we are just guessing that these might be individual gpio lines.
404 */
405static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset)
406{
407 uint16_t base;
408 uint8_t tmp;
409
410 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
411
412 base += 0xC0;
413
414 /* if anyone knows more about nvidia mcps, feel free to explain this */
415 tmp = INB(base + offset);
416 tmp &= ~0x0F;
417 tmp |= 0x05;
418 OUTB(tmp, base + offset);
419}
420
421/**
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000422 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
423 */
424static int board_ga_k8n_sli(const char *name)
425{
426 struct pci_dev *dev;
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000427
428 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */
429 if (!dev) {
430 fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n");
431 return -1;
432 }
433
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000434 nvidia_mcp_gpio_raise(dev, 0x21);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000435
436 return 0;
437}
438
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000439/**
440 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
441 */
442static int board_asus_p5nd2_sli(const char *name)
443{
444 struct pci_dev *dev;
445
446 dev = pci_dev_find(0x10DE, 0x0030); /* NVIDIA nForce4 ISA Bridge */
447 if (!dev) {
448 fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n");
449 return -1;
450 }
451
452 nvidia_mcp_gpio_raise(dev, 0x10);
453
454 return 0;
455}
456
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000457/**
458 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
459 */
460static int board_epox_ep_8rda3plus(const char *name)
461{
462 struct pci_dev *dev;
463
464 dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */
465 if (!dev) {
466 fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n");
467 return -1;
468 }
469
470 nvidia_mcp_gpio_raise(dev, 0x31);
471
472 return 0;
473}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000474
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000475static int board_hp_dl145_g3_enable(const char *name)
476{
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000477 /* Set GPIO lines in the Broadcom HT-1000 southbridge. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000478 /* GPIO 0 reg from PM regs */
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000479 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
Uwe Hermann1432a602009-06-28 23:26:37 +0000480 /* It's not a Super I/O but it uses the same index/data port method. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000481 sio_mask(0xcd6, 0x44, 0x24, 0x24);
Mondrian Nuessled5df3302009-03-30 13:20:01 +0000482
483 return 0;
484}
485
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000486/**
487 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
488 */
489static int board_epox_ep_bx3(const char *name)
490{
491 uint8_t tmp;
492
493 /* Raise GPIO22. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000494 tmp = INB(0x4036);
495 OUTB(tmp, 0xEB);
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000496
497 tmp |= 0x40;
498
Andriy Gapon65c1b862008-05-22 13:22:45 +0000499 OUTB(tmp, 0x4036);
500 OUTB(tmp, 0xEB);
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000501
502 return 0;
503}
504
Uwe Hermannffec5f32007-08-23 16:08:21 +0000505/**
Uwe Hermann372eeb52007-12-04 21:49:06 +0000506 * Suited for Acorp 6A815EPD.
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000507 */
508static int board_acorp_6a815epd(const char *name)
509{
510 struct pci_dev *dev;
511 uint16_t port;
512 uint8_t val;
513
Uwe Hermann394131e2008-10-18 21:14:13 +0000514 dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000515 if (!dev) {
516 fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n");
517 return -1;
518 }
519
520 /* Use GPIOBASE register to find where the GPIO is mapped. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000521 port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE;
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000522
Andriy Gapon65c1b862008-05-22 13:22:45 +0000523 val = INB(port);
Uwe Hermann394131e2008-10-18 21:14:13 +0000524 val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
525 val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000526 OUTB(val, port);
Jonathan A. Kollaschc7785562007-12-02 19:03:23 +0000527
528 return 0;
529}
530
531/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000532 * Suited for Artec Group DBE61 and DBE62.
533 */
534static int board_artecgroup_dbe6x(const char *name)
535{
536#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
537#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
538#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
539#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
540#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
541#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
542#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
543#define DBE6x_BOOT_LOC_FLASH (2)
544#define DBE6x_BOOT_LOC_FWHUB (3)
545
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000546 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000547 unsigned long boot_loc;
548
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000549 /* Geode only has a single core */
550 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000551 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000552
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000553 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000554
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000555 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000556 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
557 boot_loc = DBE6x_BOOT_LOC_FWHUB;
558 else
559 boot_loc = DBE6x_BOOT_LOC_FLASH;
560
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000561 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
562 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000563 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000564
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000565 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000566
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000567 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000568
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000569 return 0;
570}
571
Uwe Hermann93f66db2008-05-22 21:19:38 +0000572/**
573 * Set the specified GPIO on the specified ICHx southbridge to high.
574 *
575 * @param name The name of this board.
576 * @param ich_vendor PCI vendor ID of the specified ICHx southbridge.
577 * @param ich_device PCI device ID of the specified ICHx southbridge.
578 * @param gpiobase_reg GPIOBASE register offset in the LPC bridge.
579 * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE.
580 * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0).
581 * @param gpio_bit The bit (GPIO) which shall be set to high.
582 * @return If the write-enable was successful return 0, otherwise return -1.
583 */
584static int ich_gpio_raise(const char *name, uint16_t ich_vendor,
585 uint16_t ich_device, uint8_t gpiobase_reg,
586 uint8_t gp_lvl, uint32_t gp_lvl_bitmask,
587 unsigned int gpio_bit)
588{
589 struct pci_dev *dev;
590 uint16_t gpiobar;
591 uint32_t reg32;
592
Uwe Hermann394131e2008-10-18 21:14:13 +0000593 dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */
Uwe Hermann93f66db2008-05-22 21:19:38 +0000594 if (!dev) {
595 fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n",
596 ich_vendor, ich_device);
597 return -1;
598 }
599
600 /* Use GPIOBASE register to find the I/O space for GPIO. */
601 gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask;
602
603 /* Set specified GPIO to high. */
604 reg32 = INL(gpiobar + gp_lvl);
605 reg32 |= (1 << gpio_bit);
606 OUTL(reg32, gpiobar + gp_lvl);
607
608 return 0;
609}
610
611/**
612 * Suited for ASUS P4B266.
613 */
614static int ich2_gpio22_raise(const char *name)
615{
616 return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22);
617}
618
Peter Stuge09c13332009-02-02 22:55:26 +0000619/**
Uwe Hermann14b3e1e2009-10-06 20:23:29 +0000620 * Suited for the Dell PowerEdge 1850. All parameters except the last one are
621 * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The
622 * last parameter (GPIO number) has to be in the range [16,31] according to
623 * said Intel datasheet and was found by exhaustive search.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000624 */
625static int ich5_gpio23_raise(const char *name)
626{
627 return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23);
628}
629
630/**
Peter Stuge09c13332009-02-02 22:55:26 +0000631 * Suited for MSI MS-7046.
632 */
633static int ich6_gpio19_raise(const char *name)
634{
635 return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19);
636}
637
Stefan Reinauerac378972008-03-17 22:59:40 +0000638static int board_kontron_986lcd_m(const char *name)
639{
640 struct pci_dev *dev;
641 uint16_t gpiobar;
642 uint32_t val;
643
644#define ICH7_GPIO_LVL2 0x38
645
Uwe Hermann394131e2008-10-18 21:14:13 +0000646 dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */
Stefan Reinauerac378972008-03-17 22:59:40 +0000647 if (!dev) {
648 // This will never happen on this board
649 fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n");
650 return -1;
651 }
652
653 /* Use GPIOBASE register to find where the GPIO is mapped. */
654 gpiobar = pci_read_word(dev, 0x48) & 0xfffc;
655
Andriy Gapon65c1b862008-05-22 13:22:45 +0000656 val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */
Stefan Reinauerac378972008-03-17 22:59:40 +0000657 printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val);
658
659 /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1
660 * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0
661 * bit 3 (0x08) = 0 #WP --> block locking = 1
662 * bit 3 (0x08) = 1 #WP --> block locking = 0
663 *
664 * To enable full block locking, you would do:
665 * val &= ~ ((1 << 2) | (1 << 3));
666 */
667 val |= (1 << 2) | (1 << 3);
668
Andriy Gapon65c1b862008-05-22 13:22:45 +0000669 OUTL(val, gpiobar + ICH7_GPIO_LVL2);
Stefan Reinauerac378972008-03-17 22:59:40 +0000670
671 return 0;
672}
673
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000674/**
Peter Stuge4aa71562008-06-11 02:22:42 +0000675 * Suited for:
Luc Verhaegen11793772009-07-21 01:44:45 +0000676 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
677 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
Peter Stuge4aa71562008-06-11 02:22:42 +0000678 */
Luc Verhaegen11793772009-07-21 01:44:45 +0000679static int it8705_rom_write_enable(const char *name)
Peter Stuge4aa71562008-06-11 02:22:42 +0000680{
681 /* enter IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000682 enter_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000683
684 /* select right flash chip */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000685 sio_mask(0x2e, 0x22, 0x80, 0x80);
Peter Stuge4aa71562008-06-11 02:22:42 +0000686
687 /* bit 3: flash chip write enable
688 * bit 7: map flash chip at 1MB-128K (why though? ignoring this.)
689 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000690 sio_mask(0x2e, 0x24, 0x04, 0x04);
Peter Stuge4aa71562008-06-11 02:22:42 +0000691
692 /* exit IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000693 exit_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000694
695 return 0;
696}
697
698/**
Uwe Hermanna02d6662009-08-20 18:45:18 +0000699 * Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
Luc Verhaegen11793772009-07-21 01:44:45 +0000700 */
701static int board_aopen_vkm400(const char *name)
702{
703 struct pci_dev *dev;
704
705 dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
706 if (!dev) {
707 fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n");
708 return -1;
709 }
710
711 vt823x_set_all_writes_to_lpc(dev);
712
713 return it8705_rom_write_enable(name);
714}
715
716/**
Sean Nelsonb20953c2008-08-19 21:51:39 +0000717 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
718 *
719 * Suited for:
720 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
Uwe Hermannab60a432009-05-23 00:56:49 +0000721 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Sean Nelsonb20953c2008-08-19 21:51:39 +0000722 * - MSI KT3 Ultra2: AMD K7 + VIA KT333 + VT8235
723 */
724static int board_msi_kt4v(const char *name)
725{
726 struct pci_dev *dev;
727 uint8_t val;
Sean Nelsonb20953c2008-08-19 21:51:39 +0000728
729 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
730 if (!dev) {
731 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
732 return -1;
733 }
734
735 val = pci_read_byte(dev, 0x59);
736 val &= 0x0c;
737 pci_write_byte(dev, 0x59, val);
738
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000739 vt823x_gpio_set(dev, 12, 1);
740 w836xx_memw_enable(0x2E);
Sean Nelsonb20953c2008-08-19 21:51:39 +0000741
742 return 0;
743}
744
745/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000746 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
747 */
748static int board_soyo_sy_7vca(const char *name)
749{
750 struct pci_dev *dev;
751 uint32_t base;
752 uint8_t tmp;
753
754 /* VT82C686 Power management */
755 dev = pci_dev_find(0x1106, 0x3057);
756 if (!dev) {
757 fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
758 return -1;
759 }
760
761 /* GPO0 output from PM IO base + 0x4C */
762 tmp = pci_read_byte(dev, 0x54);
763 tmp &= ~0x03;
764 pci_write_byte(dev, 0x54, tmp);
765
766 /* PM IO base */
767 base = pci_read_long(dev, 0x48) & 0x0000FF00;
768
769 /* Drop GPO0 */
770 tmp = INB(base + 0x4C);
771 tmp &= ~0x01;
772 OUTB(tmp, base + 0x4C);
773
774 return 0;
775}
776
Uwe Hermann265e7552009-06-21 15:45:34 +0000777static int it8705f_write_enable(uint8_t port, const char *name)
778{
779 enter_conf_mode_ite(port);
780 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
781 exit_conf_mode_ite(port);
782
783 return 0;
784}
785
786/**
Uwe Hermann5ab88892009-06-21 20:50:22 +0000787 * Suited for:
788 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
789 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
Uwe Hermann265e7552009-06-21 15:45:34 +0000790 */
791static int it8705f_write_enable_2e(const char *name)
792{
793 return it8705f_write_enable(0x2e, name);
794}
795
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000796/**
Michael Gold6d52e472009-06-19 13:00:24 +0000797 * Find the runtime registers of an SMSC Super I/O, after verifying its
798 * chip ID.
799 *
800 * Returns the base port of the runtime register block, or 0 on error.
801 */
802static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
803 uint8_t logical_device)
804{
805 uint16_t rt_port = 0;
806
807 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +0000808 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +0000809 if (sio_read(sio_port, 0x20) != chip_id) {
Uwe Hermann1432a602009-06-28 23:26:37 +0000810 fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +0000811 goto out;
812 }
813
814 /* If the runtime block is active, get its address. */
815 sio_write(sio_port, 0x07, logical_device);
816 if (sio_read(sio_port, 0x30) & 1) {
817 rt_port = (sio_read(sio_port, 0x60) << 8)
818 | sio_read(sio_port, 0x61);
819 }
820
821 if (rt_port == 0) {
822 fprintf(stderr, "\nERROR: "
823 "Super I/O runtime interface not available.\n");
824 }
825out:
Uwe Hermann1432a602009-06-28 23:26:37 +0000826 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +0000827 return rt_port;
828}
829
830/**
831 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
832 * connected to GP30 on the Super I/O, and TBL# is always high.
833 */
834static int board_mitac_6513wu(const char *name)
835{
836 struct pci_dev *dev;
837 uint16_t rt_port;
838 uint8_t val;
839
840 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
841 if (!dev) {
842 fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
843 return -1;
844 }
845
Uwe Hermann1432a602009-06-28 23:26:37 +0000846 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +0000847 if (rt_port == 0)
848 return -1;
849
850 /* Configure the GPIO pin. */
851 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +0000852 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +0000853 OUTB(val, rt_port + 0x33);
854
855 /* Disable write protection. */
856 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +0000857 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +0000858 OUTB(val, rt_port + 0x4d);
859
860 return 0;
861}
862
863/**
Luc Verhaegen2f1d0a52009-07-06 22:58:46 +0000864 * Suited for Abit IP35: Intel P35 + ICH9R.
865 */
866static int board_abit_ip35(const char *name)
867{
868 struct pci_dev *dev;
869 uint16_t base;
870 uint8_t tmp;
871
872 dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */
873 if (!dev) {
874 fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n");
875 return -1;
876 }
877
878 /* get LPC GPIO base */
879 base = pci_read_long(dev, 0x48) & 0x0000FFC0;
880
881 /* Raise GPIO 16 */
882 tmp = INB(base + 0x0E);
883 tmp |= 0x01;
884 OUTB(tmp, base + 0x0E);
885
886 return 0;
887}
888
889/**
Luc Verhaegen78e4e122009-07-13 12:40:17 +0000890 * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
891 */
892static int board_asus_a7v8x(const char *name)
893{
894 uint16_t id, base;
895 uint8_t tmp;
896
897 /* find the IT8703F */
898 w836xx_ext_enter(0x2E);
899 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
900 w836xx_ext_leave(0x2E);
901
902 if (id != 0x8701) {
903 fprintf(stderr, "\nERROR: IT8703F SuperIO not found.\n");
904 return -1;
905 }
906
907 /* Get the GP567 IO base */
908 w836xx_ext_enter(0x2E);
909 sio_write(0x2E, 0x07, 0x0C);
910 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
911 w836xx_ext_leave(0x2E);
912
913 if (!base) {
914 fprintf(stderr, "\nERROR: Failed to read IT8703F SuperIO GPIO"
915 " Base.\n");
916 return -1;
917 }
918
919 /* Raise GP51. */
920 tmp = INB(base);
921 tmp |= 0x02;
922 OUTB(tmp, base);
923
924 return 0;
925}
926
Luc Verhaegen72272912009-09-01 21:22:23 +0000927/*
928 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
929 * There is only some limited checking on the port numbers.
930 */
931static int
932it8712f_gpio_set(unsigned int line, int raise)
933{
934 unsigned int port;
935 uint16_t id, base;
936 uint8_t tmp;
937
938 port = line / 10;
939 port--;
940 line %= 10;
941
942 /* Check line */
943 if ((port > 4) || /* also catches unsigned -1 */
944 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
945 fprintf(stderr,
946 "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
947 return -1;
948 }
949
950 /* find the IT8712F */
951 enter_conf_mode_ite(0x2E);
952 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
953 exit_conf_mode_ite(0x2E);
954
955 if (id != 0x8712) {
956 fprintf(stderr, "\nERROR: IT8712F SuperIO not found.\n");
957 return -1;
958 }
959
960 /* Get the GPIO base */
961 enter_conf_mode_ite(0x2E);
962 sio_write(0x2E, 0x07, 0x07);
963 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
964 exit_conf_mode_ite(0x2E);
965
966 if (!base) {
967 fprintf(stderr, "\nERROR: Failed to read IT8712F SuperIO GPIO"
968 " Base.\n");
969 return -1;
970 }
971
972 /* set GPIO. */
973 tmp = INB(base + port);
974 if (raise)
975 tmp |= 1 << line;
976 else
977 tmp &= ~(1 << line);
978 OUTB(tmp, base + port);
979
980 return 0;
981}
982
983/**
984 * Suited for Asus A7V600-X: VIA KT600 + VT8237 + IT8712F
985 */
986static int board_asus_a7v600x(const char *name)
987{
988 return it8712f_gpio_set(32, 1);
989}
990
Luc Verhaegen78e4e122009-07-13 12:40:17 +0000991/**
Uwe Hermanna02d6662009-08-20 18:45:18 +0000992 * Suited for Asus P4P800-E Deluxe: Intel Intel 865PE + ICH5R.
Luc Verhaegen4eeb7132009-08-12 16:58:11 +0000993 */
994static int board_asus_p4p800(const char *name)
995{
996 struct pci_dev *dev;
997 uint16_t base;
998 uint8_t tmp;
999
1000 dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */
1001 if (!dev) {
1002 fprintf(stderr, "\nERROR: Intel ICH5R ISA Bridge not found.\n");
1003 return -1;
1004 }
1005
1006 /* get PM IO base */
1007 base = pci_read_long(dev, 0x58) & 0x0000FFC0;
1008
1009 /* Raise GPIO 21 */
1010 tmp = INB(base + 0x0E);
1011 tmp |= 0x20;
1012 OUTB(tmp, base + 0x0E);
1013
1014 return 0;
1015}
1016
1017/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001018 * Below is the list of boards which need a special "board enable" code in
1019 * flashrom before their ROM chip can be accessed/written to.
1020 *
1021 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1022 * to the respective tables in print.c. Thanks!
1023 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001024 * We use 2 sets of IDs here, you're free to choose which is which. This
1025 * is to provide a very high degree of certainty when matching a board on
1026 * the basis of subsystem/card IDs. As not every vendor handles
1027 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001028 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001029 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
1030 * NULLed if they don't identify the board fully. But please take care to
1031 * provide an as complete set of pci ids as possible; autodetection is the
1032 * preferred behaviour and we would like to make sure that matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001033 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001034 * The coreboot ids are used two fold. When running with a coreboot firmware,
1035 * the ids uniquely matches the coreboot board identification string. When a
1036 * legacy bios is installed and when autodetection is not possible, these ids
1037 * can be used to identify the board through the -m command line argument.
1038 *
1039 * When a board is identified through its coreboot ids (in both cases), the
1040 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001041 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001042
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001043/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001044struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermannab60a432009-05-23 00:56:49 +00001045 /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */
Luc Verhaegen2f1d0a52009-07-06 22:58:46 +00001046 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35},
Uwe Hermannab60a432009-05-23 00:56:49 +00001047 {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001048 {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e},
Uwe Hermannef016f52009-07-04 15:10:41 +00001049 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2},
Uwe Hermanna02d6662009-08-20 18:45:18 +00001050 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001051 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x},
1052 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x},
Luc Verhaegen72272912009-09-01 21:22:23 +00001053 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x},
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001054 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x},
Uwe Hermannef016f52009-07-04 15:10:41 +00001055 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001056 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise},
Luc Verhaegen4eeb7132009-08-12 16:58:11 +00001057 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001058 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a},
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001059 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli},
Luc Verhaegen11793772009-07-21 01:44:45 +00001060 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable},
Uwe Hermann14b3e1e2009-10-06 20:23:29 +00001061 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise},
Uwe Hermann5ab88892009-06-21 20:50:22 +00001062 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001063 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2},
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001064 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001065 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
1066 {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash},
Luc Verhaegen11793772009-07-21 01:44:45 +00001067 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable},
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001068 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001069 {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash},
1070 {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash},
Uwe Hermann0495c942009-05-18 22:27:53 +00001071 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash},
1072 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash},
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001073 /* SB600 LPC, RD790 North. Neither are specific to the GA-MA790FX-DQ6. The coreboot ID is here to be able to trigger the board enable more easily. */
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001074 {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, "gigabyte", "ma790fx-dq6", "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash},
1075 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable},
1076 {0x1166, 0x0205, 0x1014, 0x0347, 0, 0, 0, 0, "ibm", "x3455", "IBM", "x3455", board_ibm_x3455},
1077 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi},
1078 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e},
1079 /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */
1080 {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m},
1081 {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m},
Michael Gold6d52e472009-06-19 13:00:24 +00001082 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu},
Uwe Hermann0b0cc162009-06-19 19:00:48 +00001083 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v},
Uwe Hermannd1129ac2009-05-28 15:07:42 +00001084 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e},
1085 {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001086 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise},
Uwe Hermann0b0cc162009-06-19 19:00:48 +00001087 {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
Uwe Hermann265e7552009-06-21 15:45:34 +00001088 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e},
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001089 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001090 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
1091 {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},
1092 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m},
Jon Harrison2eeff4e2009-06-19 13:53:59 +00001093 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001094 {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp},
1095 {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash},
Uwe Hermann5ab88892009-06-21 20:50:22 +00001096
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001097 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001098};
1099
Uwe Hermannffec5f32007-08-23 16:08:21 +00001100/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001101 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001102 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001103 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001104static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1105 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001106{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001107 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001108 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001109
Uwe Hermanna93045c2009-05-09 00:47:04 +00001110 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001111 if (vendor && (!board->lb_vendor
1112 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001113 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001114
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001115 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001116 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001117
Uwe Hermanna7e05482007-05-09 10:17:44 +00001118 if (!pci_dev_find(board->first_vendor, board->first_device))
1119 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001120
Uwe Hermanna7e05482007-05-09 10:17:44 +00001121 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001122 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001123 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001124
1125 if (vendor)
1126 return board;
1127
1128 if (partmatch) {
1129 /* a second entry has a matching part name */
1130 printf("AMBIGUOUS BOARD NAME: %s\n", part);
1131 printf("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001132 partmatch->lb_vendor, board->lb_vendor);
Peter Stuge6b53fed2008-01-27 16:21:21 +00001133 printf("Please use the full -m vendor:part syntax.\n");
1134 return NULL;
1135 }
1136 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001137 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001138
Peter Stuge6b53fed2008-01-27 16:21:21 +00001139 if (partmatch)
1140 return partmatch;
1141
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001142 if (!partvendor_from_cbtable) {
1143 /* Only warn if the mainboard type was not gathered from the
1144 * coreboot table. If it was, the coreboot implementor is
1145 * expected to fix flashrom, too.
1146 */
1147 printf("\nUnknown vendor:board from -m option: %s:%s\n\n",
1148 vendor, part);
1149 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001150 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001151}
1152
Uwe Hermannffec5f32007-08-23 16:08:21 +00001153/**
1154 * Match boards on PCI IDs and subsystem IDs.
1155 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001156 */
1157static struct board_pciid_enable *board_match_pci_card_ids(void)
1158{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001159 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001160
Uwe Hermanna93045c2009-05-09 00:47:04 +00001161 for (; board->vendor_name; board++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +00001162 if (!board->first_card_vendor || !board->first_card_device)
1163 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001164
Uwe Hermanna7e05482007-05-09 10:17:44 +00001165 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001166 board->first_card_vendor,
1167 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001168 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001169
Uwe Hermanna7e05482007-05-09 10:17:44 +00001170 if (board->second_vendor) {
1171 if (board->second_card_vendor) {
1172 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001173 board->second_device,
1174 board->second_card_vendor,
1175 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001176 continue;
1177 } else {
1178 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001179 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001180 continue;
1181 }
1182 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001183
Uwe Hermanna7e05482007-05-09 10:17:44 +00001184 return board;
1185 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001186
Uwe Hermanna7e05482007-05-09 10:17:44 +00001187 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001188}
1189
Uwe Hermann372eeb52007-12-04 21:49:06 +00001190int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001191{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001192 struct board_pciid_enable *board = NULL;
1193 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001194
Peter Stuge6b53fed2008-01-27 16:21:21 +00001195 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001196 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001197
Uwe Hermanna7e05482007-05-09 10:17:44 +00001198 if (!board)
1199 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001200
Uwe Hermanna7e05482007-05-09 10:17:44 +00001201 if (board) {
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001202 printf("Disabling flash write protection for board \"%s %s\"... ",
Uwe Hermanna93045c2009-05-09 00:47:04 +00001203 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001204
Uwe Hermanna93045c2009-05-09 00:47:04 +00001205 ret = board->enable(board->vendor_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001206 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001207 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001208 else
1209 printf("OK.\n");
1210 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001211
Uwe Hermanna7e05482007-05-09 10:17:44 +00001212 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001213}