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Nico Huber83693c82016-10-08 22:17:55 +02001--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +02006-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +02008--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
Nico Huber75a707f2018-06-18 16:28:33 +020015with HW.GFX.GMA.Config;
Nico Huber9e96a452019-09-22 20:25:17 +020016with HW.GFX.GMA.Config_Helpers;
Nico Huber83693c82016-10-08 22:17:55 +020017with HW.GFX.GMA.Registers;
18
Nico Huber47ff0692016-11-04 14:29:39 +010019
Nico Huber83693c82016-10-08 22:17:55 +020020private package HW.GFX.GMA.Pipe_Setup
21is
22
Nico Huber83693c82016-10-08 22:17:55 +020023 procedure On
Nico Huberf3e23662016-12-05 21:33:03 +010024 (Pipe : Pipe_Index;
Nico Huber4d592b42026-06-23 12:21:37 +000025 Pipe_Cfg : Pipe_Config;
26 Port_Cfg : Port_Config)
Nico Huber47ff0692016-11-04 14:29:39 +010027 with
Nico Huber4d592b42026-06-23 12:21:37 +000028 Pre => Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Port_Cfg.Mode);
Nico Huber83693c82016-10-08 22:17:55 +020029
Nico Huber7ad2d652016-12-07 15:19:32 +010030 procedure Off (Pipe : Pipe_Index);
Nico Huber83693c82016-10-08 22:17:55 +020031
Nico Huber33912aa2016-12-06 20:36:23 +010032 procedure Legacy_VGA_Off;
33
Nico Huber83693c82016-10-08 22:17:55 +020034 procedure All_Off;
35
Nico Huber4d592b42026-06-23 12:21:37 +000036 -- TODO: Passing `Pipe_Cfg` and `Mode` seems redundant. However,
37 -- the `Pipe_Cfg.Mode` is what the user requested and we
38 -- may have altered that in `Mode`. This should be refac-
39 -- tored to always have a single, synchronized `Mode`.
Nico Huberf7f537e2018-01-02 14:15:43 +010040 procedure Setup_FB
41 (Pipe : Pipe_Index;
Nico Huber4d592b42026-06-23 12:21:37 +000042 Pipe_Cfg : Pipe_Config;
43 Mode : Mode_Type)
Nico Huberf7f537e2018-01-02 14:15:43 +010044 with
Nico Huber4d592b42026-06-23 12:21:37 +000045 Pre => Config_Helpers.Valid_FB (Pipe_Cfg.Framebuffer, Mode);
Nico Huber83693c82016-10-08 22:17:55 +020046
Nico Huber4dc4c612018-01-10 15:55:09 +010047 procedure Update_Cursor
48 (Pipe : Pipe_Index;
49 FB : Framebuffer_Type;
50 Cursor : Cursor_Type);
51 procedure Place_Cursor
52 (Pipe : Pipe_Index;
53 FB : Framebuffer_Type;
54 Cursor : Cursor_Type);
55
Nico Huber9a4c4c32019-09-16 22:05:11 +020056 type Scaler_Reservation is private;
57 Null_Scaler_Reservation : constant Scaler_Reservation;
58 procedure Reserve_Scaler
59 (Success : out Boolean;
60 Reservation : in out Scaler_Reservation;
61 Pipe : in Pipe_Index);
Nico Huberf361ec82018-06-02 18:01:45 +020062
Nico Huber83693c82016-10-08 22:17:55 +020063private
64
Nico Huber9a4c4c32019-09-16 22:05:11 +020065 type Scaler_Reservation is record
66 Reserved : Boolean;
67 Pipe : Pipe_Index;
68 end record;
69 Null_Scaler_Reservation : constant Scaler_Reservation :=
70 (Reserved => False, Pipe => Pipe_Index'First);
71
Nico Huber83693c82016-10-08 22:17:55 +020072 subtype WM_Levels is Natural range 0 .. 7;
73 type PLANE_WM_Type is array (WM_Levels) of Registers.Registers_Index;
74
75 type Controller_Type is
76 record
Nico Huberf3e23662016-12-05 21:33:03 +010077 Pipe : Pipe_Index;
Nico Huber83693c82016-10-08 22:17:55 +020078 PIPESRC : Registers.Registers_Index;
79 PIPEMISC : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +010080 PF_CTRL : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020081 PF_WIN_POS : Registers.Registers_Index;
82 PF_WIN_SZ : Registers.Registers_Index;
83 DSPCNTR : Registers.Registers_Index;
84 DSPLINOFF : Registers.Registers_Index;
85 DSPSTRIDE : Registers.Registers_Index;
86 DSPSURF : Registers.Registers_Index;
87 DSPTILEOFF : Registers.Registers_Index;
Arthur Heymans960e2392026-03-03 19:45:24 +010088 DSPSIZE : Registers.Registers_Index;
89 DSPPOS : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020090 -- Skylake registers (partially aliased)
91 PLANE_CTL : Registers.Registers_Index;
92 PLANE_OFFSET : Registers.Registers_Index;
93 PLANE_POS : Registers.Registers_Index;
94 PLANE_SIZE : Registers.Registers_Index;
95 PLANE_STRIDE : Registers.Registers_Index;
96 PLANE_SURF : Registers.Registers_Index;
97 PS_CTRL_1 : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +010098 PS_WIN_POS_1 : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +020099 PS_WIN_SZ_1 : Registers.Registers_Index;
Nico Huber4916e342016-11-04 14:37:53 +0100100 PS_CTRL_2 : Registers.Registers_Invalid_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200101 PS_WIN_SZ_2 : Registers.Registers_Invalid_Index;
102 WM_LINETIME : Registers.Registers_Index;
103 PLANE_BUF_CFG : Registers.Registers_Index;
Nico Huber07aab5a2020-10-01 15:06:53 +0200104 PLANE_COLOR_CTL : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200105 PLANE_WM : PLANE_WM_Type;
Nico Huber07aab5a2020-10-01 15:06:53 +0200106 PLANE_2_CTL : Registers.Registers_Index;
107 PLANE_2_OFFSET : Registers.Registers_Index;
108 PLANE_2_POS : Registers.Registers_Index;
109 PLANE_2_SIZE : Registers.Registers_Index;
110 PLANE_2_STRIDE : Registers.Registers_Index;
111 PLANE_2_SURF : Registers.Registers_Index;
112 PLANE_2_BUF_CFG : Registers.Registers_Index;
113 PLANE_2_COLOR_CTL : Registers.Registers_Index;
114 PLANE_2_WM : PLANE_WM_Type;
Nico Huber4dc4c612018-01-10 15:55:09 +0100115 CUR_BUF_CFG : Registers.Registers_Index;
116 CUR_WM : PLANE_WM_Type;
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600117 MBUS_DBOX_CTL : Registers.Registers_Index;
118 PIPE_CHICKEN : Registers.Registers_Index;
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600119 PLANE_AUX_DIST : Registers.Registers_Index;
Nico Huber83693c82016-10-08 22:17:55 +0200120 end record;
121
Nico Huberf3e23662016-12-05 21:33:03 +0100122 type Controller_Array is array (Pipe_Index) of Controller_Type;
123
Arthur Heymans960e2392026-03-03 19:45:24 +0100124 -- On Gen3 (i945), FBC only works with Plane A, but LVDS and the
125 -- panel fitter are hooked to Pipe B. Hence we want Plane A feeding
126 -- Pipe B, which means swapping the plane register assignments:
127 -- Primary (Pipe A) gets Plane B, Secondary (Pipe B) gets Plane A.
128
Nico Huberf3e23662016-12-05 21:33:03 +0100129 Controllers : constant Controller_Array :=
130 (Primary => Controller_Type'
131 (Pipe => Primary,
Nico Huber83693c82016-10-08 22:17:55 +0200132 PIPESRC => Registers.PIPEASRC,
133 PIPEMISC => Registers.PIPEAMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100134 PF_CTRL => Registers.PFA_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200135 PF_WIN_POS => Registers.PFA_WIN_POS,
136 PF_WIN_SZ => Registers.PFA_WIN_SZ,
Arthur Heymans960e2392026-03-03 19:45:24 +0100137 DSPCNTR =>
138 (if Config.Planes_Pipes_Swapped
139 then Registers.DSPBCNTR else Registers.DSPACNTR),
140 DSPLINOFF =>
141 (if Config.Planes_Pipes_Swapped
142 then Registers.DSPBLINOFF else Registers.DSPALINOFF),
143 DSPSTRIDE =>
144 (if Config.Planes_Pipes_Swapped
145 then Registers.DSPBSTRIDE else Registers.DSPASTRIDE),
146 DSPSURF =>
147 (if Config.Planes_Pipes_Swapped
148 then Registers.DSPBSURF else Registers.DSPASURF),
149 DSPTILEOFF =>
150 (if Config.Planes_Pipes_Swapped
151 then Registers.DSPBTILEOFF else Registers.DSPATILEOFF),
152 DSPSIZE =>
153 (if Config.Planes_Pipes_Swapped
154 then Registers.PLANE_SIZE_1_B else Registers.PLANE_SIZE_1_A),
155 DSPPOS =>
156 (if Config.Planes_Pipes_Swapped
157 then Registers.PLANE_POS_1_B else Registers.PLANE_POS_1_A),
Nico Huber83693c82016-10-08 22:17:55 +0200158 PLANE_CTL => Registers.DSPACNTR,
159 PLANE_OFFSET => Registers.DSPATILEOFF,
160 PLANE_POS => Registers.PLANE_POS_1_A,
161 PLANE_SIZE => Registers.PLANE_SIZE_1_A,
162 PLANE_STRIDE => Registers.DSPASTRIDE,
163 PLANE_SURF => Registers.DSPASURF,
164 PS_CTRL_1 => Registers.PS_CTRL_1_A,
Nico Huber4916e342016-11-04 14:37:53 +0100165 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200166 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_A,
Nico Huber4916e342016-11-04 14:37:53 +0100167 PS_CTRL_2 => Registers.PS_CTRL_2_A,
Nico Huber83693c82016-10-08 22:17:55 +0200168 PS_WIN_SZ_2 => Registers.PS_WIN_SZ_2_A,
169 WM_LINETIME => Registers.WM_LINETIME_A,
170 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_A,
Nico Huber07aab5a2020-10-01 15:06:53 +0200171 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200172 PLANE_WM => PLANE_WM_Type'(
173 Registers.PLANE_WM_1_A_0,
174 Registers.PLANE_WM_1_A_1,
175 Registers.PLANE_WM_1_A_2,
176 Registers.PLANE_WM_1_A_3,
177 Registers.PLANE_WM_1_A_4,
178 Registers.PLANE_WM_1_A_5,
179 Registers.PLANE_WM_1_A_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100180 Registers.PLANE_WM_1_A_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200181 PLANE_2_CTL => Registers.PLANE_CTL_2_A,
182 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_A,
183 PLANE_2_POS => Registers.PLANE_POS_2_A,
184 PLANE_2_SIZE => Registers.PLANE_SIZE_2_A,
185 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_A,
186 PLANE_2_SURF => Registers.PLANE_SURF_2_A,
187 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_A,
188 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_A,
189 PLANE_2_WM => PLANE_WM_Type'(
190 Registers.PLANE_WM_2_A_0,
191 Registers.PLANE_WM_2_A_1,
192 Registers.PLANE_WM_2_A_2,
193 Registers.PLANE_WM_2_A_3,
194 Registers.PLANE_WM_2_A_4,
195 Registers.PLANE_WM_2_A_5,
196 Registers.PLANE_WM_2_A_6,
197 Registers.PLANE_WM_2_A_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100198 CUR_BUF_CFG => Registers.CUR_BUF_CFG_A,
199 CUR_WM => PLANE_WM_Type'(
200 Registers.CUR_WM_A_0,
201 Registers.CUR_WM_A_1,
202 Registers.CUR_WM_A_2,
203 Registers.CUR_WM_A_3,
204 Registers.CUR_WM_A_4,
205 Registers.CUR_WM_A_5,
206 Registers.CUR_WM_A_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600207 Registers.CUR_WM_A_7),
208 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_A,
209 PIPE_CHICKEN => Registers.PIPEA_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600210 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_A),
Nico Huberf3e23662016-12-05 21:33:03 +0100211 Secondary => Controller_Type'
212 (Pipe => Secondary,
Nico Huber83693c82016-10-08 22:17:55 +0200213 PIPESRC => Registers.PIPEBSRC,
214 PIPEMISC => Registers.PIPEBMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100215 PF_CTRL => Registers.PFB_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200216 PF_WIN_POS => Registers.PFB_WIN_POS,
217 PF_WIN_SZ => Registers.PFB_WIN_SZ,
Arthur Heymans960e2392026-03-03 19:45:24 +0100218 DSPCNTR =>
219 (if Config.Planes_Pipes_Swapped
220 then Registers.DSPACNTR else Registers.DSPBCNTR),
221 DSPLINOFF =>
222 (if Config.Planes_Pipes_Swapped
223 then Registers.DSPALINOFF else Registers.DSPBLINOFF),
224 DSPSTRIDE =>
225 (if Config.Planes_Pipes_Swapped
226 then Registers.DSPASTRIDE else Registers.DSPBSTRIDE),
227 DSPSURF =>
228 (if Config.Planes_Pipes_Swapped
229 then Registers.DSPASURF else Registers.DSPBSURF),
230 DSPTILEOFF =>
231 (if Config.Planes_Pipes_Swapped
232 then Registers.DSPATILEOFF else Registers.DSPBTILEOFF),
233 DSPSIZE =>
234 (if Config.Planes_Pipes_Swapped
235 then Registers.PLANE_SIZE_1_A else Registers.PLANE_SIZE_1_B),
236 DSPPOS =>
237 (if Config.Planes_Pipes_Swapped
238 then Registers.PLANE_POS_1_A else Registers.PLANE_POS_1_B),
Nico Huber83693c82016-10-08 22:17:55 +0200239 PLANE_CTL => Registers.DSPBCNTR,
240 PLANE_OFFSET => Registers.DSPBTILEOFF,
241 PLANE_POS => Registers.PLANE_POS_1_B,
242 PLANE_SIZE => Registers.PLANE_SIZE_1_B,
243 PLANE_STRIDE => Registers.DSPBSTRIDE,
244 PLANE_SURF => Registers.DSPBSURF,
245 PS_CTRL_1 => Registers.PS_CTRL_1_B,
Nico Huber4916e342016-11-04 14:37:53 +0100246 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200247 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_B,
Nico Huber4916e342016-11-04 14:37:53 +0100248 PS_CTRL_2 => Registers.PS_CTRL_2_B,
Nico Huber83693c82016-10-08 22:17:55 +0200249 PS_WIN_SZ_2 => Registers.PS_WIN_SZ_2_B,
250 WM_LINETIME => Registers.WM_LINETIME_B,
251 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_B,
Nico Huber07aab5a2020-10-01 15:06:53 +0200252 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200253 PLANE_WM => PLANE_WM_Type'(
254 Registers.PLANE_WM_1_B_0,
255 Registers.PLANE_WM_1_B_1,
256 Registers.PLANE_WM_1_B_2,
257 Registers.PLANE_WM_1_B_3,
258 Registers.PLANE_WM_1_B_4,
259 Registers.PLANE_WM_1_B_5,
260 Registers.PLANE_WM_1_B_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100261 Registers.PLANE_WM_1_B_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200262 PLANE_2_CTL => Registers.PLANE_CTL_2_B,
263 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_B,
264 PLANE_2_POS => Registers.PLANE_POS_2_B,
265 PLANE_2_SIZE => Registers.PLANE_SIZE_2_B,
266 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_B,
267 PLANE_2_SURF => Registers.PLANE_SURF_2_B,
268 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_B,
269 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_B,
270 PLANE_2_WM => PLANE_WM_Type'(
271 Registers.PLANE_WM_2_B_0,
272 Registers.PLANE_WM_2_B_1,
273 Registers.PLANE_WM_2_B_2,
274 Registers.PLANE_WM_2_B_3,
275 Registers.PLANE_WM_2_B_4,
276 Registers.PLANE_WM_2_B_5,
277 Registers.PLANE_WM_2_B_6,
278 Registers.PLANE_WM_2_B_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100279 CUR_BUF_CFG => Registers.CUR_BUF_CFG_B,
280 CUR_WM => PLANE_WM_Type'(
281 Registers.CUR_WM_B_0,
282 Registers.CUR_WM_B_1,
283 Registers.CUR_WM_B_2,
284 Registers.CUR_WM_B_3,
285 Registers.CUR_WM_B_4,
286 Registers.CUR_WM_B_5,
287 Registers.CUR_WM_B_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600288 Registers.CUR_WM_B_7),
289 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_B,
290 PIPE_CHICKEN => Registers.PIPEB_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600291 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_B),
Nico Huberf3e23662016-12-05 21:33:03 +0100292 Tertiary => Controller_Type'
293 (Pipe => Tertiary,
Nico Huber83693c82016-10-08 22:17:55 +0200294 PIPESRC => Registers.PIPECSRC,
295 PIPEMISC => Registers.PIPECMISC,
Nico Huber4916e342016-11-04 14:37:53 +0100296 PF_CTRL => Registers.PFC_CTL_1,
Nico Huber83693c82016-10-08 22:17:55 +0200297 PF_WIN_POS => Registers.PFC_WIN_POS,
298 PF_WIN_SZ => Registers.PFC_WIN_SZ,
299 DSPCNTR => Registers.DSPCCNTR,
300 DSPLINOFF => Registers.DSPCLINOFF,
301 DSPSTRIDE => Registers.DSPCSTRIDE,
302 DSPSURF => Registers.DSPCSURF,
303 DSPTILEOFF => Registers.DSPCTILEOFF,
Arthur Heymans960e2392026-03-03 19:45:24 +0100304 DSPSIZE => Registers.PLANE_SIZE_1_C,
305 DSPPOS => Registers.PLANE_POS_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200306 PLANE_CTL => Registers.DSPCCNTR,
307 PLANE_OFFSET => Registers.DSPCTILEOFF,
308 PLANE_POS => Registers.PLANE_POS_1_C,
309 PLANE_SIZE => Registers.PLANE_SIZE_1_C,
310 PLANE_STRIDE => Registers.DSPCSTRIDE,
311 PLANE_SURF => Registers.DSPCSURF,
312 PS_CTRL_1 => Registers.PS_CTRL_1_C,
Nico Huber4916e342016-11-04 14:37:53 +0100313 PS_WIN_POS_1 => Registers.PS_WIN_POS_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200314 PS_WIN_SZ_1 => Registers.PS_WIN_SZ_1_C,
Nico Huber4916e342016-11-04 14:37:53 +0100315 PS_CTRL_2 => Registers.Invalid_Register,
Nico Huber83693c82016-10-08 22:17:55 +0200316 PS_WIN_SZ_2 => Registers.Invalid_Register,
317 WM_LINETIME => Registers.WM_LINETIME_C,
318 PLANE_BUF_CFG => Registers.PLANE_BUF_CFG_1_C,
Nico Huber07aab5a2020-10-01 15:06:53 +0200319 PLANE_COLOR_CTL => Registers.PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200320 PLANE_WM => PLANE_WM_Type'(
321 Registers.PLANE_WM_1_C_0,
322 Registers.PLANE_WM_1_C_1,
323 Registers.PLANE_WM_1_C_2,
324 Registers.PLANE_WM_1_C_3,
325 Registers.PLANE_WM_1_C_4,
326 Registers.PLANE_WM_1_C_5,
327 Registers.PLANE_WM_1_C_6,
Nico Huber4dc4c612018-01-10 15:55:09 +0100328 Registers.PLANE_WM_1_C_7),
Nico Huber07aab5a2020-10-01 15:06:53 +0200329 PLANE_2_CTL => Registers.PLANE_CTL_2_C,
330 PLANE_2_OFFSET => Registers.PLANE_OFFSET_2_C,
331 PLANE_2_POS => Registers.PLANE_POS_2_C,
332 PLANE_2_SIZE => Registers.PLANE_SIZE_2_C,
333 PLANE_2_STRIDE => Registers.PLANE_STRIDE_2_C,
334 PLANE_2_SURF => Registers.PLANE_SURF_2_C,
335 PLANE_2_BUF_CFG => Registers.PLANE_BUF_CFG_2_C,
336 PLANE_2_COLOR_CTL => Registers.PLANE_COLOR_CTL_2_C,
337 PLANE_2_WM => PLANE_WM_Type'(
338 Registers.PLANE_WM_2_C_0,
339 Registers.PLANE_WM_2_C_1,
340 Registers.PLANE_WM_2_C_2,
341 Registers.PLANE_WM_2_C_3,
342 Registers.PLANE_WM_2_C_4,
343 Registers.PLANE_WM_2_C_5,
344 Registers.PLANE_WM_2_C_6,
345 Registers.PLANE_WM_2_C_7),
Nico Huber4dc4c612018-01-10 15:55:09 +0100346 CUR_BUF_CFG => Registers.CUR_BUF_CFG_C,
347 CUR_WM => PLANE_WM_Type'(
348 Registers.CUR_WM_C_0,
349 Registers.CUR_WM_C_1,
350 Registers.CUR_WM_C_2,
351 Registers.CUR_WM_C_3,
352 Registers.CUR_WM_C_4,
353 Registers.CUR_WM_C_5,
354 Registers.CUR_WM_C_6,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600355 Registers.CUR_WM_C_7),
356 MBUS_DBOX_CTL => Registers.PIPE_MBUS_DBOX_CTL_C,
357 PIPE_CHICKEN => Registers.PIPEC_CHICKEN,
Tim Wawrzynczak0da761a2022-09-09 10:42:36 -0600358 PLANE_AUX_DIST => Registers.PLANE_AUX_DIST_1_C));
Nico Huber83693c82016-10-08 22:17:55 +0200359
Nico Huber75a707f2018-06-18 16:28:33 +0200360 type Cursor_Regs is record
361 CTL : Registers.Registers_Index;
362 BASE : Registers.Registers_Index;
363 POS : Registers.Registers_Index;
364 FBC_CTL : Registers.Registers_Invalid_Index;
365 end record;
366
367 function Cursors (Pipe : Pipe_Index) return Cursor_Regs is
368 (if not Config.Has_Ivybridge_Cursors then
369 (if Pipe = Primary then
370 (CTL => Registers.CURACNTR,
371 BASE => Registers.CURABASE,
372 POS => Registers.CURAPOS,
373 FBC_CTL => Registers.Invalid_Register)
374 else
375 (CTL => Registers.CURBCNTR,
376 BASE => Registers.CURBBASE,
377 POS => Registers.CURBPOS,
378 FBC_CTL => Registers.Invalid_Register))
379 else
380 (if Pipe = Primary then
381 (CTL => Registers.CUR_CTL_A,
382 BASE => Registers.CUR_BASE_A,
383 POS => Registers.CUR_POS_A,
384 FBC_CTL => Registers.CUR_FBC_CTL_A)
385 elsif Pipe = Secondary then
386 (CTL => Registers.CUR_CTL_B,
387 BASE => Registers.CUR_BASE_B,
388 POS => Registers.CUR_POS_B,
389 FBC_CTL => Registers.CUR_FBC_CTL_B)
390 else
391 (CTL => Registers.CUR_CTL_C,
392 BASE => Registers.CUR_BASE_C,
393 POS => Registers.CUR_POS_C,
394 FBC_CTL => Registers.CUR_FBC_CTL_C)));
395
Nico Huber83693c82016-10-08 22:17:55 +0200396end HW.GFX.GMA.Pipe_Setup;