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Uwe Hermannb4dcb712009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermannb4dcb712009-05-13 11:36:06 +000015 */
16
17#include <stdlib.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000018#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000019#include "programmer.h"
Thomas Heijligena0655202021-12-14 16:36:05 +010020#include "hwaccess_x86_io.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010021#include "platform/pci.h"
Uwe Hermannb4dcb712009-05-13 11:36:06 +000022
23#define BIOS_ROM_ADDR 0x04
24#define BIOS_ROM_DATA 0x08
25#define INT_STATUS 0x0e
Uwe Hermann8403ccb2009-05-16 21:39:19 +000026#define INTERNAL_CONFIG 0x00
Uwe Hermannb4dcb712009-05-13 11:36:06 +000027#define SELECT_REG_WINDOW 0x800
28
Uwe Hermannb4dcb712009-05-13 11:36:06 +000029#define PCI_VENDOR_ID_3COM 0x10b7
30
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000031static uint32_t io_base_addr = 0;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000032static uint32_t internal_conf;
33static uint16_t id;
Uwe Hermann8403ccb2009-05-16 21:39:19 +000034
Thomas Heijligencc853d82021-05-04 15:32:17 +020035static const struct dev_entry nics_3com[] = {
Uwe Hermannb4dcb712009-05-13 11:36:06 +000036 /* 3C90xB */
Michael Karcher84486392010-02-24 00:04:40 +000037 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
38 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
39 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
40 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
Adrien Destuguesd42f1f62021-08-10 11:48:18 +020041 {0x10b7, 0x9006, OK, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
Michael Karcher84486392010-02-24 00:04:40 +000042 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
43 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
44 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000045
46 /* 3C905C */
Michael Karcher84486392010-02-24 00:04:40 +000047 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000048
49 /* 3C980C */
Michael Karcher84486392010-02-24 00:04:40 +000050 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000051
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000052 {0},
Uwe Hermannb4dcb712009-05-13 11:36:06 +000053};
54
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000055static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
56 chipaddr addr);
57static uint8_t nic3com_chip_readb(const struct flashctx *flash,
58 const chipaddr addr);
Anastasia Klimchukd66dded2021-08-27 15:42:46 +100059static int nic3com_shutdown(void *data);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000060static const struct par_master par_master_nic3com = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020061 .chip_readb = nic3com_chip_readb,
62 .chip_readw = fallback_chip_readw,
63 .chip_readl = fallback_chip_readl,
64 .chip_readn = fallback_chip_readn,
65 .chip_writeb = nic3com_chip_writeb,
66 .chip_writew = fallback_chip_writew,
67 .chip_writel = fallback_chip_writel,
68 .chip_writen = fallback_chip_writen,
Anastasia Klimchukd66dded2021-08-27 15:42:46 +100069 .shutdown = nic3com_shutdown,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000070};
71
David Hendricks8bb20212011-06-14 01:35:36 +000072static int nic3com_shutdown(void *data)
73{
74 /* 3COM 3C90xB cards need a special fixup. */
75 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
76 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
77 /* Select register window 3 and restore the receiver status. */
78 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
79 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
80 }
81
David Hendricks8bb20212011-06-14 01:35:36 +000082 return 0;
83}
84
Thomas Heijligencc853d82021-05-04 15:32:17 +020085static int nic3com_init(void)
Uwe Hermannb4dcb712009-05-13 11:36:06 +000086{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000087 struct pci_dev *dev = NULL;
88
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000089 if (rget_io_perms())
90 return 1;
Uwe Hermannb4dcb712009-05-13 11:36:06 +000091
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000092 dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0);
93 if (!dev)
94 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000095
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000096 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000097 if (!io_base_addr)
98 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000099
100 id = dev->device_id;
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000101
102 /* 3COM 3C90xB cards need a special fixup. */
103 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +0000104 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000105 /* Select register window 3 and save the receiver status. */
106 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
107 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
108
109 /* Set receiver type to MII for full BIOS ROM access. */
110 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
111 }
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000112
113 /*
114 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
115 * cards form a 'register window' into one of multiple (usually 8)
116 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
117 */
118 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
119
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000120 max_rom_decode.parallel = 128 * 1024;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000121
Anastasia Klimchukd66dded2021-08-27 15:42:46 +1000122 return register_par_master(&par_master_nic3com, BUS_PARALLEL, NULL);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000123}
124
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000125static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
126 chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000127{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000128 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000129 OUTB(val, io_base_addr + BIOS_ROM_DATA);
130}
131
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000132static uint8_t nic3com_chip_readb(const struct flashctx *flash,
133 const chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000134{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000135 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannc7e8a0c2009-05-19 14:14:21 +0000136 return INB(io_base_addr + BIOS_ROM_DATA);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000137}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000138
Thomas Heijligencc853d82021-05-04 15:32:17 +0200139const struct programmer_entry programmer_nic3com = {
140 .name = "nic3com",
141 .type = PCI,
142 .devs.dev = nics_3com,
143 .init = nic3com_init,
144 .map_flash_region = fallback_map,
145 .unmap_flash_region = fallback_unmap,
146 .delay = internal_delay,
147};