Handle the following architectures in generic flashrom code
- x86/x86_64 (little endian)
- PowerPC (big endian)
- MIPS (big+little endian)
No changes to programmer specific code. This means any drivers with MMIO
access will _not_ suddenly start working on big endian systems, but with
this patch everything is in place to fix them.
Compilation should work on all architectures listed above for all
drivers except nic3com and nicrealtek which require PCI Port IO which is
x86-only for now.
To compile without nic3com and nicrealtek, run
make distclean
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no
Thanks to Misha Manulis for testing early versions of this patch on
PowerPC (big endian) with the satasii programmer.
Thanks to Segher Boessenkool for design review and for helping out with
compiler tricks and pointing out that we need eieio on PowerPC.
Thanks to Vladimir Serbinenko for compile testing on MIPS (little
endian) and PowerPC (big endian) and for runtime testing on MIPS (little
endian).
Thanks to David Daney for compile testing on MIPS (big endian).
Thanks to Uwe Hermann for compile and runtime testing on x86_64.
DO NOT RUN flashrom ON NON-X86 AFTER APPLYING THIS PATCH!
This patch only provides the infrastructure, but does not convert any
drivers, so flashrom will compile, but it won't do the right thing on
non-x86 platforms.
Corresponding to flashrom svn r1013.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Misha Manulis <misha@manulis.com>
Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
diff --git a/nic3com.c b/nic3com.c
index d3dcce5..8064b57 100644
--- a/nic3com.c
+++ b/nic3com.c
@@ -18,6 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#if defined(__i386__) || defined(__x86_64__)
+
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
@@ -112,3 +114,7 @@
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
return INB(io_base_addr + BIOS_ROM_DATA);
}
+
+#else
+#error PCI port I/O access is not supported on this architecture yet.
+#endif