programmer_table: move each entry to the associated programmer source
Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71373
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/nic3com.c b/nic3com.c
index b7b967a..94442df 100644
--- a/nic3com.c
+++ b/nic3com.c
@@ -33,7 +33,7 @@
static uint32_t internal_conf;
static uint16_t id;
-const struct dev_entry nics_3com[] = {
+static const struct dev_entry nics_3com[] = {
/* 3C90xB */
{0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
{0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
@@ -81,7 +81,7 @@
return 0;
}
-int nic3com_init(void)
+static int nic3com_init(void)
{
struct pci_dev *dev = NULL;
@@ -139,6 +139,16 @@
return INB(io_base_addr + BIOS_ROM_DATA);
}
+const struct programmer_entry programmer_nic3com = {
+ .name = "nic3com",
+ .type = PCI,
+ .devs.dev = nics_3com,
+ .init = nic3com_init,
+ .map_flash_region = fallback_map,
+ .unmap_flash_region = fallback_unmap,
+ .delay = internal_delay,
+};
+
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif