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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdio.h>
29#include <pci/pci.h>
30#include <stdlib.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000031#include <sys/types.h>
32#include <sys/stat.h>
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +000033#include <sys/mman.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000034#include <fcntl.h>
35#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000036#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000038/**
39 * flashrom defaults to LPC flash devices. If a known SPI controller is found
40 * and the SPI strappings are set, this will be overwritten by the probing code.
41 *
42 * Eventually, this will become an array when multiple flash support works.
43 */
44
45flashbus_t flashbus = BUS_TYPE_LPC;
46void *spibar = NULL;
47
48
Uwe Hermann372eeb52007-12-04 21:49:06 +000049static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000050{
51 uint8_t tmp;
52
Uwe Hermann372eeb52007-12-04 21:49:06 +000053 /*
54 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
55 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
56 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000057 tmp = pci_read_byte(dev, 0x47);
58 tmp |= 0x46;
59 pci_write_byte(dev, 0x47, tmp);
60
61 return 0;
62}
63
Uwe Hermann372eeb52007-12-04 21:49:06 +000064static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000065{
Uwe Hermann372eeb52007-12-04 21:49:06 +000066 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000067
Uwe Hermann372eeb52007-12-04 21:49:06 +000068 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000069 b = pci_read_byte(dev, 0x40);
70 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000071
72 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000073 b = pci_read_byte(dev, 0x45);
74 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000075
Uwe Hermann372eeb52007-12-04 21:49:06 +000076 /* The same thing on SiS 950 Super I/O side... */
77
78 /* First probe for Super I/O on config port 0x2e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000079 OUTB(0x87, 0x2e);
80 OUTB(0x01, 0x2e);
81 OUTB(0x55, 0x2e);
82 OUTB(0x55, 0x2e);
Ollie Lhocbbf1252004-03-17 22:22:08 +000083
Andriy Gapon65c1b862008-05-22 13:22:45 +000084 if (INB(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000085 /* If that failed, try config port 0x4e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000086 OUTB(0x87, 0x4e);
87 OUTB(0x01, 0x4e);
88 OUTB(0x55, 0x4e);
89 OUTB(0xaa, 0x4e);
90 if (INB(0x4f) != 0x87) {
Ollie Lhocbbf1252004-03-17 22:22:08 +000091 printf("Can not access SiS 950\n");
92 return -1;
93 }
Andriy Gapon65c1b862008-05-22 13:22:45 +000094 OUTB(0x24, 0x4e);
95 b = INB(0x4f) | 0xfc;
96 OUTB(0x24, 0x4e);
97 OUTB(b, 0x4f);
98 OUTB(0x02, 0x4e);
99 OUTB(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000100 }
101
Andriy Gapon65c1b862008-05-22 13:22:45 +0000102 OUTB(0x24, 0x2e);
103 printf("2f is %#x\n", INB(0x2f));
104 b = INB(0x2f) | 0xfc;
105 OUTB(0x24, 0x2e);
106 OUTB(b, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000107
Andriy Gapon65c1b862008-05-22 13:22:45 +0000108 OUTB(0x02, 0x2e);
109 OUTB(0x02, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000110
111 return 0;
112}
113
Uwe Hermann987942d2006-11-07 11:16:21 +0000114/* Datasheet:
115 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
116 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
117 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
118 * - Order Number: 290562-001
119 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000120static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000121{
122 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000123 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000124
125 old = pci_read_word(dev, xbcs);
126
127 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000128 * FFF00000-FFF7FFFF are forwarded to ISA).
129 * Set bit 7: Extended BIOS Enable (PCI master accesses to
130 * FFF80000-FFFDFFFF are forwarded to ISA).
131 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
132 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
133 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
134 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
135 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
136 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
137 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000138 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000139
140 if (new == old)
141 return 0;
142
143 pci_write_word(dev, xbcs, new);
144
145 if (pci_read_word(dev, xbcs) != new) {
146 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
147 return -1;
148 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000149
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000150 return 0;
151}
152
Uwe Hermann372eeb52007-12-04 21:49:06 +0000153/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000154 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
155 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000156 */
157static int enable_flash_ich(struct pci_dev *dev, const char *name,
158 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000159{
Ollie Lho184a4042005-11-26 21:55:36 +0000160 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000161
Uwe Hermann372eeb52007-12-04 21:49:06 +0000162 /*
163 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000164 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000165 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000166 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000167
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000168 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000169 (old & (1 << 1)) ? "en" : "dis");
170 printf_debug("BIOS Write Enable: %sabled, ",
171 (old & (1 << 0)) ? "en" : "dis");
172 printf_debug("BIOS_CNTL is 0x%x\n", old);
173
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000174 new = old | 1;
175
176 if (new == old)
177 return 0;
178
Stefan Reinauer86de2832006-03-31 11:26:55 +0000179 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000180
Stefan Reinauer86de2832006-03-31 11:26:55 +0000181 if (pci_read_byte(dev, bios_cntl) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000182 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000183 return -1;
184 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000185
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000186 return 0;
187}
188
Uwe Hermann372eeb52007-12-04 21:49:06 +0000189static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000190{
Stefan Reinauereb366472006-09-06 15:48:48 +0000191 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000192}
193
Uwe Hermann372eeb52007-12-04 21:49:06 +0000194static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000195{
Stefan Reinauereb366472006-09-06 15:48:48 +0000196 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000197}
198
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000199#define ICH_STRAP_RSVD 0x00
200#define ICH_STRAP_SPI 0x01
201#define ICH_STRAP_PCI 0x02
202#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000203
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000204static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) {
205 uint32_t mmio_base;
206
207 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
208 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000209 spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000210 fd_mem, mmio_base);
211
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000212 if (spibar == MAP_FAILED) {
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000213 perror("Can't mmap memory using " MEM_DEV);
214 exit(1);
215 }
216
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000217 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(spibar + 0x6c));
218
219 flashbus = BUS_TYPE_VIA_SPI;
220
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000221 return 0;
222}
223
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000224static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000225{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000226 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000227 uint8_t old, new, bbs, buc;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000228 uint16_t spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000229 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000230 void *rcrb;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000231 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
232
233 /* Enable Flash Writes */
234 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000235
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000236 /* Get physical address of Root Complex Register Block */
237 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000238 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000239
240 /* Map RCBA to virtual memory */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000241 rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000242 if (rcrb == MAP_FAILED) {
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000243 perror("Can't mmap memory using " MEM_DEV);
244 exit(1);
245 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000246
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000247 gcs = *(volatile uint32_t *)(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000248 printf_debug("GCS = 0x%x: ", gcs);
249 printf_debug("BIOS Interface Lock-Down: %sabled, ",
250 (gcs & 0x1) ? "en" : "dis");
251 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000252 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000253
Stefan Reinauera9424d52008-06-27 16:28:34 +0000254 buc = *(volatile uint8_t *)(rcrb + 0x3414);
255 printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
256
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000257 /* It seems the ICH7 does not support SPI and LPC chips at the same
258 * time. At least not with our current code. So we prevent searching
259 * on ICH7 when the southbridge is strapped to LPC
260 */
261
262 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
263 /* No further SPI initialization required */
264 return ret;
265 }
266
267 switch (ich_generation) {
268 case 7:
269 flashbus = BUS_TYPE_ICH7_SPI;
270 spibar_offset = 0x3020;
271 break;
272 case 8:
273 flashbus = BUS_TYPE_ICH9_SPI;
274 spibar_offset = 0x3020;
275 break;
276 case 9:
277 default: /* Future version might behave the same */
278 flashbus = BUS_TYPE_ICH9_SPI;
279 spibar_offset = 0x3800;
280 break;
281 }
282
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000283 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000284 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000285
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000286 /* Assign Virtual Address */
287 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000288
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000289 switch (flashbus) {
290 case BUS_TYPE_ICH7_SPI:
291 printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(spibar + 0));
292 printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(spibar + 2));
293 printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(spibar + 4));
Stefan Reinauera9424d52008-06-27 16:28:34 +0000294 for (i=0; i < 8; i++) {
295 int offs;
296 offs = 8 + (i * 8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000297 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(spibar + offs), i);
298 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(spibar + offs +4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000299 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000300 printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(spibar + 0x50));
301 printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(spibar + 0x54));
302 printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(spibar + 0x56));
303 printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(spibar + 0x58));
304 printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(spibar + 0x5c));
Stefan Reinauera9424d52008-06-27 16:28:34 +0000305 for (i=0; i < 4; i++) {
306 int offs;
307 offs = 0x60 + (i * 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000308 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000309 }
310 printf_debug("\n");
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000311 if ( (*(uint16_t *)spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000312 printf("WARNING: SPI Configuration Lockdown activated.\n");
313 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000314 break;
315 case BUS_TYPE_ICH9_SPI:
316 /* TODO: Add dumping function for ICH8/ICH9, or drop the
317 * whole SPIBAR dumping from chipset_enable.c - There's
318 * inteltool for this task already.
319 */
320 break;
321 default:
322 /* Nothing */
323 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000324 }
325
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000326 old = pci_read_byte(dev, 0xdc);
327 printf_debug("SPI Read Configuration: ");
328 new = (old >> 2) & 0x3;
329 switch (new) {
330 case 0:
331 case 1:
332 case 2:
333 printf_debug("prefetching %sabled, caching %sabled, ",
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000334 (new & 0x2) ? "en" : "dis",
335 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000336 break;
337 default:
338 printf_debug("invalid prefetching/caching settings, ");
339 break;
340 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000341
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000342 return ret;
343}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000344
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000345static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000346{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000347 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000348}
349
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000350static int enable_flash_ich8(struct pci_dev *dev, const char *name)
351{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000352 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000353}
354
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000355static int enable_flash_ich9(struct pci_dev *dev, const char *name)
356{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000357 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000358}
359
Uwe Hermann372eeb52007-12-04 21:49:06 +0000360static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000361{
Ollie Lho184a4042005-11-26 21:55:36 +0000362 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000363
Bari Ari9477c4e2008-04-29 13:46:38 +0000364 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF*/
365 pci_write_byte(dev, 0x41, 0x7f);
366
Uwe Hermannffec5f32007-08-23 16:08:21 +0000367 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000368 val = pci_read_byte(dev, 0x40);
369 val |= 0x10;
370 pci_write_byte(dev, 0x40, val);
371
372 if (pci_read_byte(dev, 0x40) != val) {
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000373 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000374 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000375 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000376 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000377
Uwe Hermanna7e05482007-05-09 10:17:44 +0000378 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000379}
380
Uwe Hermann372eeb52007-12-04 21:49:06 +0000381static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000382{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000383 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000384
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000385 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
386 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000387
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000388 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
389 #define ROM_WRITE_ENABLE (1 << 1)
390 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
391 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000392
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000393 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
394 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
395 * Make the configured ROM areas writable.
396 */
397 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
398 reg8 |= LOWER_ROM_ADDRESS_RANGE;
399 reg8 |= UPPER_ROM_ADDRESS_RANGE;
400 reg8 |= ROM_WRITE_ENABLE;
401 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000402
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000403 /* Set positive decode on ROM. */
404 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
405 reg8 |= BIOS_ROM_POSITIVE_DECODE;
406 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000407
Ollie Lhocbbf1252004-03-17 22:22:08 +0000408 return 0;
409}
410
Mart Raudseppe1344da2008-02-08 10:10:57 +0000411/**
412 * Geode systems write protect the BIOS via RCONFs (cache settings similar
413 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
414 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
415 * ring0 privileged instructions so only the kernel can do the read/write.
416 * This function, therefore, requires that the msr kernel module be loaded
417 * to access these instructions from user space using device /dev/cpu/0/msr.
418 *
419 * This hard-coded location could have potential problems on SMP machines
420 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
421 *
422 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
423 * To enable write to NOR Boot flash for the benefit of systems that have such
424 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
425 *
426 * This is probably not portable beyond Linux.
427 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000428static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000429{
Mart Raudseppe1344da2008-02-08 10:10:57 +0000430 #define MSR_RCONF_DEFAULT 0x1808
431 #define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000432
Lane Brooksd54958a2007-11-13 16:45:22 +0000433 int fd_msr;
434 unsigned char buf[8];
Lane Brooksd54958a2007-11-13 16:45:22 +0000435
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000436 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
Lane Brooksd54958a2007-11-13 16:45:22 +0000437 if (!fd_msr) {
438 perror("open msr");
439 return -1;
440 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000441
442 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
443 perror("lseek64");
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000444 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000445 close(fd_msr);
446 return -1;
447 }
448
449 if (read(fd_msr, buf, 8) != 8) {
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000450 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000451 close(fd_msr);
452 return -1;
453 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000454
Lane Brooksd54958a2007-11-13 16:45:22 +0000455 if (buf[7] != 0x22) {
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000456 buf[7] &= 0xfb;
Mart Raudseppe1344da2008-02-08 10:10:57 +0000457 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
458 perror("lseek64");
459 close(fd_msr);
460 return -1;
461 }
462
Lane Brooksd54958a2007-11-13 16:45:22 +0000463 if (write(fd_msr, buf, 8) < 0) {
464 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000465 close(fd_msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000466 return -1;
467 }
Lane Brooksd54958a2007-11-13 16:45:22 +0000468 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000469
Mart Raudseppe1344da2008-02-08 10:10:57 +0000470 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
471 perror("lseek64");
472 close(fd_msr);
473 return -1;
474 }
475
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000476 if (read(fd_msr, buf, 8) != 8) {
477 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000478 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000479 return -1;
480 }
481
482 /* Raise WE_CS3 bit. */
483 buf[0] |= 0x08;
484
Mart Raudseppe1344da2008-02-08 10:10:57 +0000485 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
486 perror("lseek64");
487 close(fd_msr);
488 return -1;
489 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000490 if (write(fd_msr, buf, 8) < 0) {
491 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000492 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000493 return -1;
494 }
495
496 close(fd_msr);
497
Mart Raudseppe1344da2008-02-08 10:10:57 +0000498 #undef MSR_RCONF_DEFAULT
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000499 #undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000500 return 0;
501}
502
Uwe Hermann372eeb52007-12-04 21:49:06 +0000503static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000504{
Ollie Lho184a4042005-11-26 21:55:36 +0000505 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000506
Ollie Lhocbbf1252004-03-17 22:22:08 +0000507 pci_write_byte(dev, 0x52, 0xee);
508
509 new = pci_read_byte(dev, 0x52);
510
511 if (new != 0xee) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000512 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000513 return -1;
514 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000515
Ollie Lhocbbf1252004-03-17 22:22:08 +0000516 return 0;
517}
518
Uwe Hermann372eeb52007-12-04 21:49:06 +0000519static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000520{
Ollie Lho184a4042005-11-26 21:55:36 +0000521 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000522
Ollie Lhocbbf1252004-03-17 22:22:08 +0000523 new = pci_read_byte(dev, 0x45);
524
Uwe Hermann372eeb52007-12-04 21:49:06 +0000525 new &= (~0x20); /* Clear bit 5. */
526 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000527
528 pci_write_byte(dev, 0x45, new);
529
530 newer = pci_read_byte(dev, 0x45);
531 if (newer != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000532 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000533 printf("Stuck at 0x%x\n", newer);
534 return -1;
535 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000536
Ollie Lhocbbf1252004-03-17 22:22:08 +0000537 return 0;
538}
539
Uwe Hermann372eeb52007-12-04 21:49:06 +0000540static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000541{
Ollie Lho184a4042005-11-26 21:55:36 +0000542 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000543
Uwe Hermann372eeb52007-12-04 21:49:06 +0000544 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000545 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000546 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000547 if (new != old) {
548 pci_write_byte(dev, 0x43, new);
549 if (pci_read_byte(dev, 0x43) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000550 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000551 }
552 }
553
Ollie Lho761bf1b2004-03-20 16:46:10 +0000554 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000555 new = old | 0x01;
556 if (new == old)
557 return 0;
558 pci_write_byte(dev, 0x40, new);
559
560 if (pci_read_byte(dev, 0x40) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000561 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000562 return -1;
563 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000564
Ollie Lhocbbf1252004-03-17 22:22:08 +0000565 return 0;
566}
567
Uwe Hermann372eeb52007-12-04 21:49:06 +0000568static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000569{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000570 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000571
Uwe Hermanna7e05482007-05-09 10:17:44 +0000572 old = pci_read_byte(dev, 0x88);
573 new = old | 0xc0;
574 if (new != old) {
575 pci_write_byte(dev, 0x88, new);
576 if (pci_read_byte(dev, 0x88) != new) {
577 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
578 }
579 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000580
Uwe Hermanna7e05482007-05-09 10:17:44 +0000581 old = pci_read_byte(dev, 0x6d);
582 new = old | 0x01;
583 if (new == old)
584 return 0;
585 pci_write_byte(dev, 0x6d, new);
586
587 if (pci_read_byte(dev, 0x6d) != new) {
588 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
589 return -1;
590 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000591
Uwe Hermanna7e05482007-05-09 10:17:44 +0000592 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000593}
594
Uwe Hermann372eeb52007-12-04 21:49:06 +0000595/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
596static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000597{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000598 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000599 struct pci_filter f;
600 struct pci_dev *smbusdev;
601
Uwe Hermann372eeb52007-12-04 21:49:06 +0000602 /* Look for the SMBus device. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000603 pci_filter_init((struct pci_access *)0, &f);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000604 f.vendor = 0x1002;
605 f.device = 0x4372;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000606
Stefan Reinauer86de2832006-03-31 11:26:55 +0000607 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
608 if (pci_filter_match(&f, smbusdev)) {
609 break;
610 }
611 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000612
Uwe Hermanna7e05482007-05-09 10:17:44 +0000613 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000614 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000615 exit(1);
616 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000617
Uwe Hermann372eeb52007-12-04 21:49:06 +0000618 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000619 tmp = pci_read_byte(smbusdev, 0x79);
620 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000621 pci_write_byte(smbusdev, 0x79, tmp);
622
Uwe Hermann372eeb52007-12-04 21:49:06 +0000623 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000624 tmp = pci_read_byte(dev, 0x48);
625 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000626 pci_write_byte(dev, 0x48, tmp);
627
Uwe Hermann372eeb52007-12-04 21:49:06 +0000628 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000629 tmp = INB(0xc6f);
630 OUTB(tmp, 0xeb);
631 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000632 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000633 OUTB(tmp, 0xc6f);
634 OUTB(tmp, 0xeb);
635 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000636
637 return 0;
638}
639
Uwe Hermann372eeb52007-12-04 21:49:06 +0000640static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000641{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000642 uint8_t old, new, byte;
643 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000644
Uwe Hermann372eeb52007-12-04 21:49:06 +0000645 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000646 byte = pci_read_byte(dev, 0x88);
647 byte |= 0xff; /* 256K */
648 pci_write_byte(dev, 0x88, byte);
649 byte = pci_read_byte(dev, 0x8c);
650 byte |= 0xff; /* 1M */
651 pci_write_byte(dev, 0x8c, byte);
652 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000653 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000654 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000655
Uwe Hermanna7e05482007-05-09 10:17:44 +0000656 old = pci_read_byte(dev, 0x6d);
657 new = old | 0x01;
658 if (new == old)
659 return 0;
660 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000661
Uwe Hermanna7e05482007-05-09 10:17:44 +0000662 if (pci_read_byte(dev, 0x6d) != new) {
663 printf
664 ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
665 0x6d, new, name);
666 return -1;
667 }
Yinghai Luca782972007-01-22 20:21:17 +0000668
669 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000670}
671
Uwe Hermann372eeb52007-12-04 21:49:06 +0000672static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000673{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000674 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000675
Uwe Hermanne823ee02007-06-05 15:02:18 +0000676 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000677 byte = pci_read_byte(dev, 0x41);
678 byte |= 0x0e;
679 pci_write_byte(dev, 0x41, byte);
680
681 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000682 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000683 pci_write_byte(dev, 0x43, byte);
684
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000685 return 0;
686}
687
Ollie Lhocbbf1252004-03-17 22:22:08 +0000688typedef struct penable {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000689 uint16_t vendor, device;
690 const char *name;
691 int (*doit) (struct pci_dev *dev, const char *name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000692} FLASH_ENABLE;
693
Uwe Hermann372eeb52007-12-04 21:49:06 +0000694static const FLASH_ENABLE enables[] = {
Uwe Hermanneac10162008-03-13 18:52:51 +0000695 {0x1039, 0x0630, "SiS630", enable_flash_sis630},
696 {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
697 {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
698 {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
699 {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
700 {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
701 {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
702 {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
703 {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
704 {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
705 {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
706 {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
Claus Gindharta00e2a02008-05-14 12:22:38 +0000707 {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
Uwe Hermanneac10162008-03-13 18:52:51 +0000708 {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
709 {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
Ed Swierkcd2ed472008-08-20 20:31:41 +0000710 {0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc},
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000711 {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
712 {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
713 {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
714 {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7},
715 {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8},
716 {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8},
717 {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8},
718 {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8},
719 {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8},
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000720 {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9},
721 {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9},
722 {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9},
723 {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9},
724 {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9},
725 {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9},
Uwe Hermanneac10162008-03-13 18:52:51 +0000726 {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
727 {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
728 {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000729 {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi},
Uwe Hermanneac10162008-03-13 18:52:51 +0000730 {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
731 {0x1106, 0x0686, "VIA VT82C686", enable_flash_amd8111},
732 {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
733 {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
734 {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
735 {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
736 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
737 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
738 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
739 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
740 /* Slave, should not be here, to fix known bug for A01. */
741 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
742 {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
743 {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
744 {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
745 {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
746 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
747 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
748 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
749 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
750 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
751 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
752 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
753 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
Stefan Reinauer7f274642008-07-05 09:48:30 +0000754 {0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55},
Uwe Hermanneac10162008-03-13 18:52:51 +0000755 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
756 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
Ollie Lhocbbf1252004-03-17 22:22:08 +0000757};
Ollie Lho761bf1b2004-03-20 16:46:10 +0000758
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000759void print_supported_chipsets(void)
760{
761 int i;
762
763 printf("\nSupported chipsets:\n\n");
764
765 for (i = 0; i < ARRAY_SIZE(enables); i++)
766 printf("%s (%04x:%04x)\n", enables[i].name,
767 enables[i].vendor, enables[i].device);
768}
769
Uwe Hermanna7e05482007-05-09 10:17:44 +0000770int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000771{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000772 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +0000773 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000774 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000775
Uwe Hermann372eeb52007-12-04 21:49:06 +0000776 /* Now let's try to find the chipset we have... */
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000777 for (i = 0; i < ARRAY_SIZE(enables); i++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000778 dev = pci_dev_find(enables[i].vendor, enables[i].device);
779 if (dev)
780 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000781 }
782
Uwe Hermanna7e05482007-05-09 10:17:44 +0000783 if (dev) {
Uwe Hermanna502dce2007-10-17 23:55:15 +0000784 printf("Found chipset \"%s\", enabling flash write... ",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000785 enables[i].name);
786
787 ret = enables[i].doit(dev, enables[i].name);
788 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +0000789 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000790 else
Uwe Hermannac309342007-10-10 17:42:20 +0000791 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000792 }
793
794 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000795}