blob: b13318b1158817365c75ce9806a1588e0ff0cd73 [file] [log] [blame]
Sean Nelson14ba6682010-02-26 05:48:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00004 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
Sean Nelson14ba6682010-02-26 05:48:29 +00005 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Sean Nelson14ba6682010-02-26 05:48:29 +000015 */
16
17/*
18 * Contains the common SPI chip driver functions
19 */
20
Nico Hubera3140d02017-10-15 11:20:58 +020021#include <stddef.h>
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include <string.h>
Nico Hubera1672f82017-10-14 18:00:20 +020023#include <stdbool.h>
Sean Nelson14ba6682010-02-26 05:48:29 +000024#include "flash.h"
25#include "flashchips.h"
26#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000028#include "spi.h"
29
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000030static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000031{
Mathias Krausea60faab2011-01-17 07:50:42 +000032 static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Sean Nelson14ba6682010-02-26 05:48:29 +000033 int ret;
34 int i;
35
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000036 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000037 if (ret)
38 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000039 msg_cspew("RDID returned");
Sean Nelson14ba6682010-02-26 05:48:29 +000040 for (i = 0; i < bytes; i++)
Sean Nelsoned479d22010-03-24 23:14:32 +000041 msg_cspew(" 0x%02x", readarr[i]);
42 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000043 return 0;
44}
45
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000046static int spi_rems(struct flashctx *flash, unsigned char *readarr)
Sean Nelson14ba6682010-02-26 05:48:29 +000047{
Nico Hubered098d62017-04-21 23:47:08 +020048 static const unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, };
Sean Nelson14ba6682010-02-26 05:48:29 +000049 int ret;
50
Nico Hubered098d62017-04-21 23:47:08 +020051 ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000052 if (ret)
53 return ret;
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +000054 msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]);
Sean Nelson14ba6682010-02-26 05:48:29 +000055 return 0;
56}
57
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000058static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000059{
Nico Hubered098d62017-04-21 23:47:08 +020060 static const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, };
Sean Nelson14ba6682010-02-26 05:48:29 +000061 int ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000062 int i;
Sean Nelson14ba6682010-02-26 05:48:29 +000063
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000064 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000065 if (ret)
66 return ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000067 msg_cspew("RES returned");
68 for (i = 0; i < bytes; i++)
69 msg_cspew(" 0x%02x", readarr[i]);
70 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000071 return 0;
72}
73
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000074int spi_write_enable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +000075{
Mathias Krausea60faab2011-01-17 07:50:42 +000076 static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Sean Nelson14ba6682010-02-26 05:48:29 +000077 int result;
78
79 /* Send WREN (Write Enable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000080 result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +000081
82 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +000083 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +000084
85 return result;
86}
87
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000088int spi_write_disable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +000089{
Mathias Krausea60faab2011-01-17 07:50:42 +000090 static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Sean Nelson14ba6682010-02-26 05:48:29 +000091
92 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000093 return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +000094}
95
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000096static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000097{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +000098 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +000099 unsigned char readarr[4];
100 uint32_t id1;
101 uint32_t id2;
102
Nico Huber959aafa2017-04-22 00:13:15 +0200103 const int ret = spi_rdid(flash, readarr, bytes);
104 if (ret == SPI_INVALID_LENGTH)
105 msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes);
106 if (ret)
Sean Nelson14ba6682010-02-26 05:48:29 +0000107 return 0;
108
109 if (!oddparity(readarr[0]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000110 msg_cdbg("RDID byte 0 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000111
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000112 /* Check if this is a continuation vendor ID.
113 * FIXME: Handle continuation device IDs.
114 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000115 if (readarr[0] == 0x7f) {
116 if (!oddparity(readarr[1]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000117 msg_cdbg("RDID byte 1 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000118 id1 = (readarr[0] << 8) | readarr[1];
119 id2 = readarr[2];
120 if (bytes > 3) {
121 id2 <<= 8;
122 id2 |= readarr[3];
123 }
124 } else {
125 id1 = readarr[0];
126 id2 = (readarr[1] << 8) | readarr[2];
127 }
128
Sean Nelsoned479d22010-03-24 23:14:32 +0000129 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000130
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000131 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000132 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000133
134 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000135 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000136 return 1;
137
138 /* Test if there is any vendor ID. */
Urja Rannikko0a5f6e42015-06-22 23:59:15 +0000139 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00)
Sean Nelson14ba6682010-02-26 05:48:29 +0000140 return 1;
141
142 return 0;
143}
144
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000145int probe_spi_rdid(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000146{
147 return probe_spi_rdid_generic(flash, 3);
148}
149
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000150int probe_spi_rdid4(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000151{
Nico Huber959aafa2017-04-22 00:13:15 +0200152 return probe_spi_rdid_generic(flash, 4);
Sean Nelson14ba6682010-02-26 05:48:29 +0000153}
154
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000155int probe_spi_rems(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000156{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000157 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +0000158 unsigned char readarr[JEDEC_REMS_INSIZE];
159 uint32_t id1, id2;
160
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000161 if (spi_rems(flash, readarr)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000162 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000163 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000164
165 id1 = readarr[0];
166 id2 = readarr[1];
167
Sean Nelsoned479d22010-03-24 23:14:32 +0000168 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000169
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000170 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000171 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000172
173 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000174 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000175 return 1;
176
177 /* Test if there is any vendor ID. */
Urja Rannikko0a5f6e42015-06-22 23:59:15 +0000178 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00)
Sean Nelson14ba6682010-02-26 05:48:29 +0000179 return 1;
180
181 return 0;
182}
183
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000184int probe_spi_res1(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000185{
Mathias Krausea60faab2011-01-17 07:50:42 +0000186 static const unsigned char allff[] = {0xff, 0xff, 0xff};
187 static const unsigned char all00[] = {0x00, 0x00, 0x00};
Sean Nelson14ba6682010-02-26 05:48:29 +0000188 unsigned char readarr[3];
189 uint32_t id2;
Sean Nelson14ba6682010-02-26 05:48:29 +0000190
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000191 /* We only want one-byte RES if RDID and REMS are unusable. */
192
Sean Nelson14ba6682010-02-26 05:48:29 +0000193 /* Check if RDID is usable and does not return 0xff 0xff 0xff or
194 * 0x00 0x00 0x00. In that case, RES is pointless.
195 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000196 if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000197 memcmp(readarr, all00, 3)) {
198 msg_cdbg("Ignoring RES in favour of RDID.\n");
199 return 0;
200 }
201 /* Check if REMS is usable and does not return 0xff 0xff or
202 * 0x00 0x00. In that case, RES is pointless.
203 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000204 if (!spi_rems(flash, readarr) &&
205 memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000206 memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
207 msg_cdbg("Ignoring RES in favour of REMS.\n");
208 return 0;
209 }
210
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000211 if (spi_res(flash, readarr, 1)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000212 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000213 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000214
Sean Nelson14ba6682010-02-26 05:48:29 +0000215 id2 = readarr[0];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000216
Sean Nelsoned479d22010-03-24 23:14:32 +0000217 msg_cdbg("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000218
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000219 if (id2 != flash->chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000220 return 0;
221
Sean Nelson14ba6682010-02-26 05:48:29 +0000222 return 1;
223}
224
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000225int probe_spi_res2(struct flashctx *flash)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000226{
227 unsigned char readarr[2];
228 uint32_t id1, id2;
229
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000230 if (spi_res(flash, readarr, 2)) {
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000231 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000232 }
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000233
234 id1 = readarr[0];
235 id2 = readarr[1];
236
237 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
238
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000239 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000240 return 0;
241
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000242 return 1;
243}
244
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000245int probe_spi_res3(struct flashctx *flash)
246{
247 unsigned char readarr[3];
248 uint32_t id1, id2;
249
250 if (spi_res(flash, readarr, 3)) {
251 return 0;
252 }
253
254 id1 = (readarr[0] << 8) | readarr[1];
255 id2 = readarr[2];
256
257 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
258
259 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
260 return 0;
261
262 return 1;
263}
264
Stefan Tauner57794ac2012-12-29 15:04:20 +0000265/* Only used for some Atmel chips. */
266int probe_spi_at25f(struct flashctx *flash)
267{
268 static const unsigned char cmd[AT25F_RDID_OUTSIZE] = { AT25F_RDID };
269 unsigned char readarr[AT25F_RDID_INSIZE];
270 uint32_t id1;
271 uint32_t id2;
272
273 if (spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr))
274 return 0;
275
276 id1 = readarr[0];
277 id2 = readarr[1];
278
279 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
280
281 if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
282 return 1;
283
284 return 0;
285}
286
Nico Huber0ecbacb2017-10-14 16:50:43 +0200287static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay)
288{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200289 /* FIXME: We don't time out. */
Nikolai Artemievb8a90d02021-10-28 16:18:28 +1100290 while (true) {
291 uint8_t status;
292 int ret = spi_read_register(flash, STATUS1, &status);
293 if (ret)
294 return ret;
295 if (!(status & SPI_SR_WIP))
296 return 0;
297
Nico Huber0ecbacb2017-10-14 16:50:43 +0200298 programmer_delay(poll_delay);
Nikolai Artemievb8a90d02021-10-28 16:18:28 +1100299 }
Nico Huber0ecbacb2017-10-14 16:50:43 +0200300}
301
Nico Hubera3140d02017-10-15 11:20:58 +0200302/**
303 * Execute WREN plus another one byte `op`, optionally poll WIP afterwards.
304 *
305 * @param flash the flash chip's context
306 * @param op the operation to execute
307 * @param poll_delay interval in us for polling WIP, don't poll if zero
308 * @return 0 on success, non-zero otherwise
309 */
310static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op, const unsigned int poll_delay)
Sean Nelson14ba6682010-02-26 05:48:29 +0000311{
Sean Nelson14ba6682010-02-26 05:48:29 +0000312 struct spi_command cmds[] = {
313 {
Richard Hughesdf490582018-12-19 11:57:15 +0000314 .readarr = 0,
Nico Hubera3140d02017-10-15 11:20:58 +0200315 .writecnt = 1,
316 .writearr = (const unsigned char[]){ JEDEC_WREN },
Sean Nelson14ba6682010-02-26 05:48:29 +0000317 }, {
Richard Hughesdf490582018-12-19 11:57:15 +0000318 .readarr = 0,
Nico Hubera3140d02017-10-15 11:20:58 +0200319 .writecnt = 1,
320 .writearr = (const unsigned char[]){ op },
321 },
322 NULL_SPI_CMD,
323 };
324
325 const int result = spi_send_multicommand(flash, cmds);
326 if (result)
327 msg_cerr("%s failed during command execution\n", __func__);
328
Nico Huber0ecbacb2017-10-14 16:50:43 +0200329 const int status = poll_delay ? spi_poll_wip(flash, poll_delay) : 0;
Nico Hubera3140d02017-10-15 11:20:58 +0200330
Nico Huber0ecbacb2017-10-14 16:50:43 +0200331 return result ? result : status;
332}
333
Nico Huber7e3c81a2017-10-14 18:56:50 +0200334static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata)
335{
Nico Huber9bb8a322022-05-24 15:07:34 +0200336 uint8_t op;
337 if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) {
338 op = JEDEC_WRITE_EXT_ADDR_REG;
339 } else if (flash->chip->feature_bits & FEATURE_4BA_EAR_1716) {
340 op = ALT_WRITE_EXT_ADDR_REG_17;
341 } else {
342 msg_cerr("Flash misses feature flag for extended-address register.\n");
343 return -1;
344 }
345
Nico Huber7e3c81a2017-10-14 18:56:50 +0200346 struct spi_command cmds[] = {
347 {
Richard Hughesdf490582018-12-19 11:57:15 +0000348 .readarr = 0,
Nico Huber7e3c81a2017-10-14 18:56:50 +0200349 .writecnt = 1,
350 .writearr = (const unsigned char[]){ JEDEC_WREN },
351 }, {
Richard Hughesdf490582018-12-19 11:57:15 +0000352 .readarr = 0,
Nico Huber7e3c81a2017-10-14 18:56:50 +0200353 .writecnt = 2,
Nico Huber57dbd642018-03-13 18:01:05 +0100354 .writearr = (const unsigned char[]){ op, regdata },
Nico Huber7e3c81a2017-10-14 18:56:50 +0200355 },
356 NULL_SPI_CMD,
357 };
358
359 const int result = spi_send_multicommand(flash, cmds);
360 if (result)
361 msg_cerr("%s failed during command execution\n", __func__);
362 return result;
363}
364
Nico Huber7eb38aa2019-03-21 15:42:54 +0100365int spi_set_extended_address(struct flashctx *const flash, const uint8_t addr_high)
Nico Huberf43c6542017-10-14 17:47:28 +0200366{
367 if (flash->address_high_byte != addr_high &&
368 spi_write_extended_address_register(flash, addr_high))
369 return -1;
370 flash->address_high_byte = addr_high;
371 return 0;
372}
373
Nico Hubera1672f82017-10-14 18:00:20 +0200374static int spi_prepare_address(struct flashctx *const flash, uint8_t cmd_buf[],
375 const bool native_4ba, const unsigned int addr)
Nico Huber0ecbacb2017-10-14 16:50:43 +0200376{
Nico Hubera1672f82017-10-14 18:00:20 +0200377 if (native_4ba || flash->in_4ba_mode) {
Nico Huber1cf407b2017-11-10 20:18:23 +0100378 if (!spi_master_4ba(flash)) {
379 msg_cwarn("4-byte address requested but master can't handle 4-byte addresses.\n");
380 return -1;
381 }
Nico Huberf43c6542017-10-14 17:47:28 +0200382 cmd_buf[1] = (addr >> 24) & 0xff;
383 cmd_buf[2] = (addr >> 16) & 0xff;
384 cmd_buf[3] = (addr >> 8) & 0xff;
385 cmd_buf[4] = (addr >> 0) & 0xff;
386 return 4;
387 } else {
Nico Huber9bb8a322022-05-24 15:07:34 +0200388 if (flash->chip->feature_bits & FEATURE_4BA_EAR_ANY) {
Nico Huberf43c6542017-10-14 17:47:28 +0200389 if (spi_set_extended_address(flash, addr >> 24))
390 return -1;
Nico Huber1cf407b2017-11-10 20:18:23 +0100391 } else if (addr >> 24) {
392 msg_cerr("Can't handle 4-byte address for opcode '0x%02x'\n"
393 "with this chip/programmer combination.\n", cmd_buf[0]);
394 return -1;
Nico Huberf43c6542017-10-14 17:47:28 +0200395 }
396 cmd_buf[1] = (addr >> 16) & 0xff;
397 cmd_buf[2] = (addr >> 8) & 0xff;
398 cmd_buf[3] = (addr >> 0) & 0xff;
399 return 3;
400 }
Nico Huber0ecbacb2017-10-14 16:50:43 +0200401}
402
403/**
404 * Execute WREN plus another `op` that takes an address and
405 * optional data, poll WIP afterwards.
406 *
407 * @param flash the flash chip's context
408 * @param op the operation to execute
Nico Hubera1672f82017-10-14 18:00:20 +0200409 * @param native_4ba whether `op` always takes a 4-byte address
Nico Huber0ecbacb2017-10-14 16:50:43 +0200410 * @param addr the address parameter to `op`
411 * @param out_bytes bytes to send after the address,
412 * may be NULL if and only if `out_bytes` is 0
413 * @param out_bytes number of bytes to send, 256 at most, may be zero
414 * @param poll_delay interval in us for polling WIP
415 * @return 0 on success, non-zero otherwise
416 */
Nico Hubera1672f82017-10-14 18:00:20 +0200417static int spi_write_cmd(struct flashctx *const flash, const uint8_t op,
418 const bool native_4ba, const unsigned int addr,
Nico Huber0ecbacb2017-10-14 16:50:43 +0200419 const uint8_t *const out_bytes, const size_t out_len,
420 const unsigned int poll_delay)
421{
422 uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN + 256];
423 struct spi_command cmds[] = {
424 {
Richard Hughesdf490582018-12-19 11:57:15 +0000425 .readarr = 0,
Nico Huber0ecbacb2017-10-14 16:50:43 +0200426 .writecnt = 1,
427 .writearr = (const unsigned char[]){ JEDEC_WREN },
428 }, {
Richard Hughesdf490582018-12-19 11:57:15 +0000429 .readarr = 0,
Nico Huber0ecbacb2017-10-14 16:50:43 +0200430 .writearr = cmd,
431 },
432 NULL_SPI_CMD,
433 };
434
435 cmd[0] = op;
Nico Hubera1672f82017-10-14 18:00:20 +0200436 const int addr_len = spi_prepare_address(flash, cmd, native_4ba, addr);
Nico Huber0ecbacb2017-10-14 16:50:43 +0200437 if (addr_len < 0)
438 return 1;
439
440 if (1 + addr_len + out_len > sizeof(cmd)) {
441 msg_cerr("%s called for too long a write\n", __func__);
442 return 1;
443 }
Angel Ponsc92f6872020-03-31 15:32:10 +0200444 if (!out_bytes && out_len > 0)
445 return 1;
Nico Huber0ecbacb2017-10-14 16:50:43 +0200446
447 memcpy(cmd + 1 + addr_len, out_bytes, out_len);
448 cmds[1].writecnt = 1 + addr_len + out_len;
449
450 const int result = spi_send_multicommand(flash, cmds);
451 if (result)
452 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
453
454 const int status = spi_poll_wip(flash, poll_delay);
455
456 return result ? result : status;
Nico Hubera3140d02017-10-15 11:20:58 +0200457}
458
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600459static int spi_chip_erase_60(struct flashctx *flash)
Nico Hubera3140d02017-10-15 11:20:58 +0200460{
461 /* This usually takes 1-85s, so wait in 1s steps. */
462 return spi_simple_write_cmd(flash, 0x60, 1000 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000463}
464
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600465static int spi_chip_erase_62(struct flashctx *flash)
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000466{
Nico Hubera3140d02017-10-15 11:20:58 +0200467 /* This usually takes 2-5s, so wait in 100ms steps. */
468 return spi_simple_write_cmd(flash, 0x62, 100 * 1000);
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000469}
470
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600471static int spi_chip_erase_c7(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000472{
Nico Hubera3140d02017-10-15 11:20:58 +0200473 /* This usually takes 1-85s, so wait in 1s steps. */
474 return spi_simple_write_cmd(flash, 0xc7, 1000 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000475}
476
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000477int spi_block_erase_52(struct flashctx *flash, unsigned int addr,
478 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000479{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200480 /* This usually takes 100-4000ms, so wait in 100ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200481 return spi_write_cmd(flash, 0x52, false, addr, NULL, 0, 100 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000482}
483
484/* Block size is usually
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000485 * 32M (one die) for Micron
486 */
487int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
488{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200489 /* This usually takes 240-480s, so wait in 500ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200490 return spi_write_cmd(flash, 0xc4, false, addr, NULL, 0, 500 * 1000);
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000491}
492
493/* Block size is usually
Sean Nelson14ba6682010-02-26 05:48:29 +0000494 * 64k for Macronix
495 * 32k for SST
496 * 4-32k non-uniform for EON
497 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000498int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,
499 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000500{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200501 /* This usually takes 100-4000ms, so wait in 100ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200502 return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000503}
504
505/* Block size is usually
506 * 4k for PMC
507 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000508int spi_block_erase_d7(struct flashctx *flash, unsigned int addr,
509 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000510{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200511 /* This usually takes 100-4000ms, so wait in 100ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200512 return spi_write_cmd(flash, 0xd7, false, addr, NULL, 0, 100 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000513}
514
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000515/* Page erase (usually 256B blocks) */
516int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
517{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200518 /* This takes up to 20ms usually (on worn out devices
519 up to the 0.5s range), so wait in 1ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200520 return spi_write_cmd(flash, 0xdb, false, addr, NULL, 0, 1 * 1000);
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000521}
522
Sean Nelson14ba6682010-02-26 05:48:29 +0000523/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000524int spi_block_erase_20(struct flashctx *flash, unsigned int addr,
525 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000526{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200527 /* This usually takes 15-800ms, so wait in 10ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200528 return spi_write_cmd(flash, 0x20, false, addr, NULL, 0, 10 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000529}
530
Stefan Tauner94b39b42012-10-27 00:06:02 +0000531int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
532{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200533 /* This usually takes 10ms, so wait in 1ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200534 return spi_write_cmd(flash, 0x50, false, addr, NULL, 0, 1 * 1000);
Stefan Tauner94b39b42012-10-27 00:06:02 +0000535}
536
537int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
538{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200539 /* This usually takes 8ms, so wait in 1ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200540 return spi_write_cmd(flash, 0x81, false, addr, NULL, 0, 1 * 1000);
Stefan Tauner94b39b42012-10-27 00:06:02 +0000541}
542
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000543int spi_block_erase_60(struct flashctx *flash, unsigned int addr,
544 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000545{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000546 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000547 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000548 __func__);
549 return -1;
550 }
551 return spi_chip_erase_60(flash);
552}
553
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000554int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
555{
556 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
557 msg_cerr("%s called with incorrect arguments\n",
558 __func__);
559 return -1;
560 }
561 return spi_chip_erase_62(flash);
562}
563
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000564int spi_block_erase_c7(struct flashctx *flash, unsigned int addr,
565 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000566{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000567 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000568 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000569 __func__);
570 return -1;
571 }
572 return spi_chip_erase_c7(flash);
573}
574
Nico Huber7e3c81a2017-10-14 18:56:50 +0200575/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
576int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
577{
578 /* This usually takes 15-800ms, so wait in 10ms steps. */
579 return spi_write_cmd(flash, 0x21, true, addr, NULL, 0, 10 * 1000);
580}
581
582/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
Nico Huberfffc48d2022-05-28 14:26:06 +0200583int spi_block_erase_53(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
584{
585 /* This usually takes 100-4000ms, so wait in 100ms steps. */
586 return spi_write_cmd(flash, 0x53, true, addr, NULL, 0, 100 * 1000);
587}
588
589/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
Nico Huber7e3c81a2017-10-14 18:56:50 +0200590int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
591{
592 /* This usually takes 100-4000ms, so wait in 100ms steps. */
593 return spi_write_cmd(flash, 0x5c, true, addr, NULL, 0, 100 * 1000);
594}
595
596/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
597int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
598{
599 /* This usually takes 100-4000ms, so wait in 100ms steps. */
600 return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000);
601}
602
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000603erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)
604{
605 switch(opcode){
606 case 0xff:
607 case 0x00:
608 /* Not specified, assuming "not supported". */
609 return NULL;
610 case 0x20:
611 return &spi_block_erase_20;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200612 case 0x21:
613 return &spi_block_erase_21;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000614 case 0x50:
615 return &spi_block_erase_50;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000616 case 0x52:
617 return &spi_block_erase_52;
Nico Huberfffc48d2022-05-28 14:26:06 +0200618 case 0x53:
619 return &spi_block_erase_53;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200620 case 0x5c:
621 return &spi_block_erase_5c;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000622 case 0x60:
623 return &spi_block_erase_60;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000624 case 0x62:
625 return &spi_block_erase_62;
626 case 0x81:
627 return &spi_block_erase_81;
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000628 case 0xc4:
629 return &spi_block_erase_c4;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000630 case 0xc7:
631 return &spi_block_erase_c7;
632 case 0xd7:
633 return &spi_block_erase_d7;
634 case 0xd8:
635 return &spi_block_erase_d8;
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000636 case 0xdb:
637 return &spi_block_erase_db;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200638 case 0xdc:
639 return &spi_block_erase_dc;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000640 default:
Nico Huberac90af62022-12-18 00:22:47 +0000641 msg_cinfo("%s: unknown erase opcode (0x%02x).\n"
642 "Please report this at flashrom-stable@flashrom.org\n",
643 __func__, opcode);
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000644 return NULL;
645 }
646}
647
Nico Huber0ecbacb2017-10-14 16:50:43 +0200648static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000649{
Nico Huber1cf407b2017-11-10 20:18:23 +0100650 const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash);
Nico Hubera1672f82017-10-14 18:00:20 +0200651 const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM;
652 return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10);
Sean Nelson14ba6682010-02-26 05:48:29 +0000653}
654
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000655int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes,
656 unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000657{
Nico Huber1cf407b2017-11-10 20:18:23 +0100658 const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_READ && spi_master_4ba(flash);
Nico Hubera1672f82017-10-14 18:00:20 +0200659 uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, };
Nico Huber0ecbacb2017-10-14 16:50:43 +0200660
Nico Hubera1672f82017-10-14 18:00:20 +0200661 const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address);
Nico Huber0ecbacb2017-10-14 16:50:43 +0200662 if (addr_len < 0)
663 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000664
665 /* Send Read */
Nico Huber0ecbacb2017-10-14 16:50:43 +0200666 return spi_send_command(flash, 1 + addr_len, len, cmd, bytes);
Sean Nelson14ba6682010-02-26 05:48:29 +0000667}
668
669/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000670 * Read a part of the flash chip.
Nico Huberd8b2e802019-06-18 23:39:56 +0200671 * Data is read in chunks with a maximum size of chunksize.
Sean Nelson14ba6682010-02-26 05:48:29 +0000672 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000673int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
674 unsigned int len, unsigned int chunksize)
Sean Nelson14ba6682010-02-26 05:48:29 +0000675{
Nico Huberd8b2e802019-06-18 23:39:56 +0200676 int ret;
677 size_t to_read;
678 for (; len; len -= to_read, buf += to_read, start += to_read) {
679 to_read = min(chunksize, len);
680 ret = spi_nbyte_read(flash, start, buf, to_read);
681 if (ret)
682 return ret;
Sean Nelson14ba6682010-02-26 05:48:29 +0000683 }
Nico Huberd8b2e802019-06-18 23:39:56 +0200684 return 0;
Sean Nelson14ba6682010-02-26 05:48:29 +0000685}
686
687/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000688 * Write a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000689 * FIXME: Use the chunk code from Michael Karcher instead.
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000690 * Each page is written separately in chunks with a maximum size of chunksize.
691 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000692int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000693 unsigned int len, unsigned int chunksize)
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000694{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000695 unsigned int i, j, starthere, lenhere, towrite;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000696 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000697 * in struct flashctx to do this properly. All chips using
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000698 * spi_chip_write_256 have page_size set to max_writechunk_size, so
699 * we're OK for now.
700 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000701 unsigned int page_size = flash->chip->page_size;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000702
703 /* Warning: This loop has a very unusual condition and body.
704 * The loop needs to go through each page with at least one affected
705 * byte. The lowest page number is (start / page_size) since that
706 * division rounds down. The highest page number we want is the page
707 * where the last byte of the range lives. That last byte has the
708 * address (start + len - 1), thus the highest page number is
709 * (start + len - 1) / page_size. Since we want to include that last
710 * page as well, the loop condition uses <=.
711 */
712 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
713 /* Byte position of the first byte in the range in this page. */
714 /* starthere is an offset to the base address of the chip. */
715 starthere = max(start, i * page_size);
716 /* Length of bytes in the range in this page. */
717 lenhere = min(start + len, (i + 1) * page_size) - starthere;
718 for (j = 0; j < lenhere; j += chunksize) {
Nico Huber7a077222017-10-14 18:18:30 +0200719 int rc;
720
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000721 towrite = min(chunksize, lenhere - j);
Nico Huber7a077222017-10-14 18:18:30 +0200722 rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000723 if (rc)
Nico Huber7a077222017-10-14 18:18:30 +0200724 return rc;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000725 }
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000726 }
727
Nico Huber7a077222017-10-14 18:18:30 +0200728 return 0;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000729}
730
731/*
Sean Nelson14ba6682010-02-26 05:48:29 +0000732 * Program chip using byte programming. (SLOW!)
733 * This is for chips which can only handle one byte writes
734 * and for chips where memory mapped programming is impossible
735 * (e.g. due to size constraints in IT87* for over 512 kB)
736 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000737/* real chunksize is 1, logical chunksize is 1 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000738int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000739{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000740 unsigned int i;
Sean Nelson14ba6682010-02-26 05:48:29 +0000741
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000742 for (i = start; i < start + len; i++) {
Nico Huber7a077222017-10-14 18:18:30 +0200743 if (spi_nbyte_program(flash, i, buf + i - start, 1))
Sean Nelson14ba6682010-02-26 05:48:29 +0000744 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000745 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000746 return 0;
747}
748
Mark Marshallf20b7be2014-05-09 21:16:21 +0000749int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000750{
751 uint32_t pos = start;
Sean Nelson14ba6682010-02-26 05:48:29 +0000752 int result;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000753 unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {
754 JEDEC_AAI_WORD_PROGRAM,
755 };
Sean Nelson14ba6682010-02-26 05:48:29 +0000756
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000757 /* The even start address and even length requirements can be either
758 * honored outside this function, or we can call spi_byte_program
759 * for the first and/or last byte and use AAI for the rest.
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000760 * FIXME: Move this to generic code.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000761 */
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000762 /* The data sheet requires a start address with the low bit cleared. */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000763 if (start % 2) {
Nico Huberac90af62022-12-18 00:22:47 +0000764 msg_cerr("%s: start address not even!\n"
765 "Please report a bug at flashrom-stable@flashrom.org\n",
766 __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000767 if (spi_chip_write_1(flash, buf, start, start % 2))
768 return SPI_GENERIC_ERROR;
769 pos += start % 2;
770 /* Do not return an error for now. */
771 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000772 }
773 /* The data sheet requires total AAI write length to be even. */
774 if (len % 2) {
Nico Huberac90af62022-12-18 00:22:47 +0000775 msg_cerr("%s: total write length not even!\n"
776 "Please report a bug at flashrom-stable@flashrom.org\n",
777 __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000778 /* Do not return an error for now. */
779 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000780 }
781
Nico Hubera1672f82017-10-14 18:00:20 +0200782 result = spi_write_cmd(flash, JEDEC_AAI_WORD_PROGRAM, false, start, buf + pos - start, 2, 10);
Nico Huber0ecbacb2017-10-14 16:50:43 +0200783 if (result)
Stefan Reinauer87ace662014-04-26 16:12:55 +0000784 goto bailout;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000785
786 /* We already wrote 2 bytes in the multicommand step. */
787 pos += 2;
788
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000789 /* Are there at least two more bytes to write? */
790 while (pos < start + len - 1) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000791 cmd[1] = buf[pos++ - start];
792 cmd[2] = buf[pos++ - start];
Stefan Reinauer87ace662014-04-26 16:12:55 +0000793 result = spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
794 if (result != 0) {
795 msg_cerr("%s failed during followup AAI command execution: %d\n", __func__, result);
796 goto bailout;
797 }
Nico Huber0ecbacb2017-10-14 16:50:43 +0200798 if (spi_poll_wip(flash, 10))
799 goto bailout;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000800 }
801
Stefan Tauner59c4d792014-04-26 16:13:09 +0000802 /* Use WRDI to exit AAI mode. This needs to be done before issuing any other non-AAI command. */
803 result = spi_write_disable(flash);
804 if (result != 0) {
805 msg_cerr("%s failed to disable AAI mode.\n", __func__);
806 return SPI_GENERIC_ERROR;
807 }
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000808
809 /* Write remaining byte (if any). */
810 if (pos < start + len) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000811 if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000812 return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000813 }
814
Sean Nelson14ba6682010-02-26 05:48:29 +0000815 return 0;
Stefan Reinauer87ace662014-04-26 16:12:55 +0000816
817bailout:
Stefan Tauner59c4d792014-04-26 16:13:09 +0000818 result = spi_write_disable(flash);
819 if (result != 0)
820 msg_cerr("%s failed to disable AAI mode.\n", __func__);
Stefan Reinauer87ace662014-04-26 16:12:55 +0000821 return SPI_GENERIC_ERROR;
Sean Nelson14ba6682010-02-26 05:48:29 +0000822}
Nico Huber7e3c81a2017-10-14 18:56:50 +0200823
Nico Huberfe34d2a2017-11-10 21:10:20 +0100824static int spi_enter_exit_4ba(struct flashctx *const flash, const bool enter)
Nico Huber7e3c81a2017-10-14 18:56:50 +0200825{
Nico Huberfe34d2a2017-11-10 21:10:20 +0100826 const unsigned char cmd = enter ? JEDEC_ENTER_4_BYTE_ADDR_MODE : JEDEC_EXIT_4_BYTE_ADDR_MODE;
827 int ret = 1;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200828
Nico Huberfe34d2a2017-11-10 21:10:20 +0100829 if (flash->chip->feature_bits & FEATURE_4BA_ENTER)
830 ret = spi_send_command(flash, sizeof(cmd), 0, &cmd, NULL);
831 else if (flash->chip->feature_bits & FEATURE_4BA_ENTER_WREN)
832 ret = spi_simple_write_cmd(flash, cmd, 0);
Nico Huber86bddb52018-03-13 18:14:52 +0100833 else if (flash->chip->feature_bits & FEATURE_4BA_ENTER_EAR7)
834 ret = spi_set_extended_address(flash, enter ? 0x80 : 0x00);
Nico Huberfe34d2a2017-11-10 21:10:20 +0100835
Nico Huber7e3c81a2017-10-14 18:56:50 +0200836 if (!ret)
Nico Huberfe34d2a2017-11-10 21:10:20 +0100837 flash->in_4ba_mode = enter;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200838 return ret;
839}
840
Nico Huberfe34d2a2017-11-10 21:10:20 +0100841int spi_enter_4ba(struct flashctx *const flash)
Nico Huber7e3c81a2017-10-14 18:56:50 +0200842{
Nico Huberfe34d2a2017-11-10 21:10:20 +0100843 return spi_enter_exit_4ba(flash, true);
Nico Huber7e3c81a2017-10-14 18:56:50 +0200844}
845
Nico Huberfe34d2a2017-11-10 21:10:20 +0100846int spi_exit_4ba(struct flashctx *flash)
Nico Huber7e3c81a2017-10-14 18:56:50 +0200847{
Nico Huberfe34d2a2017-11-10 21:10:20 +0100848 return spi_enter_exit_4ba(flash, false);
Nico Huber7e3c81a2017-10-14 18:56:50 +0200849}