Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the common SPI chip driver functions |
| 23 | */ |
| 24 | |
| 25 | #include <string.h> |
| 26 | #include "flash.h" |
| 27 | #include "flashchips.h" |
| 28 | #include "chipdrivers.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 29 | #include "programmer.h" |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 30 | #include "spi.h" |
| 31 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 32 | static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 33 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 34 | static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 35 | int ret; |
| 36 | int i; |
| 37 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 38 | ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 39 | if (ret) |
| 40 | return ret; |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 41 | msg_cspew("RDID returned"); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 42 | for (i = 0; i < bytes; i++) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 43 | msg_cspew(" 0x%02x", readarr[i]); |
| 44 | msg_cspew(". "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 45 | return 0; |
| 46 | } |
| 47 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 48 | static int spi_rems(struct flashctx *flash, unsigned char *readarr) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 49 | { |
| 50 | unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; |
| 51 | uint32_t readaddr; |
| 52 | int ret; |
| 53 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 54 | ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, |
| 55 | readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 56 | if (ret == SPI_INVALID_ADDRESS) { |
| 57 | /* Find the lowest even address allowed for reads. */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 58 | readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 59 | cmd[1] = (readaddr >> 16) & 0xff, |
| 60 | cmd[2] = (readaddr >> 8) & 0xff, |
| 61 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 62 | ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, |
| 63 | cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 64 | } |
| 65 | if (ret) |
| 66 | return ret; |
Cristian Măgherușan-Stanciu | 9932c7b | 2011-07-07 19:56:58 +0000 | [diff] [blame] | 67 | msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 68 | return 0; |
| 69 | } |
| 70 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 71 | static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 72 | { |
| 73 | unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; |
| 74 | uint32_t readaddr; |
| 75 | int ret; |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 76 | int i; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 77 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 78 | ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 79 | if (ret == SPI_INVALID_ADDRESS) { |
| 80 | /* Find the lowest even address allowed for reads. */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 81 | readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 82 | cmd[1] = (readaddr >> 16) & 0xff, |
| 83 | cmd[2] = (readaddr >> 8) & 0xff, |
| 84 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 85 | ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 86 | } |
| 87 | if (ret) |
| 88 | return ret; |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 89 | msg_cspew("RES returned"); |
| 90 | for (i = 0; i < bytes; i++) |
| 91 | msg_cspew(" 0x%02x", readarr[i]); |
| 92 | msg_cspew(". "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 93 | return 0; |
| 94 | } |
| 95 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 96 | int spi_write_enable(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 97 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 98 | static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 99 | int result; |
| 100 | |
| 101 | /* Send WREN (Write Enable) */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 102 | result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 103 | |
| 104 | if (result) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 105 | msg_cerr("%s failed\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 106 | |
| 107 | return result; |
| 108 | } |
| 109 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 110 | int spi_write_disable(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 111 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 112 | static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 113 | |
| 114 | /* Send WRDI (Write Disable) */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 115 | return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 118 | static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 119 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 120 | const struct flashchip *chip = flash->chip; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 121 | unsigned char readarr[4]; |
| 122 | uint32_t id1; |
| 123 | uint32_t id2; |
| 124 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 125 | if (spi_rdid(flash, readarr, bytes)) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 126 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 127 | } |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 128 | |
| 129 | if (!oddparity(readarr[0])) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 130 | msg_cdbg("RDID byte 0 parity violation. "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 131 | |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 132 | /* Check if this is a continuation vendor ID. |
| 133 | * FIXME: Handle continuation device IDs. |
| 134 | */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 135 | if (readarr[0] == 0x7f) { |
| 136 | if (!oddparity(readarr[1])) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 137 | msg_cdbg("RDID byte 1 parity violation. "); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 138 | id1 = (readarr[0] << 8) | readarr[1]; |
| 139 | id2 = readarr[2]; |
| 140 | if (bytes > 3) { |
| 141 | id2 <<= 8; |
| 142 | id2 |= readarr[3]; |
| 143 | } |
| 144 | } else { |
| 145 | id1 = readarr[0]; |
| 146 | id2 = (readarr[1] << 8) | readarr[2]; |
| 147 | } |
| 148 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 149 | msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 150 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame^] | 151 | if (id1 == chip->manufacture_id && id2 == chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 152 | return 1; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 153 | |
| 154 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 155 | if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 156 | return 1; |
| 157 | |
| 158 | /* Test if there is any vendor ID. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 159 | if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 160 | return 1; |
| 161 | |
| 162 | return 0; |
| 163 | } |
| 164 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 165 | int probe_spi_rdid(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 166 | { |
| 167 | return probe_spi_rdid_generic(flash, 3); |
| 168 | } |
| 169 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 170 | int probe_spi_rdid4(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 171 | { |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 172 | /* Some SPI controllers do not support commands with writecnt=1 and |
| 173 | * readcnt=4. |
| 174 | */ |
Carl-Daniel Hailfinger | c40cff7 | 2011-12-20 00:19:29 +0000 | [diff] [blame] | 175 | switch (flash->pgm->spi.type) { |
Carl-Daniel Hailfinger | 7112772 | 2010-05-31 15:27:27 +0000 | [diff] [blame] | 176 | #if CONFIG_INTERNAL == 1 |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 177 | #if defined(__i386__) || defined(__x86_64__) |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 178 | case SPI_CONTROLLER_IT87XX: |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 179 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 180 | msg_cinfo("4 byte RDID not supported on this SPI controller\n"); |
| 181 | return 0; |
| 182 | break; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 183 | #endif |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 184 | #endif |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 185 | default: |
Carl-Daniel Hailfinger | 8ae500e | 2010-06-20 10:39:33 +0000 | [diff] [blame] | 186 | return probe_spi_rdid_generic(flash, 4); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 192 | int probe_spi_rems(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 193 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 194 | const struct flashchip *chip = flash->chip; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 195 | unsigned char readarr[JEDEC_REMS_INSIZE]; |
| 196 | uint32_t id1, id2; |
| 197 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 198 | if (spi_rems(flash, readarr)) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 199 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 200 | } |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 201 | |
| 202 | id1 = readarr[0]; |
| 203 | id2 = readarr[1]; |
| 204 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 205 | msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 206 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame^] | 207 | if (id1 == chip->manufacture_id && id2 == chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 208 | return 1; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 209 | |
| 210 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 211 | if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 212 | return 1; |
| 213 | |
| 214 | /* Test if there is any vendor ID. */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 215 | if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 216 | return 1; |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 221 | int probe_spi_res1(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 222 | { |
Mathias Krause | a60faab | 2011-01-17 07:50:42 +0000 | [diff] [blame] | 223 | static const unsigned char allff[] = {0xff, 0xff, 0xff}; |
| 224 | static const unsigned char all00[] = {0x00, 0x00, 0x00}; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 225 | unsigned char readarr[3]; |
| 226 | uint32_t id2; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 227 | |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 228 | /* We only want one-byte RES if RDID and REMS are unusable. */ |
| 229 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 230 | /* Check if RDID is usable and does not return 0xff 0xff 0xff or |
| 231 | * 0x00 0x00 0x00. In that case, RES is pointless. |
| 232 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 233 | if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) && |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 234 | memcmp(readarr, all00, 3)) { |
| 235 | msg_cdbg("Ignoring RES in favour of RDID.\n"); |
| 236 | return 0; |
| 237 | } |
| 238 | /* Check if REMS is usable and does not return 0xff 0xff or |
| 239 | * 0x00 0x00. In that case, RES is pointless. |
| 240 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 241 | if (!spi_rems(flash, readarr) && |
| 242 | memcmp(readarr, allff, JEDEC_REMS_INSIZE) && |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 243 | memcmp(readarr, all00, JEDEC_REMS_INSIZE)) { |
| 244 | msg_cdbg("Ignoring RES in favour of REMS.\n"); |
| 245 | return 0; |
| 246 | } |
| 247 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 248 | if (spi_res(flash, readarr, 1)) { |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 249 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 250 | } |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 251 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 252 | id2 = readarr[0]; |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 253 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 254 | msg_cdbg("%s: id 0x%x\n", __func__, id2); |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 255 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 256 | if (id2 != flash->chip->model_id) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 257 | return 0; |
| 258 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 259 | return 1; |
| 260 | } |
| 261 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 262 | int probe_spi_res2(struct flashctx *flash) |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 263 | { |
| 264 | unsigned char readarr[2]; |
| 265 | uint32_t id1, id2; |
| 266 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 267 | if (spi_res(flash, readarr, 2)) { |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 268 | return 0; |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 269 | } |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 270 | |
| 271 | id1 = readarr[0]; |
| 272 | id2 = readarr[1]; |
| 273 | |
| 274 | msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); |
| 275 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 276 | if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 277 | return 0; |
| 278 | |
Carl-Daniel Hailfinger | dc1cda1 | 2010-05-28 17:07:57 +0000 | [diff] [blame] | 279 | return 1; |
| 280 | } |
| 281 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 282 | int spi_chip_erase_60(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 283 | { |
| 284 | int result; |
| 285 | struct spi_command cmds[] = { |
| 286 | { |
| 287 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 288 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 289 | .readcnt = 0, |
| 290 | .readarr = NULL, |
| 291 | }, { |
| 292 | .writecnt = JEDEC_CE_60_OUTSIZE, |
| 293 | .writearr = (const unsigned char[]){ JEDEC_CE_60 }, |
| 294 | .readcnt = 0, |
| 295 | .readarr = NULL, |
| 296 | }, { |
| 297 | .writecnt = 0, |
| 298 | .writearr = NULL, |
| 299 | .readcnt = 0, |
| 300 | .readarr = NULL, |
| 301 | }}; |
| 302 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 303 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 304 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 305 | msg_cerr("%s failed during command execution\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 306 | __func__); |
| 307 | return result; |
| 308 | } |
| 309 | /* Wait until the Write-In-Progress bit is cleared. |
| 310 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 311 | */ |
| 312 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 313 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 314 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 315 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 316 | return 0; |
| 317 | } |
| 318 | |
Stefan Tauner | 3c0fcd0 | 2012-09-21 12:46:56 +0000 | [diff] [blame] | 319 | int spi_chip_erase_62(struct flashctx *flash) |
| 320 | { |
| 321 | int result; |
| 322 | struct spi_command cmds[] = { |
| 323 | { |
| 324 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 325 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 326 | .readcnt = 0, |
| 327 | .readarr = NULL, |
| 328 | }, { |
| 329 | .writecnt = JEDEC_CE_62_OUTSIZE, |
| 330 | .writearr = (const unsigned char[]){ JEDEC_CE_62 }, |
| 331 | .readcnt = 0, |
| 332 | .readarr = NULL, |
| 333 | }, { |
| 334 | .writecnt = 0, |
| 335 | .writearr = NULL, |
| 336 | .readcnt = 0, |
| 337 | .readarr = NULL, |
| 338 | }}; |
| 339 | |
| 340 | result = spi_send_multicommand(flash, cmds); |
| 341 | if (result) { |
| 342 | msg_cerr("%s failed during command execution\n", |
| 343 | __func__); |
| 344 | return result; |
| 345 | } |
| 346 | /* Wait until the Write-In-Progress bit is cleared. |
| 347 | * This usually takes 2-5 s, so wait in 100 ms steps. |
| 348 | */ |
| 349 | /* FIXME: We assume spi_read_status_register will never fail. */ |
| 350 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
| 351 | programmer_delay(100 * 1000); |
| 352 | /* FIXME: Check the status register for errors. */ |
| 353 | return 0; |
| 354 | } |
| 355 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 356 | int spi_chip_erase_c7(struct flashctx *flash) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 357 | { |
| 358 | int result; |
| 359 | struct spi_command cmds[] = { |
| 360 | { |
| 361 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 362 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 363 | .readcnt = 0, |
| 364 | .readarr = NULL, |
| 365 | }, { |
| 366 | .writecnt = JEDEC_CE_C7_OUTSIZE, |
| 367 | .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, |
| 368 | .readcnt = 0, |
| 369 | .readarr = NULL, |
| 370 | }, { |
| 371 | .writecnt = 0, |
| 372 | .writearr = NULL, |
| 373 | .readcnt = 0, |
| 374 | .readarr = NULL, |
| 375 | }}; |
| 376 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 377 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 378 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 379 | msg_cerr("%s failed during command execution\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 380 | return result; |
| 381 | } |
| 382 | /* Wait until the Write-In-Progress bit is cleared. |
| 383 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 384 | */ |
| 385 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 386 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 387 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 388 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 389 | return 0; |
| 390 | } |
| 391 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 392 | int spi_block_erase_52(struct flashctx *flash, unsigned int addr, |
| 393 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 394 | { |
| 395 | int result; |
| 396 | struct spi_command cmds[] = { |
| 397 | { |
| 398 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 399 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 400 | .readcnt = 0, |
| 401 | .readarr = NULL, |
| 402 | }, { |
| 403 | .writecnt = JEDEC_BE_52_OUTSIZE, |
| 404 | .writearr = (const unsigned char[]){ |
| 405 | JEDEC_BE_52, |
| 406 | (addr >> 16) & 0xff, |
| 407 | (addr >> 8) & 0xff, |
| 408 | (addr & 0xff) |
| 409 | }, |
| 410 | .readcnt = 0, |
| 411 | .readarr = NULL, |
| 412 | }, { |
| 413 | .writecnt = 0, |
| 414 | .writearr = NULL, |
| 415 | .readcnt = 0, |
| 416 | .readarr = NULL, |
| 417 | }}; |
| 418 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 419 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 420 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 421 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 422 | __func__, addr); |
| 423 | return result; |
| 424 | } |
| 425 | /* Wait until the Write-In-Progress bit is cleared. |
| 426 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 427 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 428 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 429 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 430 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 431 | return 0; |
| 432 | } |
| 433 | |
| 434 | /* Block size is usually |
| 435 | * 64k for Macronix |
| 436 | * 32k for SST |
| 437 | * 4-32k non-uniform for EON |
| 438 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 439 | int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, |
| 440 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 441 | { |
| 442 | int result; |
| 443 | struct spi_command cmds[] = { |
| 444 | { |
| 445 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 446 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 447 | .readcnt = 0, |
| 448 | .readarr = NULL, |
| 449 | }, { |
| 450 | .writecnt = JEDEC_BE_D8_OUTSIZE, |
| 451 | .writearr = (const unsigned char[]){ |
| 452 | JEDEC_BE_D8, |
| 453 | (addr >> 16) & 0xff, |
| 454 | (addr >> 8) & 0xff, |
| 455 | (addr & 0xff) |
| 456 | }, |
| 457 | .readcnt = 0, |
| 458 | .readarr = NULL, |
| 459 | }, { |
| 460 | .writecnt = 0, |
| 461 | .writearr = NULL, |
| 462 | .readcnt = 0, |
| 463 | .readarr = NULL, |
| 464 | }}; |
| 465 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 466 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 467 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 468 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 469 | __func__, addr); |
| 470 | return result; |
| 471 | } |
| 472 | /* Wait until the Write-In-Progress bit is cleared. |
| 473 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 474 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 475 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 476 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 477 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 478 | return 0; |
| 479 | } |
| 480 | |
| 481 | /* Block size is usually |
| 482 | * 4k for PMC |
| 483 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 484 | int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, |
| 485 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 486 | { |
| 487 | int result; |
| 488 | struct spi_command cmds[] = { |
| 489 | { |
| 490 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 491 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 492 | .readcnt = 0, |
| 493 | .readarr = NULL, |
| 494 | }, { |
| 495 | .writecnt = JEDEC_BE_D7_OUTSIZE, |
| 496 | .writearr = (const unsigned char[]){ |
| 497 | JEDEC_BE_D7, |
| 498 | (addr >> 16) & 0xff, |
| 499 | (addr >> 8) & 0xff, |
| 500 | (addr & 0xff) |
| 501 | }, |
| 502 | .readcnt = 0, |
| 503 | .readarr = NULL, |
| 504 | }, { |
| 505 | .writecnt = 0, |
| 506 | .writearr = NULL, |
| 507 | .readcnt = 0, |
| 508 | .readarr = NULL, |
| 509 | }}; |
| 510 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 511 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 512 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 513 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 514 | __func__, addr); |
| 515 | return result; |
| 516 | } |
| 517 | /* Wait until the Write-In-Progress bit is cleared. |
| 518 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 519 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 520 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 521 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 522 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 523 | return 0; |
| 524 | } |
| 525 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 526 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 527 | int spi_block_erase_20(struct flashctx *flash, unsigned int addr, |
| 528 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 529 | { |
| 530 | int result; |
| 531 | struct spi_command cmds[] = { |
| 532 | { |
| 533 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 534 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 535 | .readcnt = 0, |
| 536 | .readarr = NULL, |
| 537 | }, { |
| 538 | .writecnt = JEDEC_SE_OUTSIZE, |
| 539 | .writearr = (const unsigned char[]){ |
| 540 | JEDEC_SE, |
| 541 | (addr >> 16) & 0xff, |
| 542 | (addr >> 8) & 0xff, |
| 543 | (addr & 0xff) |
| 544 | }, |
| 545 | .readcnt = 0, |
| 546 | .readarr = NULL, |
| 547 | }, { |
| 548 | .writecnt = 0, |
| 549 | .writearr = NULL, |
| 550 | .readcnt = 0, |
| 551 | .readarr = NULL, |
| 552 | }}; |
| 553 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 554 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 555 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 556 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 557 | __func__, addr); |
| 558 | return result; |
| 559 | } |
| 560 | /* Wait until the Write-In-Progress bit is cleared. |
| 561 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 562 | */ |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 563 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 564 | programmer_delay(10 * 1000); |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 565 | /* FIXME: Check the status register for errors. */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 566 | return 0; |
| 567 | } |
| 568 | |
Stefan Tauner | 94b39b4 | 2012-10-27 00:06:02 +0000 | [diff] [blame] | 569 | int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) |
| 570 | { |
| 571 | int result; |
| 572 | struct spi_command cmds[] = { |
| 573 | { |
| 574 | /* .writecnt = JEDEC_WREN_OUTSIZE, |
| 575 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 576 | .readcnt = 0, |
| 577 | .readarr = NULL, |
| 578 | }, { */ |
| 579 | .writecnt = JEDEC_BE_50_OUTSIZE, |
| 580 | .writearr = (const unsigned char[]){ |
| 581 | JEDEC_BE_50, |
| 582 | (addr >> 16) & 0xff, |
| 583 | (addr >> 8) & 0xff, |
| 584 | (addr & 0xff) |
| 585 | }, |
| 586 | .readcnt = 0, |
| 587 | .readarr = NULL, |
| 588 | }, { |
| 589 | .writecnt = 0, |
| 590 | .writearr = NULL, |
| 591 | .readcnt = 0, |
| 592 | .readarr = NULL, |
| 593 | }}; |
| 594 | |
| 595 | result = spi_send_multicommand(flash, cmds); |
| 596 | if (result) { |
| 597 | msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); |
| 598 | return result; |
| 599 | } |
| 600 | /* Wait until the Write-In-Progress bit is cleared. |
| 601 | * This usually takes 10 ms, so wait in 1 ms steps. |
| 602 | */ |
| 603 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
| 604 | programmer_delay(1 * 1000); |
| 605 | /* FIXME: Check the status register for errors. */ |
| 606 | return 0; |
| 607 | } |
| 608 | |
| 609 | int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) |
| 610 | { |
| 611 | int result; |
| 612 | struct spi_command cmds[] = { |
| 613 | { |
| 614 | /* .writecnt = JEDEC_WREN_OUTSIZE, |
| 615 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 616 | .readcnt = 0, |
| 617 | .readarr = NULL, |
| 618 | }, { */ |
| 619 | .writecnt = JEDEC_BE_81_OUTSIZE, |
| 620 | .writearr = (const unsigned char[]){ |
| 621 | JEDEC_BE_81, |
| 622 | (addr >> 16) & 0xff, |
| 623 | (addr >> 8) & 0xff, |
| 624 | (addr & 0xff) |
| 625 | }, |
| 626 | .readcnt = 0, |
| 627 | .readarr = NULL, |
| 628 | }, { |
| 629 | .writecnt = 0, |
| 630 | .writearr = NULL, |
| 631 | .readcnt = 0, |
| 632 | .readarr = NULL, |
| 633 | }}; |
| 634 | |
| 635 | result = spi_send_multicommand(flash, cmds); |
| 636 | if (result) { |
| 637 | msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); |
| 638 | return result; |
| 639 | } |
| 640 | /* Wait until the Write-In-Progress bit is cleared. |
| 641 | * This usually takes 8 ms, so wait in 1 ms steps. |
| 642 | */ |
| 643 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
| 644 | programmer_delay(1 * 1000); |
| 645 | /* FIXME: Check the status register for errors. */ |
| 646 | return 0; |
| 647 | } |
| 648 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 649 | int spi_block_erase_60(struct flashctx *flash, unsigned int addr, |
| 650 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 651 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 652 | if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 653 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 654 | __func__); |
| 655 | return -1; |
| 656 | } |
| 657 | return spi_chip_erase_60(flash); |
| 658 | } |
| 659 | |
Stefan Tauner | 3c0fcd0 | 2012-09-21 12:46:56 +0000 | [diff] [blame] | 660 | int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen) |
| 661 | { |
| 662 | if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) { |
| 663 | msg_cerr("%s called with incorrect arguments\n", |
| 664 | __func__); |
| 665 | return -1; |
| 666 | } |
| 667 | return spi_chip_erase_62(flash); |
| 668 | } |
| 669 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 670 | int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, |
| 671 | unsigned int blocklen) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 672 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 673 | if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 674 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 675 | __func__); |
| 676 | return -1; |
| 677 | } |
| 678 | return spi_chip_erase_c7(flash); |
| 679 | } |
| 680 | |
Stefan Tauner | ac1b4c8 | 2012-02-17 14:51:04 +0000 | [diff] [blame] | 681 | erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) |
| 682 | { |
| 683 | switch(opcode){ |
| 684 | case 0xff: |
| 685 | case 0x00: |
| 686 | /* Not specified, assuming "not supported". */ |
| 687 | return NULL; |
| 688 | case 0x20: |
| 689 | return &spi_block_erase_20; |
| 690 | case 0x52: |
| 691 | return &spi_block_erase_52; |
| 692 | case 0x60: |
| 693 | return &spi_block_erase_60; |
| 694 | case 0xc7: |
| 695 | return &spi_block_erase_c7; |
| 696 | case 0xd7: |
| 697 | return &spi_block_erase_d7; |
| 698 | case 0xd8: |
| 699 | return &spi_block_erase_d8; |
| 700 | default: |
| 701 | msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " |
| 702 | "this at flashrom@flashrom.org\n", __func__, opcode); |
| 703 | return NULL; |
| 704 | } |
| 705 | } |
| 706 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 707 | int spi_byte_program(struct flashctx *flash, unsigned int addr, |
| 708 | uint8_t databyte) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 709 | { |
| 710 | int result; |
| 711 | struct spi_command cmds[] = { |
| 712 | { |
| 713 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 714 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 715 | .readcnt = 0, |
| 716 | .readarr = NULL, |
| 717 | }, { |
| 718 | .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, |
| 719 | .writearr = (const unsigned char[]){ |
| 720 | JEDEC_BYTE_PROGRAM, |
| 721 | (addr >> 16) & 0xff, |
| 722 | (addr >> 8) & 0xff, |
| 723 | (addr & 0xff), |
| 724 | databyte |
| 725 | }, |
| 726 | .readcnt = 0, |
| 727 | .readarr = NULL, |
| 728 | }, { |
| 729 | .writecnt = 0, |
| 730 | .writearr = NULL, |
| 731 | .readcnt = 0, |
| 732 | .readarr = NULL, |
| 733 | }}; |
| 734 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 735 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 736 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 737 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 738 | __func__, addr); |
| 739 | } |
| 740 | return result; |
| 741 | } |
| 742 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 743 | int spi_nbyte_program(struct flashctx *flash, unsigned int addr, uint8_t *bytes, |
| 744 | unsigned int len) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 745 | { |
| 746 | int result; |
| 747 | /* FIXME: Switch to malloc based on len unless that kills speed. */ |
| 748 | unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { |
| 749 | JEDEC_BYTE_PROGRAM, |
| 750 | (addr >> 16) & 0xff, |
| 751 | (addr >> 8) & 0xff, |
| 752 | (addr >> 0) & 0xff, |
| 753 | }; |
| 754 | struct spi_command cmds[] = { |
| 755 | { |
| 756 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 757 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 758 | .readcnt = 0, |
| 759 | .readarr = NULL, |
| 760 | }, { |
| 761 | .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, |
| 762 | .writearr = cmd, |
| 763 | .readcnt = 0, |
| 764 | .readarr = NULL, |
| 765 | }, { |
| 766 | .writecnt = 0, |
| 767 | .writearr = NULL, |
| 768 | .readcnt = 0, |
| 769 | .readarr = NULL, |
| 770 | }}; |
| 771 | |
| 772 | if (!len) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 773 | msg_cerr("%s called for zero-length write\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 774 | return 1; |
| 775 | } |
| 776 | if (len > 256) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 777 | msg_cerr("%s called for too long a write\n", __func__); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 778 | return 1; |
| 779 | } |
| 780 | |
| 781 | memcpy(&cmd[4], bytes, len); |
| 782 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 783 | result = spi_send_multicommand(flash, cmds); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 784 | if (result) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 785 | msg_cerr("%s failed during command execution at address 0x%x\n", |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 786 | __func__, addr); |
| 787 | } |
| 788 | return result; |
| 789 | } |
| 790 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 791 | int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, |
| 792 | unsigned int len) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 793 | { |
| 794 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = { |
| 795 | JEDEC_READ, |
| 796 | (address >> 16) & 0xff, |
| 797 | (address >> 8) & 0xff, |
| 798 | (address >> 0) & 0xff, |
| 799 | }; |
| 800 | |
| 801 | /* Send Read */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 802 | return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 803 | } |
| 804 | |
| 805 | /* |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 806 | * Read a part of the flash chip. |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 807 | * FIXME: Use the chunk code from Michael Karcher instead. |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 808 | * Each page is read separately in chunks with a maximum size of chunksize. |
| 809 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 810 | int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 811 | unsigned int len, unsigned int chunksize) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 812 | { |
| 813 | int rc = 0; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 814 | unsigned int i, j, starthere, lenhere, toread; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 815 | unsigned int page_size = flash->chip->page_size; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 816 | |
| 817 | /* Warning: This loop has a very unusual condition and body. |
| 818 | * The loop needs to go through each page with at least one affected |
| 819 | * byte. The lowest page number is (start / page_size) since that |
| 820 | * division rounds down. The highest page number we want is the page |
| 821 | * where the last byte of the range lives. That last byte has the |
| 822 | * address (start + len - 1), thus the highest page number is |
| 823 | * (start + len - 1) / page_size. Since we want to include that last |
| 824 | * page as well, the loop condition uses <=. |
| 825 | */ |
| 826 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 827 | /* Byte position of the first byte in the range in this page. */ |
| 828 | /* starthere is an offset to the base address of the chip. */ |
| 829 | starthere = max(start, i * page_size); |
| 830 | /* Length of bytes in the range in this page. */ |
| 831 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
| 832 | for (j = 0; j < lenhere; j += chunksize) { |
| 833 | toread = min(chunksize, lenhere - j); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 834 | rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 835 | if (rc) |
| 836 | break; |
| 837 | } |
| 838 | if (rc) |
| 839 | break; |
| 840 | } |
| 841 | |
| 842 | return rc; |
| 843 | } |
| 844 | |
| 845 | /* |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 846 | * Write a part of the flash chip. |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 847 | * FIXME: Use the chunk code from Michael Karcher instead. |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 848 | * Each page is written separately in chunks with a maximum size of chunksize. |
| 849 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 850 | int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 851 | unsigned int len, unsigned int chunksize) |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 852 | { |
| 853 | int rc = 0; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 854 | unsigned int i, j, starthere, lenhere, towrite; |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 855 | /* FIXME: page_size is the wrong variable. We need max_writechunk_size |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 856 | * in struct flashctx to do this properly. All chips using |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 857 | * spi_chip_write_256 have page_size set to max_writechunk_size, so |
| 858 | * we're OK for now. |
| 859 | */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 860 | unsigned int page_size = flash->chip->page_size; |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 861 | |
| 862 | /* Warning: This loop has a very unusual condition and body. |
| 863 | * The loop needs to go through each page with at least one affected |
| 864 | * byte. The lowest page number is (start / page_size) since that |
| 865 | * division rounds down. The highest page number we want is the page |
| 866 | * where the last byte of the range lives. That last byte has the |
| 867 | * address (start + len - 1), thus the highest page number is |
| 868 | * (start + len - 1) / page_size. Since we want to include that last |
| 869 | * page as well, the loop condition uses <=. |
| 870 | */ |
| 871 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 872 | /* Byte position of the first byte in the range in this page. */ |
| 873 | /* starthere is an offset to the base address of the chip. */ |
| 874 | starthere = max(start, i * page_size); |
| 875 | /* Length of bytes in the range in this page. */ |
| 876 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
| 877 | for (j = 0; j < lenhere; j += chunksize) { |
| 878 | towrite = min(chunksize, lenhere - j); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 879 | rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 880 | if (rc) |
| 881 | break; |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 882 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 883 | programmer_delay(10); |
| 884 | } |
| 885 | if (rc) |
| 886 | break; |
| 887 | } |
| 888 | |
| 889 | return rc; |
| 890 | } |
| 891 | |
| 892 | /* |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 893 | * Program chip using byte programming. (SLOW!) |
| 894 | * This is for chips which can only handle one byte writes |
| 895 | * and for chips where memory mapped programming is impossible |
| 896 | * (e.g. due to size constraints in IT87* for over 512 kB) |
| 897 | */ |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 898 | /* real chunksize is 1, logical chunksize is 1 */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 899 | int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 900 | unsigned int len) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 901 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 902 | unsigned int i; |
| 903 | int result = 0; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 904 | |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 905 | for (i = start; i < start + len; i++) { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 906 | result = spi_byte_program(flash, i, buf[i - start]); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 907 | if (result) |
| 908 | return 1; |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 909 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 910 | programmer_delay(10); |
| 911 | } |
| 912 | |
| 913 | return 0; |
| 914 | } |
| 915 | |
Nico Huber | 7bca126 | 2012-06-15 22:28:12 +0000 | [diff] [blame] | 916 | int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 917 | { |
| 918 | uint32_t pos = start; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 919 | int result; |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 920 | unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { |
| 921 | JEDEC_AAI_WORD_PROGRAM, |
| 922 | }; |
| 923 | struct spi_command cmds[] = { |
| 924 | { |
| 925 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 926 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 927 | .readcnt = 0, |
| 928 | .readarr = NULL, |
| 929 | }, { |
| 930 | .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, |
| 931 | .writearr = (const unsigned char[]){ |
| 932 | JEDEC_AAI_WORD_PROGRAM, |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 933 | (start >> 16) & 0xff, |
| 934 | (start >> 8) & 0xff, |
| 935 | (start & 0xff), |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 936 | buf[0], |
| 937 | buf[1] |
| 938 | }, |
| 939 | .readcnt = 0, |
| 940 | .readarr = NULL, |
| 941 | }, { |
| 942 | .writecnt = 0, |
| 943 | .writearr = NULL, |
| 944 | .readcnt = 0, |
| 945 | .readarr = NULL, |
| 946 | }}; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 947 | |
Carl-Daniel Hailfinger | c40cff7 | 2011-12-20 00:19:29 +0000 | [diff] [blame] | 948 | switch (flash->pgm->spi.type) { |
Carl-Daniel Hailfinger | 7112772 | 2010-05-31 15:27:27 +0000 | [diff] [blame] | 949 | #if CONFIG_INTERNAL == 1 |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 950 | #if defined(__i386__) || defined(__x86_64__) |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 951 | case SPI_CONTROLLER_IT87XX: |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 952 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 953 | msg_perr("%s: impossible with this SPI controller," |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 954 | " degrading to byte program\n", __func__); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 955 | return spi_chip_write_1(flash, buf, start, len); |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 956 | #endif |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 957 | #endif |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 958 | default: |
| 959 | break; |
| 960 | } |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 961 | |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 962 | /* The even start address and even length requirements can be either |
| 963 | * honored outside this function, or we can call spi_byte_program |
| 964 | * for the first and/or last byte and use AAI for the rest. |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 965 | * FIXME: Move this to generic code. |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 966 | */ |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 967 | /* The data sheet requires a start address with the low bit cleared. */ |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 968 | if (start % 2) { |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 969 | msg_cerr("%s: start address not even! Please report a bug at " |
| 970 | "flashrom@flashrom.org\n", __func__); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 971 | if (spi_chip_write_1(flash, buf, start, start % 2)) |
| 972 | return SPI_GENERIC_ERROR; |
| 973 | pos += start % 2; |
Carl-Daniel Hailfinger | ccfe0ac | 2010-10-27 22:07:11 +0000 | [diff] [blame] | 974 | cmds[1].writearr = (const unsigned char[]){ |
| 975 | JEDEC_AAI_WORD_PROGRAM, |
| 976 | (pos >> 16) & 0xff, |
| 977 | (pos >> 8) & 0xff, |
| 978 | (pos & 0xff), |
| 979 | buf[pos - start], |
| 980 | buf[pos - start + 1] |
| 981 | }; |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 982 | /* Do not return an error for now. */ |
| 983 | //return SPI_GENERIC_ERROR; |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 984 | } |
| 985 | /* The data sheet requires total AAI write length to be even. */ |
| 986 | if (len % 2) { |
| 987 | msg_cerr("%s: total write length not even! Please report a " |
| 988 | "bug at flashrom@flashrom.org\n", __func__); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 989 | /* Do not return an error for now. */ |
| 990 | //return SPI_GENERIC_ERROR; |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 991 | } |
| 992 | |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 993 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 994 | result = spi_send_multicommand(flash, cmds); |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 995 | if (result) { |
| 996 | msg_cerr("%s failed during start command execution\n", |
| 997 | __func__); |
Carl-Daniel Hailfinger | 9a795d8 | 2010-07-14 16:19:05 +0000 | [diff] [blame] | 998 | /* FIXME: Should we send WRDI here as well to make sure the chip |
| 999 | * is not in AAI mode? |
| 1000 | */ |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1001 | return result; |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1002 | } |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 1003 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1004 | programmer_delay(10); |
| 1005 | |
| 1006 | /* We already wrote 2 bytes in the multicommand step. */ |
| 1007 | pos += 2; |
| 1008 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1009 | /* Are there at least two more bytes to write? */ |
| 1010 | while (pos < start + len - 1) { |
Carl-Daniel Hailfinger | ccfe0ac | 2010-10-27 22:07:11 +0000 | [diff] [blame] | 1011 | cmd[1] = buf[pos++ - start]; |
| 1012 | cmd[2] = buf[pos++ - start]; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1013 | spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, |
| 1014 | cmd, NULL); |
Stefan Tauner | 5e695ab | 2012-05-06 17:03:40 +0000 | [diff] [blame] | 1015 | while (spi_read_status_register(flash) & SPI_SR_WIP) |
Carl-Daniel Hailfinger | 9c62d11 | 2010-06-20 10:41:35 +0000 | [diff] [blame] | 1016 | programmer_delay(10); |
| 1017 | } |
| 1018 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1019 | /* Use WRDI to exit AAI mode. This needs to be done before issuing any |
| 1020 | * other non-AAI command. |
| 1021 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1022 | spi_write_disable(flash); |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1023 | |
| 1024 | /* Write remaining byte (if any). */ |
| 1025 | if (pos < start + len) { |
Carl-Daniel Hailfinger | ccfe0ac | 2010-10-27 22:07:11 +0000 | [diff] [blame] | 1026 | if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2)) |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 1027 | return SPI_GENERIC_ERROR; |
| 1028 | pos += pos % 2; |
| 1029 | } |
| 1030 | |
Sean Nelson | 14ba668 | 2010-02-26 05:48:29 +0000 | [diff] [blame] | 1031 | return 0; |
| 1032 | } |