flashchips: Add Spansion 25FL256S......0
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/spi25.c b/spi25.c
index c403570..3b5e50e 100644
--- a/spi25.c
+++ b/spi25.c
@@ -341,13 +341,14 @@
static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata)
{
+ const uint8_t op = flash->chip->wrea_override ? : JEDEC_WRITE_EXT_ADDR_REG;
struct spi_command cmds[] = {
{
.writecnt = 1,
.writearr = (const unsigned char[]){ JEDEC_WREN },
}, {
.writecnt = 2,
- .writearr = (const unsigned char[]){ JEDEC_WRITE_EXT_ADDR_REG, regdata },
+ .writearr = (const unsigned char[]){ op, regdata },
},
NULL_SPI_CMD,
};