blob: 769b4022769dcde848884680692f433676ce128c [file] [log] [blame]
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Uwe Hermannffec5f32007-08-23 16:08:21 +000069/**
70 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000071 *
72 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +000073 * - Agami Aruma
74 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000075 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000076static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000077{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000078 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000079
Uwe Hermann372eeb52007-12-04 21:49:06 +000080 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000081 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000082 fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000083 name, sio_read(port, 0x20));
84 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000085 return -1;
86 }
87
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000088 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000089 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000090
Uwe Hermann372eeb52007-12-04 21:49:06 +000091 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000092 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000093
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000094 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
95 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
96 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
97 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000098
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000099 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000100
101 return 0;
102}
103
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000104static int w83627hf_gpio24_raise_2e(const char *name)
105{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000106 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000107}
108
109/**
110 * Winbond W83627THF: GPIO 4, bit 4
111 *
112 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000113 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000114 * - MSI K8N-NEO3
115 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000116static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000117{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000119
120 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000122 fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 name, sio_read(port, 0x20));
124 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000125 return -1;
126 }
127
128 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
129
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000130 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
131 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
132 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
133 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
134 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000135
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000136 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000137
138 return 0;
139}
140
Peter Stugecce26822008-07-21 17:48:40 +0000141static int w83627thf_gpio4_4_raise_2e(const char *name)
142{
143 return w83627thf_gpio4_4_raise(0x2e, name);
144}
145
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146static int w83627thf_gpio4_4_raise_4e(const char *name)
147{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000149}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000150
Uwe Hermannffec5f32007-08-23 16:08:21 +0000151/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000152 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000153 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000154static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000155{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000156 w836xx_ext_enter(port);
157 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000158 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000160 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000161 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000162}
163
164/**
165 * Common routine for several VT823x based boards.
166 */
167static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev)
168{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000169 uint8_t val;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000170
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000171 /* All memory cycles, not just ROM ones, go to LPC. */
172 val = pci_read_byte(dev, 0x59);
173 val &= ~0x80;
174 pci_write_byte(dev, 0x59, val);
175}
176
177/**
178 * VT823x: Set one of the GPIO pins.
179 */
180static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise)
181{
182 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000183 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000184
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000185 if ((gpio >= 12) && (gpio <= 15)) {
186 /* GPIO12-15 -> output */
187 val = pci_read_byte(dev, 0xE4);
188 val |= 0x10;
189 pci_write_byte(dev, 0xE4, val);
190 } else if (gpio == 9) {
191 /* GPIO9 -> Output */
192 val = pci_read_byte(dev, 0xE4);
193 val |= 0x20;
194 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000195 } else if (gpio == 5) {
196 val = pci_read_byte(dev, 0xE4);
197 val |= 0x01;
198 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000199 } else {
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000200 fprintf(stderr, "\nERROR: "
201 "VT823x GPIO%02d is not implemented.\n", gpio);
202 return;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000203 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000204
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000205 /* We need the I/O Base Address for this board's flash enable. */
206 base = pci_read_word(dev, 0x88) & 0xff80;
207
David Bartleyf58d3642009-12-09 07:53:01 +0000208 offset = 0x4C + gpio / 8;
209 bit = 0x01 << (gpio % 8);
210
211 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000212 if (raise)
213 val |= bit;
214 else
215 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000216 OUTB(val, base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000217}
218
219/**
220 * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
221 *
222 * We don't need to do this when using coreboot, GPIO15 is never lowered there.
223 */
224static int board_via_epia_m(const char *name)
225{
226 struct pci_dev *dev;
227
228 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
229 if (!dev) {
230 fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n");
231 return -1;
232 }
233
234 /* GPIO15 is connected to write protect. */
235 vt823x_gpio_set(dev, 15, 1);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000236
Uwe Hermanna7e05482007-05-09 10:17:44 +0000237 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000238}
239
Uwe Hermannffec5f32007-08-23 16:08:21 +0000240/**
Luc Verhaegen32707542007-07-04 17:51:49 +0000241 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000242 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
Uwe Hermann5e1aecd2009-05-18 21:56:16 +0000243 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000244 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000245static int board_asus_a7v8x_mx(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000246{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000247 struct pci_dev *dev;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000248
Uwe Hermanna7e05482007-05-09 10:17:44 +0000249 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
Luc Verhaegen32707542007-07-04 17:51:49 +0000250 if (!dev)
251 dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000252 if (!dev) {
Luc Verhaegen32707542007-07-04 17:51:49 +0000253 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000254 return -1;
255 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000256
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000257 vt823x_set_all_writes_to_lpc(dev);
258 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000259
Uwe Hermanna7e05482007-05-09 10:17:44 +0000260 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000261}
262
Uwe Hermannffec5f32007-08-23 16:08:21 +0000263/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000264 * Suited for VIAs EPIA SP and EPIA CN.
Luc Verhaegen97866082008-02-09 02:03:06 +0000265 */
266static int board_via_epia_sp(const char *name)
267{
268 struct pci_dev *dev;
Luc Verhaegen97866082008-02-09 02:03:06 +0000269
270 dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
271 if (!dev) {
272 fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
273 return -1;
274 }
275
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000276 vt823x_set_all_writes_to_lpc(dev);
277
278 return 0;
279}
280
281/**
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000282 * Suited for VIAs EPIA N & NL.
283 */
284static int board_via_epia_n(const char *name)
285{
286 struct pci_dev *dev;
287
288 dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */
289 if (!dev) {
290 fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n");
291 return -1;
292 }
293
294 /* All memory cycles, not just ROM ones, go to LPC */
295 vt823x_set_all_writes_to_lpc(dev);
296
297 /* GPIO9 -> output */
298 vt823x_gpio_set(dev, 9, 1);
299
300 return 0;
301}
302
303/**
Luc Verhaegen0f9221c2009-11-29 01:19:25 +0000304 * Suited for:
305 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
306 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
307 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000308 */
Luc Verhaegen0f9221c2009-11-29 01:19:25 +0000309static int w836xx_memw_enable_2e(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000310{
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000311 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000312
313 return 0;
314}
315
316/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000317 * Suited for ASUS P5A.
318 *
319 * This is rather nasty code, but there's no way to do this cleanly.
320 * We're basically talking to some unknown device on SMBus, my guess
321 * is that it is the Winbond W83781D that lives near the DIP BIOS.
322 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000323static int board_asus_p5a(const char *name)
324{
325 uint8_t tmp;
326 int i;
327
328#define ASUSP5A_LOOP 5000
329
Andriy Gapon65c1b862008-05-22 13:22:45 +0000330 OUTB(0x00, 0xE807);
331 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000332
Andriy Gapon65c1b862008-05-22 13:22:45 +0000333 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000334
335 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000336 OUTB(0xE1, 0xFF);
337 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000338 break;
339 }
340
341 if (i == ASUSP5A_LOOP) {
342 printf("%s: Unable to contact device.\n", name);
343 return -1;
344 }
345
Andriy Gapon65c1b862008-05-22 13:22:45 +0000346 OUTB(0x20, 0xE801);
347 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000348
Andriy Gapon65c1b862008-05-22 13:22:45 +0000349 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000350
351 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000352 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000353 if (tmp & 0x70)
354 break;
355 }
356
357 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
358 printf("%s: failed to read device.\n", name);
359 return -1;
360 }
361
Andriy Gapon65c1b862008-05-22 13:22:45 +0000362 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000363 tmp &= ~0x02;
364
Andriy Gapon65c1b862008-05-22 13:22:45 +0000365 OUTB(0x00, 0xE807);
366 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000367
Andriy Gapon65c1b862008-05-22 13:22:45 +0000368 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000369
Andriy Gapon65c1b862008-05-22 13:22:45 +0000370 OUTB(0xFF, 0xE800);
371 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000372
Andriy Gapon65c1b862008-05-22 13:22:45 +0000373 OUTB(0x20, 0xE801);
374 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000375
Andriy Gapon65c1b862008-05-22 13:22:45 +0000376 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000377
378 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000379 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000380 if (tmp & 0x70)
381 break;
382 }
383
384 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
385 printf("%s: failed to write to device.\n", name);
386 return -1;
387 }
388
389 return 0;
390}
391
Luc Verhaegena7e30502009-12-09 11:39:02 +0000392/*
393 * Set GPIO lines in the Broadcom HT-1000 southbridge.
394 *
395 * It's not a Super I/O but it uses the same index/data port method.
396 */
397static int board_hp_dl145_g3_enable(const char *name)
398{
399 /* GPIO 0 reg from PM regs */
400 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
401 sio_mask(0xcd6, 0x44, 0x24, 0x24);
402
403 return 0;
404}
405
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000406static int board_ibm_x3455(const char *name)
407{
Luc Verhaegena7e30502009-12-09 11:39:02 +0000408 /* raise gpio13 */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000409 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000410
411 return 0;
412}
413
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000414/**
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000415 * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4).
416 */
417static int board_shuttle_fn25(const char *name)
418{
419 struct pci_dev *dev;
420
421 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
422 if (!dev) {
423 fprintf(stderr,
424 "\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
425 return -1;
426 }
427
428 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
429 pci_write_byte(dev, 0x92, 0);
430
431 return 0;
432}
433
434/**
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000435 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000436 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000437static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000438{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000439 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000440 uint16_t base;
441 uint8_t tmp;
442
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000443 if ((gpio < 0) || (gpio > 31)) {
444 fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000445 return -1;
446 }
447
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000448 dev = pci_dev_find_vendorclass(0x10DE, 0x0C05);
449 switch (dev->device_id) {
450 case 0x0030: /* CK804 */
451 case 0x0050: /* MCP04 */
452 case 0x0060: /* MCP2 */
453 break;
454 default:
455 fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n");
456 return -1;
457 }
458
459 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
460 base += 0xC0;
461
462 tmp = INB(base + gpio);
463 tmp &= ~0x0F; /* null lower nibble */
464 tmp |= 0x04; /* gpio -> output. */
465 if (raise)
466 tmp |= 0x01;
467 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000468
469 return 0;
470}
471
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000472/**
473 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
474 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000475static int nvidia_mcp_gpio10_raise(const char *name)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000476{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000477 return nvidia_mcp_gpio_set(0x10, 1);
478}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000479
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000480/**
481 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
482 */
483static int nvidia_mcp_gpio21_raise(const char *name)
484{
485 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000486}
487
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000488/**
489 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
490 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000491static int nvidia_mcp_gpio31_raise(const char *name)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000492{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000493 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000494}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000495
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000496/**
497 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
498 */
499static int board_epox_ep_bx3(const char *name)
500{
501 uint8_t tmp;
502
503 /* Raise GPIO22. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000504 tmp = INB(0x4036);
505 OUTB(tmp, 0xEB);
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000506
507 tmp |= 0x40;
508
Andriy Gapon65c1b862008-05-22 13:22:45 +0000509 OUTB(tmp, 0x4036);
510 OUTB(tmp, 0xEB);
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000511
512 return 0;
513}
514
Uwe Hermannffec5f32007-08-23 16:08:21 +0000515/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000516 * Suited for Artec Group DBE61 and DBE62.
517 */
518static int board_artecgroup_dbe6x(const char *name)
519{
520#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
521#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
522#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
523#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
524#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
525#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
526#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
527#define DBE6x_BOOT_LOC_FLASH (2)
528#define DBE6x_BOOT_LOC_FWHUB (3)
529
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000530 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000531 unsigned long boot_loc;
532
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000533 /* Geode only has a single core */
534 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000535 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000536
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000537 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000538
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000539 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000540 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
541 boot_loc = DBE6x_BOOT_LOC_FWHUB;
542 else
543 boot_loc = DBE6x_BOOT_LOC_FLASH;
544
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000545 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
546 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000547 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000548
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000549 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000550
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000551 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000552
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000553 return 0;
554}
555
Uwe Hermann93f66db2008-05-22 21:19:38 +0000556/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000557 * Set a GPIO line on a given intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000558 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000559static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000560{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000561 /* table mapping the different intel ICH LPC chipsets. */
562 static struct {
563 uint16_t id;
564 uint8_t base_reg;
565 uint32_t bank0;
566 uint32_t bank1;
567 uint32_t bank2;
568 } intel_ich_gpio_table[] = {
569 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
570 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
571 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
572 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
573 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
574 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
575 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
576 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
577 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
578 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
579 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
580 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
581 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
582 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
583 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
584 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
585 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
586 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
587 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
588 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
589 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
590 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
591 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
592 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
593 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
594 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
595 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
596 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
597 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
598 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
599 {0, 0, 0, 0, 0} /* end marker */
600 };
Uwe Hermann93f66db2008-05-22 21:19:38 +0000601
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000602 struct pci_dev *dev;
603 uint16_t base;
604 uint32_t tmp;
605 int i, allowed;
606
607 /* First, look for a known LPC bridge */
608 for (dev = pacc->devices; dev; dev = dev->next)
609 if ((dev->vendor_id == 0x8086) &&
610 (dev->device_class == 0x0601)) { /* ISA Bridge */
611 /* Is this device in our list? */
612 for (i = 0; intel_ich_gpio_table[i].id; i++)
613 if (dev->device_id == intel_ich_gpio_table[i].id)
614 break;
615
616 if (intel_ich_gpio_table[i].id)
617 break;
618 }
619
Uwe Hermann93f66db2008-05-22 21:19:38 +0000620 if (!dev) {
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000621 fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +0000622 return -1;
623 }
624
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000625 /* According to the datasheets, all intel ICHs have the gpio bar 5:1
626 strapped to zero. From some mobile ich9 version on, this becomes
627 6:1. The mask below catches all. */
628 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +0000629
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000630 /* check whether the line is allowed */
631 if (gpio < 32)
632 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
633 else if (gpio < 64)
634 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
635 else
636 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
637
638 if (!allowed) {
639 fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow"
640 " setting GPIO%02d\n", gpio);
641 return -1;
642 }
643
644 printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
645 raise ? "Rais" : "Dropp", gpio);
646
647 if (gpio < 32) {
648 /* Set line to GPIO */
649 tmp = INL(base);
650 /* ICH/ICH0 multiplexes 27/28 on the line set. */
651 if ((gpio == 28) &&
652 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
653 tmp |= 1 << 27;
654 else
655 tmp |= 1 << gpio;
656 OUTL(tmp, base);
657
658 /* As soon as we are talking to ICH8 and above, this register
659 decides whether we can set the gpio or not. */
660 if (dev->device_id > 0x2800) {
661 tmp = INL(base);
662 if (!(tmp & (1 << gpio))) {
663 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
664 " does not allow setting GPIO%02d\n",
665 gpio);
666 return -1;
667 }
668 }
669
670 /* Set GPIO to OUTPUT */
671 tmp = INL(base + 0x04);
672 tmp &= ~(1 << gpio);
673 OUTL(tmp, base + 0x04);
674
675 /* Raise GPIO line */
676 tmp = INL(base + 0x0C);
677 if (raise)
678 tmp |= 1 << gpio;
679 else
680 tmp &= ~(1 << gpio);
681 OUTL(tmp, base + 0x0C);
682 } else if (gpio < 64) {
683 gpio -= 32;
684
685 /* Set line to GPIO */
686 tmp = INL(base + 0x30);
687 tmp |= 1 << gpio;
688 OUTL(tmp, base + 0x30);
689
690 /* As soon as we are talking to ICH8 and above, this register
691 decides whether we can set the gpio or not. */
692 if (dev->device_id > 0x2800) {
693 tmp = INL(base + 30);
694 if (!(tmp & (1 << gpio))) {
695 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
696 " does not allow setting GPIO%02d\n",
697 gpio + 32);
698 return -1;
699 }
700 }
701
702 /* Set GPIO to OUTPUT */
703 tmp = INL(base + 0x34);
704 tmp &= ~(1 << gpio);
705 OUTL(tmp, base + 0x34);
706
707 /* Raise GPIO line */
708 tmp = INL(base + 0x38);
709 if (raise)
710 tmp |= 1 << gpio;
711 else
712 tmp &= ~(1 << gpio);
713 OUTL(tmp, base + 0x38);
714 } else {
715 gpio -= 64;
716
717 /* Set line to GPIO */
718 tmp = INL(base + 0x40);
719 tmp |= 1 << gpio;
720 OUTL(tmp, base + 0x40);
721
722 tmp = INL(base + 40);
723 if (!(tmp & (1 << gpio))) {
724 fprintf(stderr, "\nERROR: This Intel LPC Bridge does "
725 "not allow setting GPIO%02d\n", gpio + 64);
726 return -1;
727 }
728
729 /* Set GPIO to OUTPUT */
730 tmp = INL(base + 0x44);
731 tmp &= ~(1 << gpio);
732 OUTL(tmp, base + 0x44);
733
734 /* Raise GPIO line */
735 tmp = INL(base + 0x48);
736 if (raise)
737 tmp |= 1 << gpio;
738 else
739 tmp &= ~(1 << gpio);
740 OUTL(tmp, base + 0x48);
741 }
Uwe Hermann93f66db2008-05-22 21:19:38 +0000742
743 return 0;
744}
745
746/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000747 * Suited for Abit IP35: Intel P35 + ICH9R.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000748 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000749static int intel_ich_gpio16_raise(const char *name)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000750{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000751 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +0000752}
753
Peter Stuge09c13332009-02-02 22:55:26 +0000754/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000755 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000756 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000757static int intel_ich_gpio19_raise(const char *name)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000758{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000759 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000760}
761
762/**
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +0000763 * Suited for:
764 * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
765 * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
Peter Stuge09c13332009-02-02 22:55:26 +0000766 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000767static int intel_ich_gpio21_raise(const char *name)
Peter Stuge09c13332009-02-02 22:55:26 +0000768{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000769 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +0000770}
771
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000772/**
773 * Suited for ASUS P4B266: socket478 + intel 845D + ICH2.
774 */
775static int intel_ich_gpio22_raise(const char *name)
776{
777 return intel_ich_gpio_set(22, 1);
778}
779
780/**
Luc Verhaegen1265d8d2009-11-28 18:16:31 +0000781 * Suited for:
782 * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R.
783 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000784 */
785static int intel_ich_gpio23_raise(const char *name)
786{
787 return intel_ich_gpio_set(23, 1);
788}
789
790/**
791 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
792 */
793static int board_acorp_6a815epd(const char *name)
794{
795 int ret;
796
797 /* Lower Blocks Lock -- pin 7 of PLCC32 */
798 ret = intel_ich_gpio_set(22, 1);
799 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
800 ret = intel_ich_gpio_set(23, 1);
801
802 return ret;
803}
804
805/**
806 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
807 */
Stefan Reinauerac378972008-03-17 22:59:40 +0000808static int board_kontron_986lcd_m(const char *name)
809{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000810 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +0000811
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000812 ret = intel_ich_gpio_set(34, 1); /* #TBL */
813 if (!ret)
814 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +0000815
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000816 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +0000817}
818
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000819/**
Peter Stuge4aa71562008-06-11 02:22:42 +0000820 * Suited for:
Luc Verhaegen11793772009-07-21 01:44:45 +0000821 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
822 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
Luc Verhaegen9892ca62009-12-09 07:43:13 +0000823 *
824 * SIS950 superio probably requires the same flash write enable.
Peter Stuge4aa71562008-06-11 02:22:42 +0000825 */
Luc Verhaegen11793772009-07-21 01:44:45 +0000826static int it8705_rom_write_enable(const char *name)
Peter Stuge4aa71562008-06-11 02:22:42 +0000827{
828 /* enter IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000829 enter_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000830
831 /* select right flash chip */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000832 sio_mask(0x2e, 0x22, 0x80, 0x80);
Peter Stuge4aa71562008-06-11 02:22:42 +0000833
834 /* bit 3: flash chip write enable
835 * bit 7: map flash chip at 1MB-128K (why though? ignoring this.)
836 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000837 sio_mask(0x2e, 0x24, 0x04, 0x04);
Peter Stuge4aa71562008-06-11 02:22:42 +0000838
839 /* exit IT87xx conf mode */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000840 exit_conf_mode_ite(0x2e);
Peter Stuge4aa71562008-06-11 02:22:42 +0000841
842 return 0;
843}
844
845/**
Uwe Hermanna02d6662009-08-20 18:45:18 +0000846 * Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
Luc Verhaegen11793772009-07-21 01:44:45 +0000847 */
848static int board_aopen_vkm400(const char *name)
849{
850 struct pci_dev *dev;
851
852 dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */
853 if (!dev) {
854 fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n");
855 return -1;
856 }
857
858 vt823x_set_all_writes_to_lpc(dev);
859
860 return it8705_rom_write_enable(name);
861}
862
863/**
Sean Nelsonb20953c2008-08-19 21:51:39 +0000864 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
865 *
866 * Suited for:
867 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
Uwe Hermannab60a432009-05-23 00:56:49 +0000868 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Sean Nelsonb20953c2008-08-19 21:51:39 +0000869 */
870static int board_msi_kt4v(const char *name)
871{
872 struct pci_dev *dev;
Sean Nelsonb20953c2008-08-19 21:51:39 +0000873
874 dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */
875 if (!dev) {
876 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
877 return -1;
878 }
879
Luc Verhaegen4802a7b2009-11-28 21:12:58 +0000880 vt823x_set_all_writes_to_lpc(dev);
Sean Nelsonb20953c2008-08-19 21:51:39 +0000881
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000882 vt823x_gpio_set(dev, 12, 1);
883 w836xx_memw_enable(0x2E);
Sean Nelsonb20953c2008-08-19 21:51:39 +0000884
885 return 0;
886}
887
888/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000889 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
890 */
891static int board_soyo_sy_7vca(const char *name)
892{
893 struct pci_dev *dev;
894 uint32_t base;
895 uint8_t tmp;
896
897 /* VT82C686 Power management */
898 dev = pci_dev_find(0x1106, 0x3057);
899 if (!dev) {
900 fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
901 return -1;
902 }
903
904 /* GPO0 output from PM IO base + 0x4C */
905 tmp = pci_read_byte(dev, 0x54);
906 tmp &= ~0x03;
907 pci_write_byte(dev, 0x54, tmp);
908
909 /* PM IO base */
910 base = pci_read_long(dev, 0x48) & 0x0000FF00;
911
912 /* Drop GPO0 */
913 tmp = INB(base + 0x4C);
914 tmp &= ~0x01;
915 OUTB(tmp, base + 0x4C);
916
917 return 0;
918}
919
Uwe Hermann265e7552009-06-21 15:45:34 +0000920static int it8705f_write_enable(uint8_t port, const char *name)
921{
922 enter_conf_mode_ite(port);
923 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
924 exit_conf_mode_ite(port);
925
926 return 0;
927}
928
929/**
Uwe Hermann5ab88892009-06-21 20:50:22 +0000930 * Suited for:
931 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
932 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
Uwe Hermann265e7552009-06-21 15:45:34 +0000933 */
934static int it8705f_write_enable_2e(const char *name)
935{
936 return it8705f_write_enable(0x2e, name);
937}
938
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000939/**
Michael Gold6d52e472009-06-19 13:00:24 +0000940 * Find the runtime registers of an SMSC Super I/O, after verifying its
941 * chip ID.
942 *
943 * Returns the base port of the runtime register block, or 0 on error.
944 */
945static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
946 uint8_t logical_device)
947{
948 uint16_t rt_port = 0;
949
950 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +0000951 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +0000952 if (sio_read(sio_port, 0x20) != chip_id) {
Uwe Hermann1432a602009-06-28 23:26:37 +0000953 fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +0000954 goto out;
955 }
956
957 /* If the runtime block is active, get its address. */
958 sio_write(sio_port, 0x07, logical_device);
959 if (sio_read(sio_port, 0x30) & 1) {
960 rt_port = (sio_read(sio_port, 0x60) << 8)
961 | sio_read(sio_port, 0x61);
962 }
963
964 if (rt_port == 0) {
965 fprintf(stderr, "\nERROR: "
966 "Super I/O runtime interface not available.\n");
967 }
968out:
Uwe Hermann1432a602009-06-28 23:26:37 +0000969 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +0000970 return rt_port;
971}
972
973/**
974 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
975 * connected to GP30 on the Super I/O, and TBL# is always high.
976 */
977static int board_mitac_6513wu(const char *name)
978{
979 struct pci_dev *dev;
980 uint16_t rt_port;
981 uint8_t val;
982
983 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
984 if (!dev) {
985 fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
986 return -1;
987 }
988
Uwe Hermann1432a602009-06-28 23:26:37 +0000989 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +0000990 if (rt_port == 0)
991 return -1;
992
993 /* Configure the GPIO pin. */
994 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +0000995 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +0000996 OUTB(val, rt_port + 0x33);
997
998 /* Disable write protection. */
999 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001000 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001001 OUTB(val, rt_port + 0x4d);
1002
1003 return 0;
1004}
1005
1006/**
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001007 * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
1008 */
1009static int board_asus_a7v8x(const char *name)
1010{
1011 uint16_t id, base;
1012 uint8_t tmp;
1013
1014 /* find the IT8703F */
1015 w836xx_ext_enter(0x2E);
1016 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1017 w836xx_ext_leave(0x2E);
1018
1019 if (id != 0x8701) {
1020 fprintf(stderr, "\nERROR: IT8703F SuperIO not found.\n");
1021 return -1;
1022 }
1023
1024 /* Get the GP567 IO base */
1025 w836xx_ext_enter(0x2E);
1026 sio_write(0x2E, 0x07, 0x0C);
1027 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1028 w836xx_ext_leave(0x2E);
1029
1030 if (!base) {
1031 fprintf(stderr, "\nERROR: Failed to read IT8703F SuperIO GPIO"
1032 " Base.\n");
1033 return -1;
1034 }
1035
1036 /* Raise GP51. */
1037 tmp = INB(base);
1038 tmp |= 0x02;
1039 OUTB(tmp, base);
1040
1041 return 0;
1042}
1043
Luc Verhaegen72272912009-09-01 21:22:23 +00001044/*
1045 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1046 * There is only some limited checking on the port numbers.
1047 */
1048static int
1049it8712f_gpio_set(unsigned int line, int raise)
1050{
1051 unsigned int port;
1052 uint16_t id, base;
1053 uint8_t tmp;
1054
1055 port = line / 10;
1056 port--;
1057 line %= 10;
1058
1059 /* Check line */
1060 if ((port > 4) || /* also catches unsigned -1 */
1061 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
1062 fprintf(stderr,
1063 "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
1064 return -1;
1065 }
1066
1067 /* find the IT8712F */
1068 enter_conf_mode_ite(0x2E);
1069 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1070 exit_conf_mode_ite(0x2E);
1071
1072 if (id != 0x8712) {
1073 fprintf(stderr, "\nERROR: IT8712F SuperIO not found.\n");
1074 return -1;
1075 }
1076
1077 /* Get the GPIO base */
1078 enter_conf_mode_ite(0x2E);
1079 sio_write(0x2E, 0x07, 0x07);
1080 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1081 exit_conf_mode_ite(0x2E);
1082
1083 if (!base) {
1084 fprintf(stderr, "\nERROR: Failed to read IT8712F SuperIO GPIO"
1085 " Base.\n");
1086 return -1;
1087 }
1088
1089 /* set GPIO. */
1090 tmp = INB(base + port);
1091 if (raise)
1092 tmp |= 1 << line;
1093 else
1094 tmp &= ~(1 << line);
1095 OUTB(tmp, base + port);
1096
1097 return 0;
1098}
1099
1100/**
1101 * Suited for Asus A7V600-X: VIA KT600 + VT8237 + IT8712F
1102 */
1103static int board_asus_a7v600x(const char *name)
1104{
1105 return it8712f_gpio_set(32, 1);
1106}
1107
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001108/**
David Bartleyf58d3642009-12-09 07:53:01 +00001109 * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
1110 */
1111static int board_asus_m2v_mx(const char *name)
1112{
1113 struct pci_dev *dev;
1114
1115 dev = pci_dev_find(0x1106, 0x3337); /* VT8237A ISA bridge */
1116 if (!dev) {
1117 fprintf(stderr, "\nERROR: VT8237A ISA bridge not found.\n");
1118 return -1;
1119 }
1120
1121 /* GPO5 is connected to WP# and TBL#. */
1122 vt823x_gpio_set(dev, 5, 1);
1123
1124 return 0;
1125}
1126
1127
1128/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001129 * Below is the list of boards which need a special "board enable" code in
1130 * flashrom before their ROM chip can be accessed/written to.
1131 *
1132 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1133 * to the respective tables in print.c. Thanks!
1134 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001135 * We use 2 sets of IDs here, you're free to choose which is which. This
1136 * is to provide a very high degree of certainty when matching a board on
1137 * the basis of subsystem/card IDs. As not every vendor handles
1138 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001139 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001140 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
1141 * NULLed if they don't identify the board fully. But please take care to
1142 * provide an as complete set of pci ids as possible; autodetection is the
1143 * preferred behaviour and we would like to make sure that matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001144 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001145 * The coreboot ids are used two fold. When running with a coreboot firmware,
1146 * the ids uniquely matches the coreboot board identification string. When a
1147 * legacy bios is installed and when autodetection is not possible, these ids
1148 * can be used to identify the board through the -m command line argument.
1149 *
1150 * When a board is identified through its coreboot ids (in both cases), the
1151 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001152 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001153
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001154/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001155struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermannab60a432009-05-23 00:56:49 +00001156 /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001157 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001158 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, "Acorp", "6A815EPD", board_acorp_6a815epd},
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001159 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001160 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e},
Luc Verhaegen0f9221c2009-11-29 01:19:25 +00001161 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e},
Uwe Hermanna02d6662009-08-20 18:45:18 +00001162 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001163 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x},
1164 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x},
Luc Verhaegen72272912009-09-01 21:22:23 +00001165 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x},
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001166 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x},
Uwe Hermannef016f52009-07-04 15:10:41 +00001167 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx},
David Bartleyf58d3642009-12-09 07:53:01 +00001168 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", board_asus_m2v_mx},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001169 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise},
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001170 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001171 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001172 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a},
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001173 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise},
Luc Verhaegen11793772009-07-21 01:44:45 +00001174 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001175 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise},
Uwe Hermann5ab88892009-06-21 20:50:22 +00001176 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},
Luc Verhaegen0f9221c2009-11-29 01:19:25 +00001177 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e},
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001178 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001179 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001180 {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash},
Luc Verhaegen11793772009-07-21 01:44:45 +00001181 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable},
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001182 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001183 {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash},
1184 {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash},
Uwe Hermann0495c942009-05-18 22:27:53 +00001185 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash},
1186 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", it87xx_probe_spi_flash},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001187 {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001188 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001189 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, "IBM", "x3455", board_ibm_x3455},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001190 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi},
1191 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001192 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m},
Michael Gold6d52e472009-06-19 13:00:24 +00001193 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001194 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v},
Uwe Hermannd1129ac2009-05-28 15:07:42 +00001195 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e},
Luc Verhaegen4802a7b2009-11-28 21:12:58 +00001196 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v},
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001197 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001198 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
Luc Verhaegen0f9221c2009-11-29 01:19:25 +00001199 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e},
Uwe Hermann265e7552009-06-21 15:45:34 +00001200 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e},
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001201 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001202 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001203 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
1204 {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},
1205 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001206 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", board_via_epia_n},
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001207 {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp},
Luc Verhaegena7e30502009-12-09 11:39:02 +00001208 {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash},
Uwe Hermann5ab88892009-06-21 20:50:22 +00001209
Uwe Hermann5e1aecd2009-05-18 21:56:16 +00001210 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001211};
1212
Uwe Hermannffec5f32007-08-23 16:08:21 +00001213/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001214 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001215 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001216 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001217static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1218 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001219{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001220 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001221 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001222
Uwe Hermanna93045c2009-05-09 00:47:04 +00001223 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001224 if (vendor && (!board->lb_vendor
1225 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001226 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001227
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001228 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001229 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001230
Uwe Hermanna7e05482007-05-09 10:17:44 +00001231 if (!pci_dev_find(board->first_vendor, board->first_device))
1232 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001233
Uwe Hermanna7e05482007-05-09 10:17:44 +00001234 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001235 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001236 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001237
1238 if (vendor)
1239 return board;
1240
1241 if (partmatch) {
1242 /* a second entry has a matching part name */
1243 printf("AMBIGUOUS BOARD NAME: %s\n", part);
1244 printf("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001245 partmatch->lb_vendor, board->lb_vendor);
Peter Stuge6b53fed2008-01-27 16:21:21 +00001246 printf("Please use the full -m vendor:part syntax.\n");
1247 return NULL;
1248 }
1249 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001250 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001251
Peter Stuge6b53fed2008-01-27 16:21:21 +00001252 if (partmatch)
1253 return partmatch;
1254
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001255 if (!partvendor_from_cbtable) {
1256 /* Only warn if the mainboard type was not gathered from the
1257 * coreboot table. If it was, the coreboot implementor is
1258 * expected to fix flashrom, too.
1259 */
1260 printf("\nUnknown vendor:board from -m option: %s:%s\n\n",
1261 vendor, part);
1262 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001263 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001264}
1265
Uwe Hermannffec5f32007-08-23 16:08:21 +00001266/**
1267 * Match boards on PCI IDs and subsystem IDs.
1268 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001269 */
1270static struct board_pciid_enable *board_match_pci_card_ids(void)
1271{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001272 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001273
Uwe Hermanna93045c2009-05-09 00:47:04 +00001274 for (; board->vendor_name; board++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +00001275 if (!board->first_card_vendor || !board->first_card_device)
1276 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001277
Uwe Hermanna7e05482007-05-09 10:17:44 +00001278 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001279 board->first_card_vendor,
1280 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001281 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001282
Uwe Hermanna7e05482007-05-09 10:17:44 +00001283 if (board->second_vendor) {
1284 if (board->second_card_vendor) {
1285 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001286 board->second_device,
1287 board->second_card_vendor,
1288 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001289 continue;
1290 } else {
1291 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001292 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001293 continue;
1294 }
1295 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001296
Uwe Hermanna7e05482007-05-09 10:17:44 +00001297 return board;
1298 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001299
Uwe Hermanna7e05482007-05-09 10:17:44 +00001300 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001301}
1302
Uwe Hermann372eeb52007-12-04 21:49:06 +00001303int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001304{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001305 struct board_pciid_enable *board = NULL;
1306 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001307
Peter Stuge6b53fed2008-01-27 16:21:21 +00001308 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001309 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001310
Uwe Hermanna7e05482007-05-09 10:17:44 +00001311 if (!board)
1312 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001313
Uwe Hermanna7e05482007-05-09 10:17:44 +00001314 if (board) {
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001315 printf("Disabling flash write protection for board \"%s %s\"... ",
Uwe Hermanna93045c2009-05-09 00:47:04 +00001316 board->vendor_name, board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001317
Uwe Hermanna93045c2009-05-09 00:47:04 +00001318 ret = board->enable(board->vendor_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001319 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001320 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001321 else
1322 printf("OK.\n");
1323 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001324
Uwe Hermanna7e05482007-05-09 10:17:44 +00001325 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001326}