blob: 30c343f4df950a385d50fb40038e039fbe7de9ad [file] [log] [blame]
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Sean Nelsonc57a9202010-01-04 17:15:23 +00008 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000014 *
Uwe Hermannd1107642007-08-29 17:52:32 +000015 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 *
Uwe Hermannd1107642007-08-29 17:52:32 +000020 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023 */
24
25#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000026#include "chipdrivers.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000027
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000028#define MAX_REFLASH_TRIES 0x10
Sean Nelsonc57a9202010-01-04 17:15:23 +000029#define MASK_FULL 0xffff
30#define MASK_2AA 0x7ff
Sean Nelson35727f72010-01-28 23:55:12 +000031#define MASK_AAA 0xfff
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000032
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000033/* Check one byte for odd parity */
34uint8_t oddparity(uint8_t val)
35{
36 val = (val ^ (val >> 4)) & 0xf;
37 val = (val ^ (val >> 2)) & 0x3;
38 return (val ^ (val >> 1)) & 0x1;
39}
40
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000041void toggle_ready_jedec_common(chipaddr dst, int delay)
Uwe Hermann51582f22007-08-23 10:20:40 +000042{
43 unsigned int i = 0;
44 uint8_t tmp1, tmp2;
45
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000046 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000047
48 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000049 if (delay)
50 programmer_delay(delay);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000051 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000052 if (tmp1 == tmp2) {
53 break;
54 }
55 tmp1 = tmp2;
56 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000057 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000058 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000059}
60
61void toggle_ready_jedec(chipaddr dst)
62{
63 toggle_ready_jedec_common(dst, 0);
64}
65
66/* Some chips require a minimum delay between toggle bit reads.
67 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
68 * but experiments show that 2 ms are already enough. Pick a safety factor
69 * of 4 and use an 8 ms delay.
70 * Given that erase is slow on all chips, it is recommended to use
71 * toggle_ready_jedec_slow in erase functions.
72 */
73void toggle_ready_jedec_slow(chipaddr dst)
74{
75 toggle_ready_jedec_common(dst, 8 * 1000);
Uwe Hermann51582f22007-08-23 10:20:40 +000076}
77
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000078void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000079{
80 unsigned int i = 0;
81 uint8_t tmp;
82
83 data &= 0x80;
84
85 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000086 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000087 if (tmp == data) {
88 break;
89 }
90 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000091 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000092 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Uwe Hermann51582f22007-08-23 10:20:40 +000093}
94
Sean Nelsonc57a9202010-01-04 17:15:23 +000095void start_program_jedec_common(struct flashchip *flash, unsigned int mask)
Uwe Hermann51582f22007-08-23 10:20:40 +000096{
Sean Nelsonc57a9202010-01-04 17:15:23 +000097 chipaddr bios = flash->virtual_memory;
98 chip_writeb(0xAA, bios + (0x5555 & mask));
99 chip_writeb(0x55, bios + (0x2AAA & mask));
100 chip_writeb(0xA0, bios + (0x5555 & mask));
Uwe Hermann51582f22007-08-23 10:20:40 +0000101}
102
Sean Nelson35727f72010-01-28 23:55:12 +0000103int probe_jedec_common(struct flashchip *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000104{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000105 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +0000106 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000107 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000108 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +0000109 int probe_timing_enter, probe_timing_exit;
110
111 if (flash->probe_timing > 0)
112 probe_timing_enter = probe_timing_exit = flash->probe_timing;
113 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
114 probe_timing_enter = probe_timing_exit = 0;
115 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
Sean Nelsoned479d22010-03-24 23:14:32 +0000116 msg_cdbg("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000117 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +0000118 probe_timing_enter = 10000;
119 probe_timing_exit = 40;
120 } else {
Sean Nelsoned479d22010-03-24 23:14:32 +0000121 msg_cerr("Chip has negative value in probe_timing, failing "
Maciej Pijankac6e11112009-06-03 14:46:22 +0000122 "without chip access\n");
123 return 0;
124 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000125
Ollie Lho761bf1b2004-03-20 16:46:10 +0000126 /* Issue JEDEC Product ID Entry command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000127 chip_writeb(0xAA, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000128 if (probe_timing_enter)
129 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000130 chip_writeb(0x55, bios + (0x2AAA & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000131 if (probe_timing_enter)
132 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000133 chip_writeb(0x90, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000134 if (probe_timing_enter)
135 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000136
Ollie Lho761bf1b2004-03-20 16:46:10 +0000137 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000138 id1 = chip_readb(bios);
139 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000140 largeid1 = id1;
141 largeid2 = id2;
142
143 /* Check if it is a continuation ID, this should be a while loop. */
144 if (id1 == 0x7F) {
145 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000146 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000147 largeid1 |= id1;
148 }
149 if (id2 == 0x7F) {
150 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000151 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000152 largeid2 |= id2;
153 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000154
Ollie Lho761bf1b2004-03-20 16:46:10 +0000155 /* Issue JEDEC Product ID Exit command */
Sean Nelson35727f72010-01-28 23:55:12 +0000156 if ((flash->feature_bits & FEATURE_SHORT_RESET) == FEATURE_LONG_RESET)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000157 {
158 chip_writeb(0xAA, bios + (0x5555 & mask));
159 if (probe_timing_exit)
160 programmer_delay(10);
161 chip_writeb(0x55, bios + (0x2AAA & mask));
162 if (probe_timing_exit)
163 programmer_delay(10);
164 }
165 chip_writeb(0xF0, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000166 if (probe_timing_exit)
167 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000168
Sean Nelsoned479d22010-03-24 23:14:32 +0000169 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000170 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +0000171 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000172
173 /* Read the product ID location again. We should now see normal flash contents. */
174 flashcontent1 = chip_readb(bios);
175 flashcontent2 = chip_readb(bios + 0x01);
176
177 /* Check if it is a continuation ID, this should be a while loop. */
178 if (flashcontent1 == 0x7F) {
179 flashcontent1 <<= 8;
180 flashcontent1 |= chip_readb(bios + 0x100);
181 }
182 if (flashcontent2 == 0x7F) {
183 flashcontent2 <<= 8;
184 flashcontent2 |= chip_readb(bios + 0x101);
185 }
186
187 if (largeid1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +0000188 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000189 if (largeid2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +0000190 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000191
Sean Nelsoned479d22010-03-24 23:14:32 +0000192 msg_cdbg("\n");
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000193 if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id)
194 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000195
Sean Nelsonc57a9202010-01-04 17:15:23 +0000196 if (flash->feature_bits & FEATURE_REGISTERMAP)
197 map_flash_registers(flash);
198
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000199 return 1;
Ollie Lho73eca802004-03-19 22:10:07 +0000200}
201
Sean Nelsonc57a9202010-01-04 17:15:23 +0000202int erase_sector_jedec_common(struct flashchip *flash, unsigned int page,
203 unsigned int pagesize, unsigned int mask)
Ollie Lho73eca802004-03-19 22:10:07 +0000204{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000205 chipaddr bios = flash->virtual_memory;
206
Ollie Lho761bf1b2004-03-20 16:46:10 +0000207 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000208 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000209 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000210 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000211 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000212 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000213 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000214
Sean Nelsonc57a9202010-01-04 17:15:23 +0000215 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000216 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000217 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000218 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000219 chip_writeb(0x30, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000220 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000221
Ollie Lho73eca802004-03-19 22:10:07 +0000222 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000223 toggle_ready_jedec_slow(bios);
Ollie Lho73eca802004-03-19 22:10:07 +0000224
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000225 if (check_erased_range(flash, page, pagesize)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000226 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000227 return -1;
228 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000229 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000230}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000231
Sean Nelsonc57a9202010-01-04 17:15:23 +0000232int erase_block_jedec_common(struct flashchip *flash, unsigned int block,
233 unsigned int blocksize, unsigned int mask)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000234{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000235 chipaddr bios = flash->virtual_memory;
236
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000237 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000238 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000239 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000240 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000241 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000242 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000243 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000244
Sean Nelsonc57a9202010-01-04 17:15:23 +0000245 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000246 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000247 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000248 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000249 chip_writeb(0x50, bios + block);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000250 programmer_delay(10);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000251
252 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000253 toggle_ready_jedec_slow(bios);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000254
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000255 if (check_erased_range(flash, block, blocksize)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000256 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000257 return -1;
258 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000259 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000260}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000261
Sean Nelsonc57a9202010-01-04 17:15:23 +0000262int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000263{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000264 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000265 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000266
Ollie Lho761bf1b2004-03-20 16:46:10 +0000267 /* Issue the JEDEC Chip Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000268 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000269 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000270 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000271 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000272 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000273 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000274
Sean Nelsonc57a9202010-01-04 17:15:23 +0000275 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000276 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000277 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000278 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000279 chip_writeb(0x10, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000280 programmer_delay(10);
Ollie Lho73eca802004-03-19 22:10:07 +0000281
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000282 toggle_ready_jedec_slow(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000283
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000284 if (check_erased_range(flash, 0, total_size)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000285 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000286 return -1;
287 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000288 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000289}
290
Sean Nelsonc57a9202010-01-04 17:15:23 +0000291int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src,
292 chipaddr dst, unsigned int mask)
293{
294 int tried = 0, failed = 0;
295 chipaddr bios = flash->virtual_memory;
296
297 /* If the data is 0xFF, don't program it and don't complain. */
298 if (*src == 0xFF) {
299 return 0;
300 }
301
302retry:
303 /* Issue JEDEC Byte Program command */
304 start_program_jedec_common(flash, mask);
305
306 /* transfer data from source to destination */
307 chip_writeb(*src, dst);
308 toggle_ready_jedec(bios);
309
310 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
311 goto retry;
312 }
313
314 if (tried >= MAX_REFLASH_TRIES)
315 failed = 1;
316
317 return failed;
318}
319
320int write_sector_jedec_common(struct flashchip *flash, uint8_t *src,
321 chipaddr dst, unsigned int page_size, unsigned int mask)
322{
323 int i, failed = 0;
324 chipaddr olddst;
325
326 olddst = dst;
327 for (i = 0; i < page_size; i++) {
328 if (write_byte_program_jedec_common(flash, src, dst, mask))
329 failed = 1;
330 dst++, src++;
331 }
332 if (failed)
Sean Nelsoned479d22010-03-24 23:14:32 +0000333 msg_cerr(" writing sector at 0x%lx failed!\n", olddst);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000334
335 return failed;
336}
337
338int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src,
339 int start, int page_size, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000340{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000341 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000342 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000343 chipaddr bios = flash->virtual_memory;
344 chipaddr dst = bios + start;
345 chipaddr d = dst;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000346
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000347retry:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000348 /* Issue JEDEC Start Program command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000349 start_program_jedec_common(flash, mask);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000350
Ollie Lho98bea8a2004-12-07 03:15:51 +0000351 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000352 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000353 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000354 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000355 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000356 dst++;
357 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000358 }
359
Ollie Lho761bf1b2004-03-20 16:46:10 +0000360 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000361
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000362 dst = d;
363 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000364 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000365
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000366 if (failed && tried++ < MAX_REFLASH_TRIES) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000367 msg_cerr("retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000368 goto retry;
369 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000370 if (failed) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000371 msg_cerr(" page 0x%lx failed!\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000372 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000373 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000374 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000375}
376
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000377int getaddrmask(struct flashchip *flash)
378{
379 switch (flash->feature_bits & FEATURE_ADDR_MASK) {
380 case FEATURE_ADDR_FULL:
381 return MASK_FULL;
382 break;
Sean Nelson35727f72010-01-28 23:55:12 +0000383 case FEATURE_ADDR_2AA:
384 return MASK_2AA;
385 break;
386 case FEATURE_ADDR_AAA:
387 return MASK_AAA;
388 break;
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000389 default:
Sean Nelsoned479d22010-03-24 23:14:32 +0000390 msg_cerr("%s called with unknown mask\n", __func__);
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000391 return 0;
392 break;
393 }
394}
395
Ollie Lho184a4042005-11-26 21:55:36 +0000396int write_jedec(struct flashchip *flash, uint8_t *buf)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000397{
Sean Nelson35727f72010-01-28 23:55:12 +0000398 int mask;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000399 int i, failed = 0;
Ollie Lho070647d2004-03-22 22:19:17 +0000400 int total_size = flash->total_size * 1024;
401 int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000402
Sean Nelson35727f72010-01-28 23:55:12 +0000403 mask = getaddrmask(flash);
404
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000405 if (erase_chip_jedec(flash)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000406 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000407 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000408 }
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000409
Sean Nelsoned479d22010-03-24 23:14:32 +0000410 msg_cinfo("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000411 for (i = 0; i < total_size / page_size; i++) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000412 msg_cinfo("%04d at address: 0x%08x", i, i * page_size);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000413 if (write_page_write_jedec_common(flash, buf + i * page_size,
Sean Nelson35727f72010-01-28 23:55:12 +0000414 i * page_size, page_size, mask))
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000415 failed = 1;
Sean Nelsoned479d22010-03-24 23:14:32 +0000416 msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000417 }
Sean Nelsoned479d22010-03-24 23:14:32 +0000418 msg_cinfo("DONE!\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000419
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000420 return failed;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000421}
Michael Karcher1c296ca2009-11-27 17:49:42 +0000422
423int write_jedec_1(struct flashchip *flash, uint8_t * buf)
424{
425 int i;
426 chipaddr bios = flash->virtual_memory;
427 chipaddr dst = bios;
Sean Nelson35727f72010-01-28 23:55:12 +0000428 int mask;
429
430 mask = getaddrmask(flash);
Michael Karcher1c296ca2009-11-27 17:49:42 +0000431
432 programmer_delay(10);
433 if (erase_flash(flash)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000434 msg_cerr("ERASE FAILED!\n");
Michael Karcher1c296ca2009-11-27 17:49:42 +0000435 return -1;
436 }
437
Sean Nelsoned479d22010-03-24 23:14:32 +0000438 msg_cinfo("Programming page: ");
Michael Karcher1c296ca2009-11-27 17:49:42 +0000439 for (i = 0; i < flash->total_size; i++) {
440 if ((i & 0x3) == 0)
Sean Nelsoned479d22010-03-24 23:14:32 +0000441 msg_cinfo("address: 0x%08lx", (unsigned long)i * 1024);
Michael Karcher1c296ca2009-11-27 17:49:42 +0000442
Sean Nelson35727f72010-01-28 23:55:12 +0000443 write_sector_jedec_common(flash, buf + i * 1024, dst + i * 1024, 1024, mask);
Michael Karcher1c296ca2009-11-27 17:49:42 +0000444
445 if ((i & 0x3) == 0)
Sean Nelsoned479d22010-03-24 23:14:32 +0000446 msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Michael Karcher1c296ca2009-11-27 17:49:42 +0000447 }
448
Sean Nelsoned479d22010-03-24 23:14:32 +0000449 msg_cinfo("DONE!\n");
Michael Karcher1c296ca2009-11-27 17:49:42 +0000450 return 0;
451}
Sean Nelsonc57a9202010-01-04 17:15:23 +0000452
453/* erase chip with block_erase() prototype */
454int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr,
455 unsigned int blocksize)
456{
Sean Nelson35727f72010-01-28 23:55:12 +0000457 int mask;
458
459 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000460 if ((addr != 0) || (blocksize != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000461 msg_cerr("%s called with incorrect arguments\n",
Sean Nelsonc57a9202010-01-04 17:15:23 +0000462 __func__);
463 return -1;
464 }
Sean Nelson35727f72010-01-28 23:55:12 +0000465 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000466}
467
468int probe_jedec(struct flashchip *flash)
469{
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000470 int mask;
471
472 mask = getaddrmask(flash);
Sean Nelson35727f72010-01-28 23:55:12 +0000473 return probe_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000474}
475
476int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int size)
477{
Sean Nelson35727f72010-01-28 23:55:12 +0000478 int mask;
479
480 mask = getaddrmask(flash);
481 return erase_sector_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000482}
483
484int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int size)
485{
Sean Nelson35727f72010-01-28 23:55:12 +0000486 int mask;
487
488 mask = getaddrmask(flash);
489 return erase_block_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000490}
491
492int erase_chip_jedec(struct flashchip *flash)
493{
Sean Nelson35727f72010-01-28 23:55:12 +0000494 int mask;
495
496 mask = getaddrmask(flash);
497 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000498}