Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it> |
| 6 | * Copyright (C) 2006 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com> |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 9 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 14 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 19 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 23 | */ |
| 24 | |
| 25 | #include "flash.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 26 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 27 | #define MAX_REFLASH_TRIES 0x10 |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 28 | #define MASK_FULL 0xffff |
| 29 | #define MASK_2AA 0x7ff |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 30 | #define MASK_AAA 0xfff |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 31 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 32 | /* Check one byte for odd parity */ |
| 33 | uint8_t oddparity(uint8_t val) |
| 34 | { |
| 35 | val = (val ^ (val >> 4)) & 0xf; |
| 36 | val = (val ^ (val >> 2)) & 0x3; |
| 37 | return (val ^ (val >> 1)) & 0x1; |
| 38 | } |
| 39 | |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 40 | void toggle_ready_jedec_common(chipaddr dst, int delay) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 41 | { |
| 42 | unsigned int i = 0; |
| 43 | uint8_t tmp1, tmp2; |
| 44 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 45 | tmp1 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 46 | |
| 47 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 48 | if (delay) |
| 49 | programmer_delay(delay); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 50 | tmp2 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 51 | if (tmp1 == tmp2) { |
| 52 | break; |
| 53 | } |
| 54 | tmp1 = tmp2; |
| 55 | } |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 56 | if (i > 0x100000) |
| 57 | printf_debug("%s: excessive loops, i=0x%x\n", __func__, i); |
| 58 | } |
| 59 | |
| 60 | void toggle_ready_jedec(chipaddr dst) |
| 61 | { |
| 62 | toggle_ready_jedec_common(dst, 0); |
| 63 | } |
| 64 | |
| 65 | /* Some chips require a minimum delay between toggle bit reads. |
| 66 | * The Winbond W39V040C wants 50 ms between reads on sector erase toggle, |
| 67 | * but experiments show that 2 ms are already enough. Pick a safety factor |
| 68 | * of 4 and use an 8 ms delay. |
| 69 | * Given that erase is slow on all chips, it is recommended to use |
| 70 | * toggle_ready_jedec_slow in erase functions. |
| 71 | */ |
| 72 | void toggle_ready_jedec_slow(chipaddr dst) |
| 73 | { |
| 74 | toggle_ready_jedec_common(dst, 8 * 1000); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 75 | } |
| 76 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 77 | void data_polling_jedec(chipaddr dst, uint8_t data) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 78 | { |
| 79 | unsigned int i = 0; |
| 80 | uint8_t tmp; |
| 81 | |
| 82 | data &= 0x80; |
| 83 | |
| 84 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 85 | tmp = chip_readb(dst) & 0x80; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 86 | if (tmp == data) { |
| 87 | break; |
| 88 | } |
| 89 | } |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 90 | if (i > 0x100000) |
| 91 | printf_debug("%s: excessive loops, i=0x%x\n", __func__, i); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 94 | void start_program_jedec_common(struct flashchip *flash, unsigned int mask) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 95 | { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 96 | chipaddr bios = flash->virtual_memory; |
| 97 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
| 98 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
| 99 | chip_writeb(0xA0, bios + (0x5555 & mask)); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 102 | int probe_jedec_common(struct flashchip *flash, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 103 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 104 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 105 | uint8_t id1, id2; |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 106 | uint32_t largeid1, largeid2; |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 107 | uint32_t flashcontent1, flashcontent2; |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 108 | int probe_timing_enter, probe_timing_exit; |
| 109 | |
| 110 | if (flash->probe_timing > 0) |
| 111 | probe_timing_enter = probe_timing_exit = flash->probe_timing; |
| 112 | else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */ |
| 113 | probe_timing_enter = probe_timing_exit = 0; |
| 114 | } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ |
| 115 | printf_debug("Chip lacks correct probe timing information, " |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 116 | "using default 10mS/40uS. "); |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 117 | probe_timing_enter = 10000; |
| 118 | probe_timing_exit = 40; |
| 119 | } else { |
| 120 | printf("Chip has negative value in probe_timing, failing " |
| 121 | "without chip access\n"); |
| 122 | return 0; |
| 123 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 124 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 125 | /* Issue JEDEC Product ID Entry command */ |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 126 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 127 | if (probe_timing_enter) |
| 128 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 129 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 130 | if (probe_timing_enter) |
| 131 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 132 | chip_writeb(0x90, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 133 | if (probe_timing_enter) |
| 134 | programmer_delay(probe_timing_enter); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 135 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 136 | /* Read product ID */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 137 | id1 = chip_readb(bios); |
| 138 | id2 = chip_readb(bios + 0x01); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 139 | largeid1 = id1; |
| 140 | largeid2 = id2; |
| 141 | |
| 142 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 143 | if (id1 == 0x7F) { |
| 144 | largeid1 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 145 | id1 = chip_readb(bios + 0x100); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 146 | largeid1 |= id1; |
| 147 | } |
| 148 | if (id2 == 0x7F) { |
| 149 | largeid2 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 150 | id2 = chip_readb(bios + 0x101); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 151 | largeid2 |= id2; |
| 152 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 153 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 154 | /* Issue JEDEC Product ID Exit command */ |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 155 | if ((flash->feature_bits & FEATURE_SHORT_RESET) == FEATURE_LONG_RESET) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 156 | { |
| 157 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
| 158 | if (probe_timing_exit) |
| 159 | programmer_delay(10); |
| 160 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
| 161 | if (probe_timing_exit) |
| 162 | programmer_delay(10); |
| 163 | } |
| 164 | chip_writeb(0xF0, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 165 | if (probe_timing_exit) |
| 166 | programmer_delay(probe_timing_exit); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 167 | |
Uwe Hermann | 04aa59a | 2009-09-02 22:09:00 +0000 | [diff] [blame] | 168 | printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 169 | if (!oddparity(id1)) |
| 170 | printf_debug(", id1 parity violation"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 171 | |
| 172 | /* Read the product ID location again. We should now see normal flash contents. */ |
| 173 | flashcontent1 = chip_readb(bios); |
| 174 | flashcontent2 = chip_readb(bios + 0x01); |
| 175 | |
| 176 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 177 | if (flashcontent1 == 0x7F) { |
| 178 | flashcontent1 <<= 8; |
| 179 | flashcontent1 |= chip_readb(bios + 0x100); |
| 180 | } |
| 181 | if (flashcontent2 == 0x7F) { |
| 182 | flashcontent2 <<= 8; |
| 183 | flashcontent2 |= chip_readb(bios + 0x101); |
| 184 | } |
| 185 | |
| 186 | if (largeid1 == flashcontent1) |
| 187 | printf_debug(", id1 is normal flash content"); |
| 188 | if (largeid2 == flashcontent2) |
| 189 | printf_debug(", id2 is normal flash content"); |
| 190 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 191 | printf_debug("\n"); |
Carl-Daniel Hailfinger | e940466 | 2010-01-09 02:24:17 +0000 | [diff] [blame] | 192 | if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id) |
| 193 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 194 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 195 | if (flash->feature_bits & FEATURE_REGISTERMAP) |
| 196 | map_flash_registers(flash); |
| 197 | |
Carl-Daniel Hailfinger | e940466 | 2010-01-09 02:24:17 +0000 | [diff] [blame] | 198 | return 1; |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 199 | } |
| 200 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 201 | int erase_sector_jedec_common(struct flashchip *flash, unsigned int page, |
| 202 | unsigned int pagesize, unsigned int mask) |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 203 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 204 | chipaddr bios = flash->virtual_memory; |
| 205 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 206 | /* Issue the Sector Erase command */ |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 207 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 208 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 209 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 210 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 211 | chip_writeb(0x80, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 212 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 213 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 214 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 215 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 216 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 217 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 218 | chip_writeb(0x30, bios + page); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 219 | programmer_delay(10); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 220 | |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 221 | /* wait for Toggle bit ready */ |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 222 | toggle_ready_jedec_slow(bios); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 223 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 224 | if (check_erased_range(flash, page, pagesize)) { |
| 225 | fprintf(stderr,"ERASE FAILED!\n"); |
| 226 | return -1; |
| 227 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 228 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 229 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 230 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 231 | int erase_block_jedec_common(struct flashchip *flash, unsigned int block, |
| 232 | unsigned int blocksize, unsigned int mask) |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 233 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 234 | chipaddr bios = flash->virtual_memory; |
| 235 | |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 236 | /* Issue the Sector Erase command */ |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 237 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 238 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 239 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 240 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 241 | chip_writeb(0x80, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 242 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 243 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 244 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 245 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 246 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 247 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 248 | chip_writeb(0x50, bios + block); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 249 | programmer_delay(10); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 250 | |
| 251 | /* wait for Toggle bit ready */ |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 252 | toggle_ready_jedec_slow(bios); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 253 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 254 | if (check_erased_range(flash, block, blocksize)) { |
| 255 | fprintf(stderr,"ERASE FAILED!\n"); |
| 256 | return -1; |
| 257 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 258 | return 0; |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 259 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 260 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 261 | int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 262 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 263 | int total_size = flash->total_size * 1024; |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 264 | chipaddr bios = flash->virtual_memory; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 265 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 266 | /* Issue the JEDEC Chip Erase command */ |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 267 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 268 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 269 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 270 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 271 | chip_writeb(0x80, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 272 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 273 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 274 | chip_writeb(0xAA, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 275 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 276 | chip_writeb(0x55, bios + (0x2AAA & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 277 | programmer_delay(10); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 278 | chip_writeb(0x10, bios + (0x5555 & mask)); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 279 | programmer_delay(10); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 280 | |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 281 | toggle_ready_jedec_slow(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 282 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 283 | if (check_erased_range(flash, 0, total_size)) { |
| 284 | fprintf(stderr,"ERASE FAILED!\n"); |
| 285 | return -1; |
| 286 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 287 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 288 | } |
| 289 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 290 | int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src, |
| 291 | chipaddr dst, unsigned int mask) |
| 292 | { |
| 293 | int tried = 0, failed = 0; |
| 294 | chipaddr bios = flash->virtual_memory; |
| 295 | |
| 296 | /* If the data is 0xFF, don't program it and don't complain. */ |
| 297 | if (*src == 0xFF) { |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | retry: |
| 302 | /* Issue JEDEC Byte Program command */ |
| 303 | start_program_jedec_common(flash, mask); |
| 304 | |
| 305 | /* transfer data from source to destination */ |
| 306 | chip_writeb(*src, dst); |
| 307 | toggle_ready_jedec(bios); |
| 308 | |
| 309 | if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { |
| 310 | goto retry; |
| 311 | } |
| 312 | |
| 313 | if (tried >= MAX_REFLASH_TRIES) |
| 314 | failed = 1; |
| 315 | |
| 316 | return failed; |
| 317 | } |
| 318 | |
| 319 | int write_sector_jedec_common(struct flashchip *flash, uint8_t *src, |
| 320 | chipaddr dst, unsigned int page_size, unsigned int mask) |
| 321 | { |
| 322 | int i, failed = 0; |
| 323 | chipaddr olddst; |
| 324 | |
| 325 | olddst = dst; |
| 326 | for (i = 0; i < page_size; i++) { |
| 327 | if (write_byte_program_jedec_common(flash, src, dst, mask)) |
| 328 | failed = 1; |
| 329 | dst++, src++; |
| 330 | } |
| 331 | if (failed) |
| 332 | fprintf(stderr, " writing sector at 0x%lx failed!\n", olddst); |
| 333 | |
| 334 | return failed; |
| 335 | } |
| 336 | |
| 337 | int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, |
| 338 | int start, int page_size, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 339 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 340 | int i, tried = 0, failed; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 341 | uint8_t *s = src; |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 342 | chipaddr bios = flash->virtual_memory; |
| 343 | chipaddr dst = bios + start; |
| 344 | chipaddr d = dst; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 345 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 346 | retry: |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 347 | /* Issue JEDEC Start Program comand */ |
| 348 | start_program_jedec_common(flash, mask); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 349 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 350 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame] | 351 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 352 | /* If the data is 0xFF, don't program it */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 353 | if (*src != 0xFF) |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 354 | chip_writeb(*src, dst); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 355 | dst++; |
| 356 | src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 357 | } |
| 358 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 359 | toggle_ready_jedec(dst - 1); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 360 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 361 | dst = d; |
| 362 | src = s; |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 363 | failed = verify_range(flash, src, start, page_size, NULL); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 364 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 365 | if (failed && tried++ < MAX_REFLASH_TRIES) { |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame] | 366 | fprintf(stderr, "retrying.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 367 | goto retry; |
| 368 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 369 | if (failed) { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 370 | fprintf(stderr, " page 0x%lx failed!\n", |
| 371 | (d - bios) / page_size); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 372 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 373 | return failed; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 376 | int getaddrmask(struct flashchip *flash) |
| 377 | { |
| 378 | switch (flash->feature_bits & FEATURE_ADDR_MASK) { |
| 379 | case FEATURE_ADDR_FULL: |
| 380 | return MASK_FULL; |
| 381 | break; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 382 | case FEATURE_ADDR_2AA: |
| 383 | return MASK_2AA; |
| 384 | break; |
| 385 | case FEATURE_ADDR_AAA: |
| 386 | return MASK_AAA; |
| 387 | break; |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 388 | default: |
| 389 | fprintf(stderr, "%s called with unknown mask\n", __func__); |
| 390 | return 0; |
| 391 | break; |
| 392 | } |
| 393 | } |
| 394 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 395 | int write_jedec(struct flashchip *flash, uint8_t *buf) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 396 | { |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 397 | int mask; |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 398 | int i, failed = 0; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 399 | int total_size = flash->total_size * 1024; |
| 400 | int page_size = flash->page_size; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 401 | |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 402 | mask = getaddrmask(flash); |
| 403 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 404 | if (erase_chip_jedec(flash)) { |
| 405 | fprintf(stderr,"ERASE FAILED!\n"); |
| 406 | return -1; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 407 | } |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 408 | |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 409 | printf("Programming page: "); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 410 | for (i = 0; i < total_size / page_size; i++) { |
| 411 | printf("%04d at address: 0x%08x", i, i * page_size); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 412 | if (write_page_write_jedec_common(flash, buf + i * page_size, |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 413 | i * page_size, page_size, mask)) |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 414 | failed = 1; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 415 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 416 | } |
| 417 | printf("\n"); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 418 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 419 | return failed; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 420 | } |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 421 | |
| 422 | int write_jedec_1(struct flashchip *flash, uint8_t * buf) |
| 423 | { |
| 424 | int i; |
| 425 | chipaddr bios = flash->virtual_memory; |
| 426 | chipaddr dst = bios; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 427 | int mask; |
| 428 | |
| 429 | mask = getaddrmask(flash); |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 430 | |
| 431 | programmer_delay(10); |
| 432 | if (erase_flash(flash)) { |
| 433 | fprintf(stderr, "ERASE FAILED!\n"); |
| 434 | return -1; |
| 435 | } |
| 436 | |
| 437 | printf("Programming page: "); |
| 438 | for (i = 0; i < flash->total_size; i++) { |
| 439 | if ((i & 0x3) == 0) |
| 440 | printf("address: 0x%08lx", (unsigned long)i * 1024); |
| 441 | |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 442 | write_sector_jedec_common(flash, buf + i * 1024, dst + i * 1024, 1024, mask); |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 443 | |
| 444 | if ((i & 0x3) == 0) |
| 445 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
| 446 | } |
| 447 | |
| 448 | printf("\n"); |
| 449 | return 0; |
| 450 | } |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 451 | |
| 452 | /* erase chip with block_erase() prototype */ |
| 453 | int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr, |
| 454 | unsigned int blocksize) |
| 455 | { |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 456 | int mask; |
| 457 | |
| 458 | mask = getaddrmask(flash); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 459 | if ((addr != 0) || (blocksize != flash->total_size * 1024)) { |
| 460 | fprintf(stderr, "%s called with incorrect arguments\n", |
| 461 | __func__); |
| 462 | return -1; |
| 463 | } |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 464 | return erase_chip_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 465 | } |
| 466 | |
| 467 | int probe_jedec(struct flashchip *flash) |
| 468 | { |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 469 | int mask; |
| 470 | |
| 471 | mask = getaddrmask(flash); |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 472 | return probe_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int size) |
| 476 | { |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 477 | int mask; |
| 478 | |
| 479 | mask = getaddrmask(flash); |
| 480 | return erase_sector_jedec_common(flash, page, size, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int size) |
| 484 | { |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 485 | int mask; |
| 486 | |
| 487 | mask = getaddrmask(flash); |
| 488 | return erase_block_jedec_common(flash, page, size, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | int erase_chip_jedec(struct flashchip *flash) |
| 492 | { |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 493 | int mask; |
| 494 | |
| 495 | mask = getaddrmask(flash); |
| 496 | return erase_chip_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 497 | } |