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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Sean Nelsonc57a9202010-01-04 17:15:23 +00008 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000014 *
Uwe Hermannd1107642007-08-29 17:52:32 +000015 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 *
Uwe Hermannd1107642007-08-29 17:52:32 +000020 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023 */
24
25#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000026
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000027#define MAX_REFLASH_TRIES 0x10
Sean Nelsonc57a9202010-01-04 17:15:23 +000028#define MASK_FULL 0xffff
29#define MASK_2AA 0x7ff
Sean Nelson35727f72010-01-28 23:55:12 +000030#define MASK_AAA 0xfff
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000031
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000032/* Check one byte for odd parity */
33uint8_t oddparity(uint8_t val)
34{
35 val = (val ^ (val >> 4)) & 0xf;
36 val = (val ^ (val >> 2)) & 0x3;
37 return (val ^ (val >> 1)) & 0x1;
38}
39
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000040void toggle_ready_jedec_common(chipaddr dst, int delay)
Uwe Hermann51582f22007-08-23 10:20:40 +000041{
42 unsigned int i = 0;
43 uint8_t tmp1, tmp2;
44
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000045 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000046
47 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000048 if (delay)
49 programmer_delay(delay);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000050 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000051 if (tmp1 == tmp2) {
52 break;
53 }
54 tmp1 = tmp2;
55 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000056 if (i > 0x100000)
57 printf_debug("%s: excessive loops, i=0x%x\n", __func__, i);
58}
59
60void toggle_ready_jedec(chipaddr dst)
61{
62 toggle_ready_jedec_common(dst, 0);
63}
64
65/* Some chips require a minimum delay between toggle bit reads.
66 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
67 * but experiments show that 2 ms are already enough. Pick a safety factor
68 * of 4 and use an 8 ms delay.
69 * Given that erase is slow on all chips, it is recommended to use
70 * toggle_ready_jedec_slow in erase functions.
71 */
72void toggle_ready_jedec_slow(chipaddr dst)
73{
74 toggle_ready_jedec_common(dst, 8 * 1000);
Uwe Hermann51582f22007-08-23 10:20:40 +000075}
76
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000077void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000078{
79 unsigned int i = 0;
80 uint8_t tmp;
81
82 data &= 0x80;
83
84 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000085 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000086 if (tmp == data) {
87 break;
88 }
89 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000090 if (i > 0x100000)
91 printf_debug("%s: excessive loops, i=0x%x\n", __func__, i);
Uwe Hermann51582f22007-08-23 10:20:40 +000092}
93
Sean Nelsonc57a9202010-01-04 17:15:23 +000094void start_program_jedec_common(struct flashchip *flash, unsigned int mask)
Uwe Hermann51582f22007-08-23 10:20:40 +000095{
Sean Nelsonc57a9202010-01-04 17:15:23 +000096 chipaddr bios = flash->virtual_memory;
97 chip_writeb(0xAA, bios + (0x5555 & mask));
98 chip_writeb(0x55, bios + (0x2AAA & mask));
99 chip_writeb(0xA0, bios + (0x5555 & mask));
Uwe Hermann51582f22007-08-23 10:20:40 +0000100}
101
Sean Nelson35727f72010-01-28 23:55:12 +0000102int probe_jedec_common(struct flashchip *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000103{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000104 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +0000105 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000106 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000107 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +0000108 int probe_timing_enter, probe_timing_exit;
109
110 if (flash->probe_timing > 0)
111 probe_timing_enter = probe_timing_exit = flash->probe_timing;
112 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
113 probe_timing_enter = probe_timing_exit = 0;
114 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
115 printf_debug("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000116 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +0000117 probe_timing_enter = 10000;
118 probe_timing_exit = 40;
119 } else {
120 printf("Chip has negative value in probe_timing, failing "
121 "without chip access\n");
122 return 0;
123 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000124
Ollie Lho761bf1b2004-03-20 16:46:10 +0000125 /* Issue JEDEC Product ID Entry command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000126 chip_writeb(0xAA, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000127 if (probe_timing_enter)
128 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000129 chip_writeb(0x55, bios + (0x2AAA & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000130 if (probe_timing_enter)
131 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000132 chip_writeb(0x90, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000133 if (probe_timing_enter)
134 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000135
Ollie Lho761bf1b2004-03-20 16:46:10 +0000136 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000137 id1 = chip_readb(bios);
138 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000139 largeid1 = id1;
140 largeid2 = id2;
141
142 /* Check if it is a continuation ID, this should be a while loop. */
143 if (id1 == 0x7F) {
144 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000145 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000146 largeid1 |= id1;
147 }
148 if (id2 == 0x7F) {
149 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000150 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000151 largeid2 |= id2;
152 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000153
Ollie Lho761bf1b2004-03-20 16:46:10 +0000154 /* Issue JEDEC Product ID Exit command */
Sean Nelson35727f72010-01-28 23:55:12 +0000155 if ((flash->feature_bits & FEATURE_SHORT_RESET) == FEATURE_LONG_RESET)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000156 {
157 chip_writeb(0xAA, bios + (0x5555 & mask));
158 if (probe_timing_exit)
159 programmer_delay(10);
160 chip_writeb(0x55, bios + (0x2AAA & mask));
161 if (probe_timing_exit)
162 programmer_delay(10);
163 }
164 chip_writeb(0xF0, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000165 if (probe_timing_exit)
166 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000167
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000168 printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000169 if (!oddparity(id1))
170 printf_debug(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000171
172 /* Read the product ID location again. We should now see normal flash contents. */
173 flashcontent1 = chip_readb(bios);
174 flashcontent2 = chip_readb(bios + 0x01);
175
176 /* Check if it is a continuation ID, this should be a while loop. */
177 if (flashcontent1 == 0x7F) {
178 flashcontent1 <<= 8;
179 flashcontent1 |= chip_readb(bios + 0x100);
180 }
181 if (flashcontent2 == 0x7F) {
182 flashcontent2 <<= 8;
183 flashcontent2 |= chip_readb(bios + 0x101);
184 }
185
186 if (largeid1 == flashcontent1)
187 printf_debug(", id1 is normal flash content");
188 if (largeid2 == flashcontent2)
189 printf_debug(", id2 is normal flash content");
190
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000191 printf_debug("\n");
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000192 if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id)
193 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000194
Sean Nelsonc57a9202010-01-04 17:15:23 +0000195 if (flash->feature_bits & FEATURE_REGISTERMAP)
196 map_flash_registers(flash);
197
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000198 return 1;
Ollie Lho73eca802004-03-19 22:10:07 +0000199}
200
Sean Nelsonc57a9202010-01-04 17:15:23 +0000201int erase_sector_jedec_common(struct flashchip *flash, unsigned int page,
202 unsigned int pagesize, unsigned int mask)
Ollie Lho73eca802004-03-19 22:10:07 +0000203{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000204 chipaddr bios = flash->virtual_memory;
205
Ollie Lho761bf1b2004-03-20 16:46:10 +0000206 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000207 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000208 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000209 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000210 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000211 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000212 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000213
Sean Nelsonc57a9202010-01-04 17:15:23 +0000214 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000215 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000216 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000217 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000218 chip_writeb(0x30, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000219 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000220
Ollie Lho73eca802004-03-19 22:10:07 +0000221 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000222 toggle_ready_jedec_slow(bios);
Ollie Lho73eca802004-03-19 22:10:07 +0000223
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000224 if (check_erased_range(flash, page, pagesize)) {
225 fprintf(stderr,"ERASE FAILED!\n");
226 return -1;
227 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000228 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000229}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000230
Sean Nelsonc57a9202010-01-04 17:15:23 +0000231int erase_block_jedec_common(struct flashchip *flash, unsigned int block,
232 unsigned int blocksize, unsigned int mask)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000233{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000234 chipaddr bios = flash->virtual_memory;
235
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000236 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000237 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000238 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000239 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000240 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000241 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000242 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000243
Sean Nelsonc57a9202010-01-04 17:15:23 +0000244 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000245 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000246 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000247 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000248 chip_writeb(0x50, bios + block);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000249 programmer_delay(10);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000250
251 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000252 toggle_ready_jedec_slow(bios);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000253
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000254 if (check_erased_range(flash, block, blocksize)) {
255 fprintf(stderr,"ERASE FAILED!\n");
256 return -1;
257 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000258 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000259}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000260
Sean Nelsonc57a9202010-01-04 17:15:23 +0000261int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000262{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000263 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000264 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000265
Ollie Lho761bf1b2004-03-20 16:46:10 +0000266 /* Issue the JEDEC Chip Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000267 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000268 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000269 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000270 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000271 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000272 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000273
Sean Nelsonc57a9202010-01-04 17:15:23 +0000274 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000275 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000276 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000277 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000278 chip_writeb(0x10, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000279 programmer_delay(10);
Ollie Lho73eca802004-03-19 22:10:07 +0000280
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000281 toggle_ready_jedec_slow(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000282
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000283 if (check_erased_range(flash, 0, total_size)) {
284 fprintf(stderr,"ERASE FAILED!\n");
285 return -1;
286 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000287 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000288}
289
Sean Nelsonc57a9202010-01-04 17:15:23 +0000290int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src,
291 chipaddr dst, unsigned int mask)
292{
293 int tried = 0, failed = 0;
294 chipaddr bios = flash->virtual_memory;
295
296 /* If the data is 0xFF, don't program it and don't complain. */
297 if (*src == 0xFF) {
298 return 0;
299 }
300
301retry:
302 /* Issue JEDEC Byte Program command */
303 start_program_jedec_common(flash, mask);
304
305 /* transfer data from source to destination */
306 chip_writeb(*src, dst);
307 toggle_ready_jedec(bios);
308
309 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
310 goto retry;
311 }
312
313 if (tried >= MAX_REFLASH_TRIES)
314 failed = 1;
315
316 return failed;
317}
318
319int write_sector_jedec_common(struct flashchip *flash, uint8_t *src,
320 chipaddr dst, unsigned int page_size, unsigned int mask)
321{
322 int i, failed = 0;
323 chipaddr olddst;
324
325 olddst = dst;
326 for (i = 0; i < page_size; i++) {
327 if (write_byte_program_jedec_common(flash, src, dst, mask))
328 failed = 1;
329 dst++, src++;
330 }
331 if (failed)
332 fprintf(stderr, " writing sector at 0x%lx failed!\n", olddst);
333
334 return failed;
335}
336
337int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src,
338 int start, int page_size, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000339{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000340 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000341 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000342 chipaddr bios = flash->virtual_memory;
343 chipaddr dst = bios + start;
344 chipaddr d = dst;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000345
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000346retry:
Sean Nelsonc57a9202010-01-04 17:15:23 +0000347 /* Issue JEDEC Start Program comand */
348 start_program_jedec_common(flash, mask);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000349
Ollie Lho98bea8a2004-12-07 03:15:51 +0000350 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000351 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000352 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000353 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000354 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000355 dst++;
356 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000357 }
358
Ollie Lho761bf1b2004-03-20 16:46:10 +0000359 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000360
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000361 dst = d;
362 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000363 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000364
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000365 if (failed && tried++ < MAX_REFLASH_TRIES) {
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000366 fprintf(stderr, "retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000367 goto retry;
368 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000369 if (failed) {
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000370 fprintf(stderr, " page 0x%lx failed!\n",
371 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000372 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000373 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000374}
375
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000376int getaddrmask(struct flashchip *flash)
377{
378 switch (flash->feature_bits & FEATURE_ADDR_MASK) {
379 case FEATURE_ADDR_FULL:
380 return MASK_FULL;
381 break;
Sean Nelson35727f72010-01-28 23:55:12 +0000382 case FEATURE_ADDR_2AA:
383 return MASK_2AA;
384 break;
385 case FEATURE_ADDR_AAA:
386 return MASK_AAA;
387 break;
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000388 default:
389 fprintf(stderr, "%s called with unknown mask\n", __func__);
390 return 0;
391 break;
392 }
393}
394
Ollie Lho184a4042005-11-26 21:55:36 +0000395int write_jedec(struct flashchip *flash, uint8_t *buf)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000396{
Sean Nelson35727f72010-01-28 23:55:12 +0000397 int mask;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000398 int i, failed = 0;
Ollie Lho070647d2004-03-22 22:19:17 +0000399 int total_size = flash->total_size * 1024;
400 int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000401
Sean Nelson35727f72010-01-28 23:55:12 +0000402 mask = getaddrmask(flash);
403
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000404 if (erase_chip_jedec(flash)) {
405 fprintf(stderr,"ERASE FAILED!\n");
406 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000407 }
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000408
Uwe Hermanna502dce2007-10-17 23:55:15 +0000409 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000410 for (i = 0; i < total_size / page_size; i++) {
411 printf("%04d at address: 0x%08x", i, i * page_size);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000412 if (write_page_write_jedec_common(flash, buf + i * page_size,
Sean Nelson35727f72010-01-28 23:55:12 +0000413 i * page_size, page_size, mask))
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000414 failed = 1;
Ollie Lho070647d2004-03-22 22:19:17 +0000415 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000416 }
417 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000418
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000419 return failed;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000420}
Michael Karcher1c296ca2009-11-27 17:49:42 +0000421
422int write_jedec_1(struct flashchip *flash, uint8_t * buf)
423{
424 int i;
425 chipaddr bios = flash->virtual_memory;
426 chipaddr dst = bios;
Sean Nelson35727f72010-01-28 23:55:12 +0000427 int mask;
428
429 mask = getaddrmask(flash);
Michael Karcher1c296ca2009-11-27 17:49:42 +0000430
431 programmer_delay(10);
432 if (erase_flash(flash)) {
433 fprintf(stderr, "ERASE FAILED!\n");
434 return -1;
435 }
436
437 printf("Programming page: ");
438 for (i = 0; i < flash->total_size; i++) {
439 if ((i & 0x3) == 0)
440 printf("address: 0x%08lx", (unsigned long)i * 1024);
441
Sean Nelson35727f72010-01-28 23:55:12 +0000442 write_sector_jedec_common(flash, buf + i * 1024, dst + i * 1024, 1024, mask);
Michael Karcher1c296ca2009-11-27 17:49:42 +0000443
444 if ((i & 0x3) == 0)
445 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
446 }
447
448 printf("\n");
449 return 0;
450}
Sean Nelsonc57a9202010-01-04 17:15:23 +0000451
452/* erase chip with block_erase() prototype */
453int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr,
454 unsigned int blocksize)
455{
Sean Nelson35727f72010-01-28 23:55:12 +0000456 int mask;
457
458 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000459 if ((addr != 0) || (blocksize != flash->total_size * 1024)) {
460 fprintf(stderr, "%s called with incorrect arguments\n",
461 __func__);
462 return -1;
463 }
Sean Nelson35727f72010-01-28 23:55:12 +0000464 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000465}
466
467int probe_jedec(struct flashchip *flash)
468{
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000469 int mask;
470
471 mask = getaddrmask(flash);
Sean Nelson35727f72010-01-28 23:55:12 +0000472 return probe_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000473}
474
475int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int size)
476{
Sean Nelson35727f72010-01-28 23:55:12 +0000477 int mask;
478
479 mask = getaddrmask(flash);
480 return erase_sector_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000481}
482
483int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int size)
484{
Sean Nelson35727f72010-01-28 23:55:12 +0000485 int mask;
486
487 mask = getaddrmask(flash);
488 return erase_block_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000489}
490
491int erase_chip_jedec(struct flashchip *flash)
492{
Sean Nelson35727f72010-01-28 23:55:12 +0000493 int mask;
494
495 mask = getaddrmask(flash);
496 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000497}