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Ronald G. Minnichb1934902002-06-11 19:15:55 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnichb1934902002-06-11 19:15:55 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnichb1934902002-06-11 19:15:55 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnichb1934902002-06-11 19:15:55 +000019 */
20
21#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include "chipdrivers.h"
Ronald G. Minnichb1934902002-06-11 19:15:55 +000023
Michael Karcher1c296ca2009-11-27 17:49:42 +000024/* WARNING!
25 This chip uses the standard JEDEC Addresses in 16-bit mode as word
26 addresses. In byte mode, 0xAAA has to be used instead of 0x555 and
27 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC
28 functions. */
29
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000030void write_page_m29f400bt(chipaddr bios, uint8_t *src,
31 chipaddr dst, int page_size)
Uwe Hermann51582f22007-08-23 10:20:40 +000032{
33 int i;
34
35 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000036 chip_writeb(0xAA, bios + 0xAAA);
37 chip_writeb(0x55, bios + 0x555);
38 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000039
40 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000041 chip_writeb(*src, dst);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000042 //chip_writeb(0xF0, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000043 //programmer_delay(5);
Uwe Hermannfd374142007-08-23 15:20:38 +000044 toggle_ready_jedec(dst);
Uwe Hermann51582f22007-08-23 10:20:40 +000045 printf
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000046 ("Value in the flash at address 0x%lx = %#x, want %#x\n",
47 (dst - bios), chip_readb(dst), *src);
Uwe Hermann51582f22007-08-23 10:20:40 +000048 dst++;
49 src++;
50 }
51}
52
Ollie Lho761bf1b2004-03-20 16:46:10 +000053int probe_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000054{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000055 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000056 uint8_t id1, id2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000057
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000058 chip_writeb(0xAA, bios + 0xAAA);
59 chip_writeb(0x55, bios + 0x555);
60 chip_writeb(0x90, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000061
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000062 programmer_delay(10);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000063
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000064 id1 = chip_readb(bios);
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +000065 /* The data sheet says id2 is at (bios + 0x01) and id2 listed in
66 * flash.h does not match. It should be possible to use JEDEC probe.
67 */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000068 id2 = chip_readb(bios + 0x02);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000069
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000070 chip_writeb(0xAA, bios + 0xAAA);
71 chip_writeb(0x55, bios + 0x555);
72 chip_writeb(0xF0, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000073
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000074 programmer_delay(10);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000075
Uwe Hermann04aa59a2009-09-02 22:09:00 +000076 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000077
Ronald G. Minnichb1934902002-06-11 19:15:55 +000078 if (id1 == flash->manufacture_id && id2 == flash->model_id)
79 return 1;
80
81 return 0;
82}
83
Ollie Lho761bf1b2004-03-20 16:46:10 +000084int erase_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000085{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000086 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000087
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000088 chip_writeb(0xAA, bios + 0xAAA);
89 chip_writeb(0x55, bios + 0x555);
90 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000091
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000092 chip_writeb(0xAA, bios + 0xAAA);
93 chip_writeb(0x55, bios + 0x555);
94 chip_writeb(0x10, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000095
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000096 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +000097 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000098
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000099 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
100 fprintf(stderr, "ERASE FAILED!\n");
101 return -1;
102 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000103 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000104}
105
Sean Nelson6b11ad22009-12-23 17:05:59 +0000106int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000107{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000108 chipaddr bios = flash->virtual_memory;
109 chipaddr dst = bios + start;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000110
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000111 chip_writeb(0xAA, bios + 0xAAA);
112 chip_writeb(0x55, bios + 0x555);
113 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000114
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000115 chip_writeb(0xAA, bios + 0xAAA);
116 chip_writeb(0x55, bios + 0x555);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000117 //chip_writeb(0x10, bios + 0xAAA);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000118 chip_writeb(0x30, dst);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000119
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000120 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000121 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000122
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000123 if (check_erased_range(flash, start, len)) {
124 fprintf(stderr, "ERASE FAILED!\n");
125 return -1;
126 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000127 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000128}
129
Sean Nelson6b11ad22009-12-23 17:05:59 +0000130int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen)
131{
132 if ((address != 0) || (blocklen != flash->total_size * 1024)) {
133 fprintf(stderr, "%s called with incorrect arguments\n",
134 __func__);
135 return -1;
136 }
137 return erase_m29f400bt(flash);
138}
139
Ollie Lho184a4042005-11-26 21:55:36 +0000140int write_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000141{
142 int i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000143 int total_size = flash->total_size * 1024;
144 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000145 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000146
147 //erase_m29f400bt (flash);
Uwe Hermanna502dce2007-10-17 23:55:15 +0000148 printf("Programming page:\n ");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000149 /*********************************
150 *Pages for M29F400BT:
151 * 16 0x7c000 0x7ffff TOP
152 * 8 0x7a000 0x7bfff
153 * 8 0x78000 0x79fff
154 * 32 0x70000 0x77fff
155 * 64 0x60000 0x6ffff
156 * 64 0x50000 0x5ffff
157 * 64 0x40000 0x4ffff
158 *---------------------------------
159 * 64 0x30000 0x3ffff
160 * 64 0x20000 0x2ffff
161 * 64 0x10000 0x1ffff
162 * 64 0x00000 0x0ffff BOTTOM
163 *********************************/
Ollie Lho761bf1b2004-03-20 16:46:10 +0000164 printf("total_size/page_size = %d\n", total_size / page_size);
165 for (i = 0; i < (total_size / page_size) - 1; i++) {
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000166 printf("%04d at address: 0x%08x\n", i, i * page_size);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000167 if (block_erase_m29f400bt(flash, i * page_size, page_size)) {
168 fprintf(stderr, "ERASE FAILED!\n");
169 return -1;
170 }
Ollie Lho761bf1b2004-03-20 16:46:10 +0000171 write_page_m29f400bt(bios, buf + i * page_size,
172 bios + i * page_size, page_size);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000173 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000174 }
175
Ollie Lho761bf1b2004-03-20 16:46:10 +0000176 printf("%04d at address: 0x%08x\n", 7, 0x70000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000177 if (block_erase_m29f400bt(flash, 0x70000, 32 * 1024)) {
178 fprintf(stderr, "ERASE FAILED!\n");
179 return -1;
180 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000181 write_page_m29f400bt(bios, buf + 0x70000, bios + 0x70000, 32 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000182
183 printf("%04d at address: 0x%08x\n", 8, 0x78000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000184 if (block_erase_m29f400bt(flash, 0x78000, 8 * 1024)) {
185 fprintf(stderr, "ERASE FAILED!\n");
186 return -1;
187 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000188 write_page_m29f400bt(bios, buf + 0x78000, bios + 0x78000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000189
190 printf("%04d at address: 0x%08x\n", 9, 0x7a000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000191 if (block_erase_m29f400bt(flash, 0x7a000, 8 * 1024)) {
192 fprintf(stderr, "ERASE FAILED!\n");
193 return -1;
194 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000195 write_page_m29f400bt(bios, buf + 0x7a000, bios + 0x7a000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000196
197 printf("%04d at address: 0x%08x\n", 10, 0x7c000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000198 if (block_erase_m29f400bt(flash, 0x7c000, 16 * 1024)) {
199 fprintf(stderr, "ERASE FAILED!\n");
200 return -1;
201 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000202 write_page_m29f400bt(bios, buf + 0x7c000, bios + 0x7c000, 16 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000203
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000204 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000205
Uwe Hermannffec5f32007-08-23 16:08:21 +0000206 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000207}
208
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +0000209int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000210{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000211 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000212
Uwe Hermanna502dce2007-10-17 23:55:15 +0000213 printf("Programming page:\n ");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000214 /*********************************
215 *Pages for M29F400BT:
216 * 16 0x7c000 0x7ffff TOP
217 * 8 0x7a000 0x7bfff
218 * 8 0x78000 0x79fff
219 * 32 0x70000 0x77fff
220 * 64 0x60000 0x6ffff
221 * 64 0x50000 0x5ffff
222 * 64 0x40000 0x4ffff
223 *---------------------------------
224 * 64 0x30000 0x3ffff
225 * 64 0x20000 0x2ffff
226 * 64 0x10000 0x1ffff
227 * 64 0x00000 0x0ffff BOTTOM
228 *********************************/
Ollie Lho761bf1b2004-03-20 16:46:10 +0000229 printf("%04d at address: 0x%08x\n", 7, 0x00000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000230 if (block_erase_m29f400bt(flash, 0x00000, 64 * 1024)) {
231 fprintf(stderr, "ERASE FAILED!\n");
232 return -1;
233 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000234 write_page_m29f400bt(bios, buf + 0x00000, bios + 0x00000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000235
236 printf("%04d at address: 0x%08x\n", 7, 0x10000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000237 if (block_erase_m29f400bt(flash, 0x10000, 64 * 1024)) {
238 fprintf(stderr, "ERASE FAILED!\n");
239 return -1;
240 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000241 write_page_m29f400bt(bios, buf + 0x10000, bios + 0x10000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000242
243 printf("%04d at address: 0x%08x\n", 7, 0x20000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000244 if (block_erase_m29f400bt(flash, 0x20000, 64 * 1024)) {
245 fprintf(stderr, "ERASE FAILED!\n");
246 return -1;
247 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000248 write_page_m29f400bt(bios, buf + 0x20000, bios + 0x20000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000249
250 printf("%04d at address: 0x%08x\n", 7, 0x30000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000251 if (block_erase_m29f400bt(flash, 0x30000, 64 * 1024)) {
252 fprintf(stderr, "ERASE FAILED!\n");
253 return -1;
254 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000255 write_page_m29f400bt(bios, buf + 0x30000, bios + 0x30000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000256
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000257 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000258
Uwe Hermannffec5f32007-08-23 16:08:21 +0000259 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000260}