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Ronald G. Minnichb1934902002-06-11 19:15:55 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnichb1934902002-06-11 19:15:55 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnichb1934902002-06-11 19:15:55 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnichb1934902002-06-11 19:15:55 +000019 */
20
21#include "flash.h"
Ronald G. Minnichb1934902002-06-11 19:15:55 +000022
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000023void protect_m29f400bt(chipaddr bios)
Uwe Hermann51582f22007-08-23 10:20:40 +000024{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000025 chip_writeb(0xAA, bios + 0xAAA);
26 chip_writeb(0x55, bios + 0x555);
27 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000028
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000029 programmer_delay(200);
Uwe Hermann51582f22007-08-23 10:20:40 +000030}
31
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000032void write_page_m29f400bt(chipaddr bios, uint8_t *src,
33 chipaddr dst, int page_size)
Uwe Hermann51582f22007-08-23 10:20:40 +000034{
35 int i;
36
37 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000038 chip_writeb(0xAA, bios + 0xAAA);
39 chip_writeb(0x55, bios + 0x555);
40 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000041
42 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000043 chip_writeb(*src, dst);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000044 //chip_writeb(0xF0, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000045 //programmer_delay(5);
Uwe Hermannfd374142007-08-23 15:20:38 +000046 toggle_ready_jedec(dst);
Uwe Hermann51582f22007-08-23 10:20:40 +000047 printf
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000048 ("Value in the flash at address 0x%lx = %#x, want %#x\n",
49 (dst - bios), chip_readb(dst), *src);
Uwe Hermann51582f22007-08-23 10:20:40 +000050 dst++;
51 src++;
52 }
53}
54
Ollie Lho761bf1b2004-03-20 16:46:10 +000055int probe_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000056{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000057 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000058 uint8_t id1, id2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000059
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000060 chip_writeb(0xAA, bios + 0xAAA);
61 chip_writeb(0x55, bios + 0x555);
62 chip_writeb(0x90, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000063
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000064 programmer_delay(10);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000065
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000066 id1 = chip_readb(bios);
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +000067 /* The data sheet says id2 is at (bios + 0x01) and id2 listed in
68 * flash.h does not match. It should be possible to use JEDEC probe.
69 */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000070 id2 = chip_readb(bios + 0x02);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000071
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000072 chip_writeb(0xAA, bios + 0xAAA);
73 chip_writeb(0x55, bios + 0x555);
74 chip_writeb(0xF0, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000075
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000076 programmer_delay(10);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000077
Peter Stuge5cafc332009-01-25 23:52:45 +000078 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000079
Ronald G. Minnichb1934902002-06-11 19:15:55 +000080 if (id1 == flash->manufacture_id && id2 == flash->model_id)
81 return 1;
82
83 return 0;
84}
85
Ollie Lho761bf1b2004-03-20 16:46:10 +000086int erase_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000087{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000088 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000089
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000090 chip_writeb(0xAA, bios + 0xAAA);
91 chip_writeb(0x55, bios + 0x555);
92 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000093
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000094 chip_writeb(0xAA, bios + 0xAAA);
95 chip_writeb(0x55, bios + 0x555);
96 chip_writeb(0x10, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000097
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000098 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +000099 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000100
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000101 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
102 fprintf(stderr, "ERASE FAILED!\n");
103 return -1;
104 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000105 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000106}
107
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000108int block_erase_m29f400bt(struct flashchip *flash, int start, int len)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000109{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000110 chipaddr bios = flash->virtual_memory;
111 chipaddr dst = bios + start;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000112
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000113 chip_writeb(0xAA, bios + 0xAAA);
114 chip_writeb(0x55, bios + 0x555);
115 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000116
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000117 chip_writeb(0xAA, bios + 0xAAA);
118 chip_writeb(0x55, bios + 0x555);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000119 //chip_writeb(0x10, bios + 0xAAA);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000120 chip_writeb(0x30, dst);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000121
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000122 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000123 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000124
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000125 if (check_erased_range(flash, start, len)) {
126 fprintf(stderr, "ERASE FAILED!\n");
127 return -1;
128 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000129 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000130}
131
Ollie Lho184a4042005-11-26 21:55:36 +0000132int write_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000133{
134 int i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000135 int total_size = flash->total_size * 1024;
136 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000137 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000138
139 //erase_m29f400bt (flash);
Uwe Hermanna502dce2007-10-17 23:55:15 +0000140 printf("Programming page:\n ");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000141 /*********************************
142 *Pages for M29F400BT:
143 * 16 0x7c000 0x7ffff TOP
144 * 8 0x7a000 0x7bfff
145 * 8 0x78000 0x79fff
146 * 32 0x70000 0x77fff
147 * 64 0x60000 0x6ffff
148 * 64 0x50000 0x5ffff
149 * 64 0x40000 0x4ffff
150 *---------------------------------
151 * 64 0x30000 0x3ffff
152 * 64 0x20000 0x2ffff
153 * 64 0x10000 0x1ffff
154 * 64 0x00000 0x0ffff BOTTOM
155 *********************************/
Ollie Lho761bf1b2004-03-20 16:46:10 +0000156 printf("total_size/page_size = %d\n", total_size / page_size);
157 for (i = 0; i < (total_size / page_size) - 1; i++) {
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000158 printf("%04d at address: 0x%08x\n", i, i * page_size);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000159 if (block_erase_m29f400bt(flash, i * page_size, page_size)) {
160 fprintf(stderr, "ERASE FAILED!\n");
161 return -1;
162 }
Ollie Lho761bf1b2004-03-20 16:46:10 +0000163 write_page_m29f400bt(bios, buf + i * page_size,
164 bios + i * page_size, page_size);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000165 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000166 }
167
Ollie Lho761bf1b2004-03-20 16:46:10 +0000168 printf("%04d at address: 0x%08x\n", 7, 0x70000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000169 if (block_erase_m29f400bt(flash, 0x70000, 32 * 1024)) {
170 fprintf(stderr, "ERASE FAILED!\n");
171 return -1;
172 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000173 write_page_m29f400bt(bios, buf + 0x70000, bios + 0x70000, 32 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000174
175 printf("%04d at address: 0x%08x\n", 8, 0x78000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000176 if (block_erase_m29f400bt(flash, 0x78000, 8 * 1024)) {
177 fprintf(stderr, "ERASE FAILED!\n");
178 return -1;
179 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000180 write_page_m29f400bt(bios, buf + 0x78000, bios + 0x78000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000181
182 printf("%04d at address: 0x%08x\n", 9, 0x7a000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000183 if (block_erase_m29f400bt(flash, 0x7a000, 8 * 1024)) {
184 fprintf(stderr, "ERASE FAILED!\n");
185 return -1;
186 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000187 write_page_m29f400bt(bios, buf + 0x7a000, bios + 0x7a000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000188
189 printf("%04d at address: 0x%08x\n", 10, 0x7c000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000190 if (block_erase_m29f400bt(flash, 0x7c000, 16 * 1024)) {
191 fprintf(stderr, "ERASE FAILED!\n");
192 return -1;
193 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000194 write_page_m29f400bt(bios, buf + 0x7c000, bios + 0x7c000, 16 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000195
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000196 printf("\n");
197 //protect_m29f400bt (bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000198
Uwe Hermannffec5f32007-08-23 16:08:21 +0000199 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000200}
201
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +0000202int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000203{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000204 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000205
Uwe Hermanna502dce2007-10-17 23:55:15 +0000206 printf("Programming page:\n ");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000207 /*********************************
208 *Pages for M29F400BT:
209 * 16 0x7c000 0x7ffff TOP
210 * 8 0x7a000 0x7bfff
211 * 8 0x78000 0x79fff
212 * 32 0x70000 0x77fff
213 * 64 0x60000 0x6ffff
214 * 64 0x50000 0x5ffff
215 * 64 0x40000 0x4ffff
216 *---------------------------------
217 * 64 0x30000 0x3ffff
218 * 64 0x20000 0x2ffff
219 * 64 0x10000 0x1ffff
220 * 64 0x00000 0x0ffff BOTTOM
221 *********************************/
Ollie Lho761bf1b2004-03-20 16:46:10 +0000222 printf("%04d at address: 0x%08x\n", 7, 0x00000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000223 if (block_erase_m29f400bt(flash, 0x00000, 64 * 1024)) {
224 fprintf(stderr, "ERASE FAILED!\n");
225 return -1;
226 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000227 write_page_m29f400bt(bios, buf + 0x00000, bios + 0x00000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000228
229 printf("%04d at address: 0x%08x\n", 7, 0x10000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000230 if (block_erase_m29f400bt(flash, 0x10000, 64 * 1024)) {
231 fprintf(stderr, "ERASE FAILED!\n");
232 return -1;
233 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000234 write_page_m29f400bt(bios, buf + 0x10000, bios + 0x10000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000235
236 printf("%04d at address: 0x%08x\n", 7, 0x20000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000237 if (block_erase_m29f400bt(flash, 0x20000, 64 * 1024)) {
238 fprintf(stderr, "ERASE FAILED!\n");
239 return -1;
240 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000241 write_page_m29f400bt(bios, buf + 0x20000, bios + 0x20000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000242
243 printf("%04d at address: 0x%08x\n", 7, 0x30000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000244 if (block_erase_m29f400bt(flash, 0x30000, 64 * 1024)) {
245 fprintf(stderr, "ERASE FAILED!\n");
246 return -1;
247 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000248 write_page_m29f400bt(bios, buf + 0x30000, bios + 0x30000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000249
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000250 printf("\n");
251 //protect_m29f400bt (bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000252
Uwe Hermannffec5f32007-08-23 16:08:21 +0000253 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000254}