Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 17 | #if defined(__i386__) || defined(__x86_64__) |
| 18 | |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 19 | #include <stdlib.h> |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 20 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 21 | #include "programmer.h" |
Patrick Georgi | 32508eb | 2012-07-20 20:35:14 +0000 | [diff] [blame] | 22 | #include "hwaccess.h" |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 23 | |
| 24 | #define BIOS_ROM_ADDR 0x04 |
| 25 | #define BIOS_ROM_DATA 0x08 |
| 26 | #define INT_STATUS 0x0e |
Uwe Hermann | 8403ccb | 2009-05-16 21:39:19 +0000 | [diff] [blame] | 27 | #define INTERNAL_CONFIG 0x00 |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 28 | #define SELECT_REG_WINDOW 0x800 |
| 29 | |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 30 | #define PCI_VENDOR_ID_3COM 0x10b7 |
| 31 | |
Stefan Tauner | 0ccec8f | 2014-06-01 23:49:03 +0000 | [diff] [blame] | 32 | static uint32_t io_base_addr = 0; |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 33 | static uint32_t internal_conf; |
| 34 | static uint16_t id; |
Uwe Hermann | 8403ccb | 2009-05-16 21:39:19 +0000 | [diff] [blame] | 35 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 36 | static const struct dev_entry nics_3com[] = { |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 37 | /* 3C90xB */ |
Michael Karcher | 8448639 | 2010-02-24 00:04:40 +0000 | [diff] [blame] | 38 | {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"}, |
| 39 | {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" }, |
| 40 | {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" }, |
| 41 | {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" }, |
| 42 | {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, |
| 43 | {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" }, |
| 44 | {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" }, |
| 45 | {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" }, |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 46 | |
| 47 | /* 3C905C */ |
Michael Karcher | 8448639 | 2010-02-24 00:04:40 +0000 | [diff] [blame] | 48 | {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 49 | |
| 50 | /* 3C980C */ |
Michael Karcher | 8448639 | 2010-02-24 00:04:40 +0000 | [diff] [blame] | 51 | {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" }, |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 52 | |
Carl-Daniel Hailfinger | 1c6d2ff | 2012-08-27 00:44:42 +0000 | [diff] [blame] | 53 | {0}, |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 54 | }; |
| 55 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 56 | static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, |
| 57 | chipaddr addr); |
| 58 | static uint8_t nic3com_chip_readb(const struct flashctx *flash, |
| 59 | const chipaddr addr); |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 60 | static const struct par_master par_master_nic3com = { |
Thomas Heijligen | 43040f2 | 2022-06-23 14:38:35 +0200 | [diff] [blame] | 61 | .chip_readb = nic3com_chip_readb, |
| 62 | .chip_readw = fallback_chip_readw, |
| 63 | .chip_readl = fallback_chip_readl, |
| 64 | .chip_readn = fallback_chip_readn, |
| 65 | .chip_writeb = nic3com_chip_writeb, |
| 66 | .chip_writew = fallback_chip_writew, |
| 67 | .chip_writel = fallback_chip_writel, |
| 68 | .chip_writen = fallback_chip_writen, |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 69 | }; |
| 70 | |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 71 | static int nic3com_shutdown(void *data) |
| 72 | { |
| 73 | /* 3COM 3C90xB cards need a special fixup. */ |
| 74 | if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 |
| 75 | || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { |
| 76 | /* Select register window 3 and restore the receiver status. */ |
| 77 | OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); |
| 78 | OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG); |
| 79 | } |
| 80 | |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 81 | return 0; |
| 82 | } |
| 83 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 84 | static int nic3com_init(void) |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 85 | { |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 86 | struct pci_dev *dev = NULL; |
| 87 | |
Carl-Daniel Hailfinger | d6bb828 | 2012-07-21 17:27:08 +0000 | [diff] [blame] | 88 | if (rget_io_perms()) |
| 89 | return 1; |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 90 | |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 91 | dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0); |
| 92 | if (!dev) |
| 93 | return 1; |
Carl-Daniel Hailfinger | 744132a | 2010-07-06 09:55:48 +0000 | [diff] [blame] | 94 | |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 95 | io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); |
Niklas Söderlund | 89edf36 | 2013-08-23 23:29:23 +0000 | [diff] [blame] | 96 | if (!io_base_addr) |
| 97 | return 1; |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 98 | |
| 99 | id = dev->device_id; |
Uwe Hermann | 8403ccb | 2009-05-16 21:39:19 +0000 | [diff] [blame] | 100 | |
| 101 | /* 3COM 3C90xB cards need a special fixup. */ |
| 102 | if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 |
Maciej Pijanka | bc2bbd2 | 2009-06-02 16:45:59 +0000 | [diff] [blame] | 103 | || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { |
Uwe Hermann | 8403ccb | 2009-05-16 21:39:19 +0000 | [diff] [blame] | 104 | /* Select register window 3 and save the receiver status. */ |
| 105 | OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); |
| 106 | internal_conf = INL(io_base_addr + INTERNAL_CONFIG); |
| 107 | |
| 108 | /* Set receiver type to MII for full BIOS ROM access. */ |
| 109 | OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr); |
| 110 | } |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 111 | |
| 112 | /* |
| 113 | * The lowest 16 bytes of the I/O mapped register space of (most) 3COM |
| 114 | * cards form a 'register window' into one of multiple (usually 8) |
| 115 | * register banks. For 3C90xB/3C90xC we need register window/bank 0. |
| 116 | */ |
| 117 | OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); |
| 118 | |
David Hendricks | 8bb2021 | 2011-06-14 01:35:36 +0000 | [diff] [blame] | 119 | if (register_shutdown(nic3com_shutdown, NULL)) |
| 120 | return 1; |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 121 | |
| 122 | max_rom_decode.parallel = 128 * 1024; |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 123 | register_par_master(&par_master_nic3com, BUS_PARALLEL); |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 124 | |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 128 | static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, |
| 129 | chipaddr addr) |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 130 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 131 | OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 132 | OUTB(val, io_base_addr + BIOS_ROM_DATA); |
| 133 | } |
| 134 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 135 | static uint8_t nic3com_chip_readb(const struct flashctx *flash, |
| 136 | const chipaddr addr) |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 137 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 138 | OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); |
Uwe Hermann | c7e8a0c | 2009-05-19 14:14:21 +0000 | [diff] [blame] | 139 | return INB(io_base_addr + BIOS_ROM_DATA); |
Uwe Hermann | b4dcb71 | 2009-05-13 11:36:06 +0000 | [diff] [blame] | 140 | } |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 141 | |
Thomas Heijligen | cc853d8 | 2021-05-04 15:32:17 +0200 | [diff] [blame] | 142 | const struct programmer_entry programmer_nic3com = { |
| 143 | .name = "nic3com", |
| 144 | .type = PCI, |
| 145 | .devs.dev = nics_3com, |
| 146 | .init = nic3com_init, |
| 147 | .map_flash_region = fallback_map, |
| 148 | .unmap_flash_region = fallback_unmap, |
| 149 | .delay = internal_delay, |
| 150 | }; |
| 151 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 152 | #else |
| 153 | #error PCI port I/O access is not supported on this architecture yet. |
| 154 | #endif |