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Ronald G. Minnichb1934902002-06-11 19:15:55 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnichb1934902002-06-11 19:15:55 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnichb1934902002-06-11 19:15:55 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnichb1934902002-06-11 19:15:55 +000019 */
20
21#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include "chipdrivers.h"
Ronald G. Minnichb1934902002-06-11 19:15:55 +000023
Michael Karcher1c296ca2009-11-27 17:49:42 +000024/* WARNING!
25 This chip uses the standard JEDEC Addresses in 16-bit mode as word
26 addresses. In byte mode, 0xAAA has to be used instead of 0x555 and
27 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC
28 functions. */
29
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +000030/* chunksize is 1 */
Stefan Taunerd196e7c2011-09-18 00:41:33 +000031int write_m29f400bt(struct flashchip *flash, uint8_t *src, unsigned int start, unsigned int len)
Uwe Hermann51582f22007-08-23 10:20:40 +000032{
33 int i;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000034 chipaddr bios = flash->virtual_memory;
35 chipaddr dst = flash->virtual_memory + start;
Uwe Hermann51582f22007-08-23 10:20:40 +000036
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000037 for (i = 0; i < len; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000038 chip_writeb(0xAA, bios + 0xAAA);
39 chip_writeb(0x55, bios + 0x555);
40 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000041
42 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000043 chip_writeb(*src, dst);
Uwe Hermannfd374142007-08-23 15:20:38 +000044 toggle_ready_jedec(dst);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000045#if 0
46 /* We only want to print something in the error case. */
Sean Nelsoned479d22010-03-24 23:14:32 +000047 msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000048 (dst - bios), chip_readb(dst), *src);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000049#endif
Uwe Hermann51582f22007-08-23 10:20:40 +000050 dst++;
51 src++;
52 }
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000053
54 /* FIXME: Ignore errors for now. */
55 return 0;
Uwe Hermann51582f22007-08-23 10:20:40 +000056}
57
Ollie Lho761bf1b2004-03-20 16:46:10 +000058int probe_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000059{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000060 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000061 uint8_t id1, id2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000062
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000063 chip_writeb(0xAA, bios + 0xAAA);
64 chip_writeb(0x55, bios + 0x555);
65 chip_writeb(0x90, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000066
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000067 programmer_delay(10);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000068
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000069 id1 = chip_readb(bios);
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +000070 /* The data sheet says id2 is at (bios + 0x01) and id2 listed in
71 * flash.h does not match. It should be possible to use JEDEC probe.
72 */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000073 id2 = chip_readb(bios + 0x02);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000074
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000075 chip_writeb(0xAA, bios + 0xAAA);
76 chip_writeb(0x55, bios + 0x555);
77 chip_writeb(0xF0, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000078
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000079 programmer_delay(10);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000080
Sean Nelsoned479d22010-03-24 23:14:32 +000081 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000082
Ronald G. Minnichb1934902002-06-11 19:15:55 +000083 if (id1 == flash->manufacture_id && id2 == flash->model_id)
84 return 1;
85
86 return 0;
87}
88
Ollie Lho761bf1b2004-03-20 16:46:10 +000089int erase_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000090{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000091 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000092
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000093 chip_writeb(0xAA, bios + 0xAAA);
94 chip_writeb(0x55, bios + 0x555);
95 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000096
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000097 chip_writeb(0xAA, bios + 0xAAA);
98 chip_writeb(0x55, bios + 0x555);
99 chip_writeb(0x10, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000100
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000101 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000102 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000103
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000104 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000105 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000106}
107
Sean Nelson6b11ad22009-12-23 17:05:59 +0000108int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000109{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000110 chipaddr bios = flash->virtual_memory;
111 chipaddr dst = bios + start;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000112
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000113 chip_writeb(0xAA, bios + 0xAAA);
114 chip_writeb(0x55, bios + 0x555);
115 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000116
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000117 chip_writeb(0xAA, bios + 0xAAA);
118 chip_writeb(0x55, bios + 0x555);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000119 chip_writeb(0x30, dst);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000120
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000121 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000122 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000123
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000124 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000125 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000126}
127
Sean Nelson6b11ad22009-12-23 17:05:59 +0000128int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen)
129{
130 if ((address != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000131 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson6b11ad22009-12-23 17:05:59 +0000132 __func__);
133 return -1;
134 }
135 return erase_m29f400bt(flash);
136}