blob: 3e0263cb40fb35863dc95f9ceea65d9f2f269af2 [file] [log] [blame]
Andrew Morganc29c2e72010-06-07 22:37:54 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Andrew Morganc29c2e72010-06-07 22:37:54 +000015 */
16
Andrew Morganc29c2e72010-06-07 22:37:54 +000017#include <stdlib.h>
18#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000019#include "programmer.h"
Thomas Heijligena0655202021-12-14 16:36:05 +010020#include "hwaccess_x86_io.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010021#include "platform/pci.h"
Andrew Morganc29c2e72010-06-07 22:37:54 +000022
23#define PCI_VENDOR_ID_NATSEMI 0x100b
24
25#define BOOT_ROM_ADDR 0x50
26#define BOOT_ROM_DATA 0x54
27
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000028static uint32_t io_base_addr = 0;
Thomas Heijligencc853d82021-05-04 15:32:17 +020029static const struct dev_entry nics_natsemi[] = {
Andrew Morganc29c2e72010-06-07 22:37:54 +000030 {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
31 {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000032
33 {0},
Andrew Morganc29c2e72010-06-07 22:37:54 +000034};
35
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000036static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
37 chipaddr addr);
38static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
39 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000040static const struct par_master par_master_nicnatsemi = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020041 .chip_readb = nicnatsemi_chip_readb,
42 .chip_readw = fallback_chip_readw,
43 .chip_readl = fallback_chip_readl,
44 .chip_readn = fallback_chip_readn,
45 .chip_writeb = nicnatsemi_chip_writeb,
46 .chip_writew = fallback_chip_writew,
47 .chip_writel = fallback_chip_writel,
48 .chip_writen = fallback_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000049};
50
Thomas Heijligencc853d82021-05-04 15:32:17 +020051static int nicnatsemi_init(void)
Andrew Morganc29c2e72010-06-07 22:37:54 +000052{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000053 struct pci_dev *dev = NULL;
54
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000055 if (rget_io_perms())
56 return 1;
Andrew Morganc29c2e72010-06-07 22:37:54 +000057
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000058 dev = pcidev_init(nics_natsemi, PCI_BASE_ADDRESS_0);
59 if (!dev)
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000060 return 1;
Andrew Morganc29c2e72010-06-07 22:37:54 +000061
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000062 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000063 if (!io_base_addr)
64 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000065
Andrew Morgan74a828a2010-07-21 15:12:07 +000066 /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
67 * in another. My NIC has MA16 connected to A16 on the boot ROM socket
68 * so I'm assuming it is accessible. If not then next line wants to be
69 * max_rom_decode.parallel = 65536; and the mask in the read/write
70 * functions below wants to be 0x0000FFFF.
71 */
72 max_rom_decode.parallel = 131072;
Anastasia Klimchukc1f2a472021-08-27 15:47:46 +100073 return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, NULL);
Andrew Morganc29c2e72010-06-07 22:37:54 +000074}
75
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000076static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
77 chipaddr addr)
Andrew Morganc29c2e72010-06-07 22:37:54 +000078{
Andrew Morgan74a828a2010-07-21 15:12:07 +000079 OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
Andrew Morganc29c2e72010-06-07 22:37:54 +000080 /*
81 * The datasheet requires 32 bit accesses to this register, but it seems
82 * that requirement might only apply if the register is memory mapped.
David Borg243ec632010-08-08 17:04:21 +000083 * Bits 8-31 of this register are apparently don't care, and if this
84 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
Andrew Morganc29c2e72010-06-07 22:37:54 +000085 * register seem to work fine. Due to that, we ignore the advice in the
86 * data sheet.
87 */
88 OUTB(val, io_base_addr + BOOT_ROM_DATA);
89}
90
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000091static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
92 const chipaddr addr)
Andrew Morganc29c2e72010-06-07 22:37:54 +000093{
Andrew Morgan74a828a2010-07-21 15:12:07 +000094 OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
Andrew Morganc29c2e72010-06-07 22:37:54 +000095 /*
96 * The datasheet requires 32 bit accesses to this register, but it seems
97 * that requirement might only apply if the register is memory mapped.
David Borg243ec632010-08-08 17:04:21 +000098 * Bits 8-31 of this register are apparently don't care, and if this
99 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
Andrew Morganc29c2e72010-06-07 22:37:54 +0000100 * register seem to work fine. Due to that, we ignore the advice in the
101 * data sheet.
102 */
103 return INB(io_base_addr + BOOT_ROM_DATA);
104}
105
Thomas Heijligencc853d82021-05-04 15:32:17 +0200106const struct programmer_entry programmer_nicnatsemi = {
107 .name = "nicnatsemi",
108 .type = PCI,
109 .devs.dev = nics_natsemi,
110 .init = nicnatsemi_init,
111 .map_flash_region = fallback_map,
112 .unmap_flash_region = fallback_unmap,
113 .delay = internal_delay,
114};