programmer_table: move each entry to the associated programmer source
Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71373
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/nicnatsemi.c b/nicnatsemi.c
index 085768d..c134edb 100644
--- a/nicnatsemi.c
+++ b/nicnatsemi.c
@@ -27,7 +27,7 @@
#define BOOT_ROM_DATA 0x54
static uint32_t io_base_addr = 0;
-const struct dev_entry nics_natsemi[] = {
+static const struct dev_entry nics_natsemi[] = {
{0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
{0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
@@ -49,7 +49,7 @@
.chip_writen = fallback_chip_writen,
};
-int nicnatsemi_init(void)
+static int nicnatsemi_init(void)
{
struct pci_dev *dev = NULL;
@@ -106,6 +106,16 @@
return INB(io_base_addr + BOOT_ROM_DATA);
}
+const struct programmer_entry programmer_nicnatsemi = {
+ .name = "nicnatsemi",
+ .type = PCI,
+ .devs.dev = nics_natsemi,
+ .init = nicnatsemi_init,
+ .map_flash_region = fallback_map,
+ .unmap_flash_region = fallback_unmap,
+ .delay = internal_delay,
+};
+
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif