blob: acefddb5ea7a865f736de423982e7f823edb3a15 [file] [log] [blame]
Andrew Morganc29c2e72010-06-07 22:37:54 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#if defined(__i386__) || defined(__x86_64__)
22
23#include <stdlib.h>
24#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000025#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000026#include "hwaccess.h"
Andrew Morganc29c2e72010-06-07 22:37:54 +000027
28#define PCI_VENDOR_ID_NATSEMI 0x100b
29
30#define BOOT_ROM_ADDR 0x50
31#define BOOT_ROM_DATA 0x54
32
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000033static uint32_t io_base_addr = 0;
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000034const struct dev_entry nics_natsemi[] = {
Andrew Morganc29c2e72010-06-07 22:37:54 +000035 {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
36 {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000037
38 {0},
Andrew Morganc29c2e72010-06-07 22:37:54 +000039};
40
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000041static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
42 chipaddr addr);
43static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
44 const chipaddr addr);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000045static const struct par_programmer par_programmer_nicnatsemi = {
46 .chip_readb = nicnatsemi_chip_readb,
47 .chip_readw = fallback_chip_readw,
48 .chip_readl = fallback_chip_readl,
49 .chip_readn = fallback_chip_readn,
50 .chip_writeb = nicnatsemi_chip_writeb,
51 .chip_writew = fallback_chip_writew,
52 .chip_writel = fallback_chip_writel,
53 .chip_writen = fallback_chip_writen,
54};
55
Andrew Morganc29c2e72010-06-07 22:37:54 +000056int nicnatsemi_init(void)
57{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000058 struct pci_dev *dev = NULL;
59
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000060 if (rget_io_perms())
61 return 1;
Andrew Morganc29c2e72010-06-07 22:37:54 +000062
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000063 dev = pcidev_init(nics_natsemi, PCI_BASE_ADDRESS_0);
64 if (!dev)
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000065 return 1;
Andrew Morganc29c2e72010-06-07 22:37:54 +000066
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000067 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000068 if (!io_base_addr)
69 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000070
Andrew Morgan74a828a2010-07-21 15:12:07 +000071 /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
72 * in another. My NIC has MA16 connected to A16 on the boot ROM socket
73 * so I'm assuming it is accessible. If not then next line wants to be
74 * max_rom_decode.parallel = 65536; and the mask in the read/write
75 * functions below wants to be 0x0000FFFF.
76 */
77 max_rom_decode.parallel = 131072;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000078 register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL);
Andrew Morgan74a828a2010-07-21 15:12:07 +000079
Andrew Morganc29c2e72010-06-07 22:37:54 +000080 return 0;
81}
82
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000083static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
84 chipaddr addr)
Andrew Morganc29c2e72010-06-07 22:37:54 +000085{
Andrew Morgan74a828a2010-07-21 15:12:07 +000086 OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
Andrew Morganc29c2e72010-06-07 22:37:54 +000087 /*
88 * The datasheet requires 32 bit accesses to this register, but it seems
89 * that requirement might only apply if the register is memory mapped.
David Borg243ec632010-08-08 17:04:21 +000090 * Bits 8-31 of this register are apparently don't care, and if this
91 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
Andrew Morganc29c2e72010-06-07 22:37:54 +000092 * register seem to work fine. Due to that, we ignore the advice in the
93 * data sheet.
94 */
95 OUTB(val, io_base_addr + BOOT_ROM_DATA);
96}
97
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000098static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
99 const chipaddr addr)
Andrew Morganc29c2e72010-06-07 22:37:54 +0000100{
Andrew Morgan74a828a2010-07-21 15:12:07 +0000101 OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
Andrew Morganc29c2e72010-06-07 22:37:54 +0000102 /*
103 * The datasheet requires 32 bit accesses to this register, but it seems
104 * that requirement might only apply if the register is memory mapped.
David Borg243ec632010-08-08 17:04:21 +0000105 * Bits 8-31 of this register are apparently don't care, and if this
106 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
Andrew Morganc29c2e72010-06-07 22:37:54 +0000107 * register seem to work fine. Due to that, we ignore the advice in the
108 * data sheet.
109 */
110 return INB(io_base_addr + BOOT_ROM_DATA);
111}
112
113#else
114#error PCI port I/O access is not supported on this architecture yet.
115#endif