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Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the ITE IT87* SPI specific routines
24 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000028#include <string.h>
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +000029#include <stdlib.h>
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000030#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000031#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000032#include "programmer.h"
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000033#include "spi.h"
34
35#define ITE_SUPERIO_PORT1 0x2e
36#define ITE_SUPERIO_PORT2 0x4e
37
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000038uint16_t it8716f_flashport = 0;
39/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000040static int fast_spi = 1;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000041
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000042/* Helper functions for most recent ITE IT87xx Super I/O chips */
43#define CHIP_ID_BYTE1_REG 0x20
44#define CHIP_ID_BYTE2_REG 0x21
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000045void enter_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000046{
Andriy Gapon65c1b862008-05-22 13:22:45 +000047 OUTB(0x87, port);
48 OUTB(0x01, port);
49 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000050 if (port == ITE_SUPERIO_PORT1)
Andriy Gapon65c1b862008-05-22 13:22:45 +000051 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000052 else
Andriy Gapon65c1b862008-05-22 13:22:45 +000053 OUTB(0xaa, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000054}
55
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056void exit_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000057{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058 sio_write(port, 0x02, 0x02);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000059}
60
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000061uint16_t probe_id_ite(uint16_t port)
62{
63 uint16_t id;
64
65 enter_conf_mode_ite(port);
66 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
67 id |= sio_read(port, CHIP_ID_BYTE2_REG);
68 exit_conf_mode_ite(port);
69
70 return id;
71}
72
73struct superio probe_superio_ite(void)
74{
75 struct superio ret = {};
76 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
77 uint16_t *i = ite_ports;
78
79 ret.vendor = SUPERIO_VENDOR_ITE;
80 for (; *i; i++) {
81 ret.port = *i;
82 ret.model = probe_id_ite(ret.port);
83 switch (ret.model >> 8) {
84 case 0x82:
85 case 0x86:
86 case 0x87:
Uwe Hermann431f4f72010-09-05 12:41:25 +000087 msg_pinfo("Found ITE Super I/O, ID 0x%04hx.\n",
88 ret.model);
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000089 return ret;
90 }
91 }
92
93 /* No good ID found. */
94 ret.vendor = SUPERIO_VENDOR_NONE;
95 ret.port = 0;
96 ret.model = 0;
97 return ret;
98}
99
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000100static uint16_t it87spi_probe(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000101{
102 uint8_t tmp = 0;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000103 char *portpos = NULL;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000104 uint16_t flashport = 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000105
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000106 enter_conf_mode_ite(port);
107 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
108 tmp = sio_read(port, 0x24) & 0xFE;
109 /* If IT87SPI was not explicitly selected, we want to check
110 * quickly if LPC->SPI translation is active.
111 */
112 if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) {
113 msg_pdbg("No IT87* serial flash segment enabled.\n");
114 exit_conf_mode_ite(port);
115 /* Nothing to do. */
116 return 1;
117 }
118 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
119 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
120 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
121 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
122 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
123 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
124 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
125 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
126 msg_pdbg("LPC write to serial flash %sabled\n",
127 (tmp & 1 << 4) ? "en" : "dis");
128 /* The LPC->SPI force write enable below only makes sense for
129 * non-programmer mode.
130 */
131 /* If any serial flash segment is enabled, enable writing. */
132 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
133 msg_pdbg("Enabling LPC write to serial flash\n");
134 tmp |= 1 << 4;
135 sio_write(port, 0x24, tmp);
136 }
137 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
138 /* LDN 0x7, reg 0x64/0x65 */
139 sio_write(port, 0x07, 0x7);
140 flashport = sio_read(port, 0x64) << 8;
141 flashport |= sio_read(port, 0x65);
142 msg_pdbg("Serial flash port 0x%04x\n", flashport);
143 /* Non-default port requested? */
144 portpos = extract_programmer_param("it87spiport");
145 if (portpos) {
146 char *endptr = NULL;
147 unsigned long forced_flashport;
148 forced_flashport = strtoul(portpos, &endptr, 0);
149 /* Port 0, port >0x1000, unaligned ports and garbage strings
150 * are rejected.
Carl-Daniel Hailfinger01f3ef42010-03-25 02:50:40 +0000151 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000152 if (!forced_flashport || (forced_flashport >= 0x1000) ||
153 (forced_flashport & 0x7) || (*endptr != '\0')) {
154 /* Using ports below 0x100 is a really bad idea, and
155 * should only be done if no port between 0x100 and
156 * 0xff8 works due to routing issues.
157 */
158 msg_perr("Error: it87spiport specified, but no valid "
159 "port specified.\nPort must be a multiple of "
160 "0x8 and lie between 0x100 and 0xff8.\n");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000161 free(portpos);
162 /* FIXME: Return failure here once it87spi_common_init()
163 * can handle the return value sanely.
164 */
165 exit(1);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000166 } else {
167 flashport = (uint16_t)forced_flashport;
168 msg_pinfo("Forcing serial flash port 0x%04x\n",
169 flashport);
170 sio_write(port, 0x64, (flashport >> 8));
171 sio_write(port, 0x65, (flashport & 0xff));
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000172 }
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000173 }
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000174 free(portpos);
175 exit_conf_mode_ite(port);
176 it8716f_flashport = flashport;
177 if (buses_supported & CHIP_BUSTYPE_SPI)
178 msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
179 spi_controller = SPI_CONTROLLER_IT87XX;
180 buses_supported |= CHIP_BUSTYPE_SPI;
181 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000182}
183
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000184int init_superio_ite(void)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000185{
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000186 if (superio.vendor != SUPERIO_VENDOR_ITE)
187 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000188
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000189 switch (superio.model) {
190 case 0x8705:
191 return it8705f_write_enable(superio.port);
192 break;
193 case 0x8716:
194 case 0x8718:
195 case 0x8720:
196 return it87spi_probe(superio.port);
197 break;
198 default:
199 msg_pdbg("Super I/O ID 0x%04hx is not on the list of flash "
200 "capable controllers.\n", superio.model);
201 }
202 return 1;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000203}
204
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000205
206int it87spi_init(void)
207{
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000208 int ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000209
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000210 get_io_perms();
Uwe Hermann43959702010-03-13 17:28:29 +0000211 /* Probe for the Super I/O chip and fill global struct superio. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000212 probe_superio();
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000213 ret = init_superio_ite();
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000214 if (!ret) {
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000215 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000216 } else {
217 buses_supported = CHIP_BUSTYPE_NONE;
218 }
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000219 return ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000220}
221
Uwe Hermann394131e2008-10-18 21:14:13 +0000222/*
223 * The IT8716F only supports commands with length 1,2,4,5 bytes including
224 * command byte and can not read more than 3 bytes from the device.
225 *
226 * This function expects writearr[0] to be the first byte sent to the device,
227 * whereas the IT8716F splits commands internally into address and non-address
228 * commands with the address in inverse wire order. That's why the register
229 * ordering in case 4 and 5 may seem strange.
230 */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000231int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000232 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000233{
234 uint8_t busy, writeenc;
235 int i;
236
237 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000238 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000239 } while (busy);
240 if (readcnt > 3) {
Sean Nelson01e532d2010-01-10 01:09:58 +0000241 msg_pinfo("%s called with unsupported readcnt %i.\n",
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000242 __func__, readcnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000243 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000244 }
245 switch (writecnt) {
246 case 1:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000247 OUTB(writearr[0], it8716f_flashport + 1);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000248 writeenc = 0x0;
249 break;
250 case 2:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000251 OUTB(writearr[0], it8716f_flashport + 1);
252 OUTB(writearr[1], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000253 writeenc = 0x1;
254 break;
255 case 4:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000256 OUTB(writearr[0], it8716f_flashport + 1);
257 OUTB(writearr[1], it8716f_flashport + 4);
258 OUTB(writearr[2], it8716f_flashport + 3);
259 OUTB(writearr[3], it8716f_flashport + 2);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000260 writeenc = 0x2;
261 break;
262 case 5:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000263 OUTB(writearr[0], it8716f_flashport + 1);
264 OUTB(writearr[1], it8716f_flashport + 4);
265 OUTB(writearr[2], it8716f_flashport + 3);
266 OUTB(writearr[3], it8716f_flashport + 2);
267 OUTB(writearr[4], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000268 writeenc = 0x3;
269 break;
270 default:
Sean Nelson01e532d2010-01-10 01:09:58 +0000271 msg_pinfo("%s called with unsupported writecnt %i.\n",
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000272 __func__, writecnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000273 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000274 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000275 /*
276 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000277 * Note:
278 * We can't use writecnt directly, but have to use a strange encoding.
Uwe Hermann394131e2008-10-18 21:14:13 +0000279 */
280 OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
281 | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000282
283 if (readcnt > 0) {
284 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000285 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000286 } while (busy);
287
Uwe Hermann394131e2008-10-18 21:14:13 +0000288 for (i = 0; i < readcnt; i++)
Andriy Gapon65c1b862008-05-22 13:22:45 +0000289 readarr[i] = INB(it8716f_flashport + 5 + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000290 }
291
292 return 0;
293}
294
295/* Page size is usually 256 bytes */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000296static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int start)
Uwe Hermann394131e2008-10-18 21:14:13 +0000297{
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000298 int i;
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000299 int result;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000300 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000301
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000302 result = spi_write_enable();
303 if (result)
304 return result;
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000305 /* FIXME: The command below seems to be redundant or wrong. */
Uwe Hermann394131e2008-10-18 21:14:13 +0000306 OUTB(0x06, it8716f_flashport + 1);
Andriy Gapon65c1b862008-05-22 13:22:45 +0000307 OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000308 for (i = 0; i < 256; i++) {
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000309 chip_writeb(buf[i], bios + start + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000310 }
Andriy Gapon65c1b862008-05-22 13:22:45 +0000311 OUTB(0, it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000312 /* Wait until the Write-In-Progress bit is cleared.
313 * This usually takes 1-10 ms, so wait in 1 ms steps.
314 */
315 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000316 programmer_delay(1000);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000317 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000318}
319
320/*
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000321 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
322 * Need to read this big flash using firmware cycles 3 byte at a time.
323 */
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000324int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000325{
326 int total_size = 1024 * flash->total_size;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000327 fast_spi = 0;
328
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000329 if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) {
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000330 spi_read_chunked(flash, buf, start, len, 3);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000331 } else {
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000332 read_memmapped(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000333 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000334
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000335 return 0;
336}
337
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000338int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
Uwe Hermann394131e2008-10-18 21:14:13 +0000339{
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000340 /*
341 * IT8716F only allows maximum of 512 kb SPI chip size for memory
342 * mapped access.
343 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000344 if ((programmer == PROGRAMMER_IT87SPI) || (flash->total_size * 1024 > 512 * 1024)) {
345 spi_chip_write_1_new(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000346 } else {
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000347 int lenhere;
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000348
349 if (start % 256) {
350 /* start to the end of the page or start + len,
351 * whichever is smaller. Page length is hardcoded to
352 * 256 bytes (IT87 SPI hardware limitation).
353 */
354 lenhere = min(len, (start | 0xff) - start + 1);
355 spi_chip_write_1_new(flash, buf, start, lenhere);
356 start += lenhere;
357 len -= lenhere;
358 buf += lenhere;
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000359 }
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000360
361 /* FIXME: Handle chips which have max writechunk size >1 and <256. */
362 while (len >= 256) {
363 it8716f_spi_page_program(flash, buf, start);
364 start += 256;
365 len -= 256;
366 buf += 256;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000367 }
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000368 if (len)
369 spi_chip_write_1_new(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000370 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000371
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000372 return 0;
373}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000374
375#endif