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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +000025#include <string.h>
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000026#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000027#include "flashchips.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000028#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000030#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000031
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000032enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000033
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000034const struct spi_programmer spi_programmer[] = {
35 { /* SPI_CONTROLLER_NONE */
36 .command = NULL,
37 .multicommand = NULL,
38 .read = NULL,
39 .write_256 = NULL,
40 },
41
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000042#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000043#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000044 { /* SPI_CONTROLLER_ICH7 */
45 .command = ich_spi_send_command,
46 .multicommand = ich_spi_send_multicommand,
47 .read = ich_spi_read,
48 .write_256 = ich_spi_write_256,
49 },
50
51 { /* SPI_CONTROLLER_ICH9 */
52 .command = ich_spi_send_command,
53 .multicommand = ich_spi_send_multicommand,
54 .read = ich_spi_read,
55 .write_256 = ich_spi_write_256,
56 },
57
58 { /* SPI_CONTROLLER_IT87XX */
59 .command = it8716f_spi_send_command,
60 .multicommand = default_spi_send_multicommand,
61 .read = it8716f_spi_chip_read,
62 .write_256 = it8716f_spi_chip_write_256,
63 },
64
65 { /* SPI_CONTROLLER_SB600 */
66 .command = sb600_spi_send_command,
67 .multicommand = default_spi_send_multicommand,
68 .read = sb600_spi_read,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +000069 .write_256 = sb600_spi_write_256,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000070 },
71
72 { /* SPI_CONTROLLER_VIA */
73 .command = ich_spi_send_command,
74 .multicommand = ich_spi_send_multicommand,
75 .read = ich_spi_read,
76 .write_256 = ich_spi_write_256,
77 },
78
79 { /* SPI_CONTROLLER_WBSIO */
80 .command = wbsio_spi_send_command,
81 .multicommand = default_spi_send_multicommand,
82 .read = wbsio_spi_read,
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +000083 .write_256 = spi_chip_write_1,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000084 },
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000085
86 { /* SPI_CONTROLLER_MCP6X_BITBANG */
87 .command = bitbang_spi_send_command,
88 .multicommand = default_spi_send_multicommand,
89 .read = bitbang_spi_read,
90 .write_256 = bitbang_spi_write_256,
91 },
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +000092#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000093#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000094
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000095#if CONFIG_FT2232_SPI == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000096 { /* SPI_CONTROLLER_FT2232 */
97 .command = ft2232_spi_send_command,
98 .multicommand = default_spi_send_multicommand,
99 .read = ft2232_spi_read,
100 .write_256 = ft2232_spi_write_256,
101 },
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000102#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000103
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000104#if CONFIG_DUMMY == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000105 { /* SPI_CONTROLLER_DUMMY */
106 .command = dummy_spi_send_command,
107 .multicommand = default_spi_send_multicommand,
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +0000108 .read = dummy_spi_read,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000109 .write_256 = dummy_spi_write_256,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000110 },
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +0000111#endif
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000112
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000113#if CONFIG_BUSPIRATE_SPI == 1
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000114 { /* SPI_CONTROLLER_BUSPIRATE */
115 .command = buspirate_spi_send_command,
116 .multicommand = default_spi_send_multicommand,
117 .read = buspirate_spi_read,
Carl-Daniel Hailfinger408e47a2010-03-22 03:30:58 +0000118 .write_256 = buspirate_spi_write_256,
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000119 },
120#endif
121
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000122#if CONFIG_DEDIPROG == 1
Carl-Daniel Hailfingerd38fac82010-01-19 11:15:48 +0000123 { /* SPI_CONTROLLER_DEDIPROG */
124 .command = dediprog_spi_send_command,
125 .multicommand = default_spi_send_multicommand,
126 .read = dediprog_spi_read,
Carl-Daniel Hailfinger306b8182010-11-23 21:28:16 +0000127 .write_256 = dediprog_spi_write_256,
Carl-Daniel Hailfingerd38fac82010-01-19 11:15:48 +0000128 },
129#endif
130
Carl-Daniel Hailfingere7fdd6e2010-07-21 10:26:01 +0000131#if CONFIG_RAYER_SPI == 1
132 { /* SPI_CONTROLLER_RAYER */
133 .command = bitbang_spi_send_command,
134 .multicommand = default_spi_send_multicommand,
135 .read = bitbang_spi_read,
136 .write_256 = bitbang_spi_write_256,
137 },
138#endif
139
Idwer Vollering004f4b72010-09-03 18:21:21 +0000140#if CONFIG_NICINTEL_SPI == 1
141 { /* SPI_CONTROLLER_NICINTEL */
142 .command = bitbang_spi_send_command,
143 .multicommand = default_spi_send_multicommand,
144 .read = bitbang_spi_read,
145 .write_256 = bitbang_spi_write_256,
146 },
147#endif
148
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000149 {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000150};
151
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000152const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000153
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000154int spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000155 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000156{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000157 if (!spi_programmer[spi_controller].command) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000158 msg_perr("%s called, but SPI is unsupported on this "
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000159 "hardware. Please report a bug at "
160 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000161 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000162 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000163
164 return spi_programmer[spi_controller].command(writecnt, readcnt,
165 writearr, readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000166}
167
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000168int spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000169{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000170 if (!spi_programmer[spi_controller].multicommand) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000171 msg_perr("%s called, but SPI is unsupported on this "
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000172 "hardware. Please report a bug at "
173 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000174 return 1;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000175 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000176
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000177 return spi_programmer[spi_controller].multicommand(cmds);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000178}
179
180int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
181 const unsigned char *writearr, unsigned char *readarr)
182{
183 struct spi_command cmd[] = {
184 {
185 .writecnt = writecnt,
186 .readcnt = readcnt,
187 .writearr = writearr,
188 .readarr = readarr,
189 }, {
190 .writecnt = 0,
191 .writearr = NULL,
192 .readcnt = 0,
193 .readarr = NULL,
194 }};
195
196 return spi_send_multicommand(cmd);
197}
198
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000199int default_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000200{
201 int result = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000202 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
203 result = spi_send_command(cmds->writecnt, cmds->readcnt,
204 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000205 }
206 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000207}
208
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000209int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000210{
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +0000211 int addrbase = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000212 if (!spi_programmer[spi_controller].read) {
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000213 msg_perr("%s called, but SPI read is unsupported on this "
214 "hardware. Please report a bug at "
215 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000216 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000217 }
218
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +0000219 /* Check if the chip fits between lowest valid and highest possible
220 * address. Highest possible address with the current SPI implementation
221 * means 0xffffff, the highest unsigned 24bit number.
222 */
223 addrbase = spi_get_valid_read_addr();
224 if (addrbase + flash->total_size * 1024 > (1 << 24)) {
225 msg_perr("Flash chip size exceeds the allowed access window. ");
226 msg_perr("Read will probably fail.\n");
227 /* Try to get the best alignment subject to constraints. */
228 addrbase = (1 << 24) - flash->total_size * 1024;
229 }
230 /* Check if alignment is native (at least the largest power of two which
231 * is a factor of the mapped size of the chip).
232 */
233 if (ffs(flash->total_size * 1024) > (ffs(addrbase) ? : 33)) {
234 msg_perr("Flash chip is not aligned natively in the allowed "
235 "access window.\n");
236 msg_perr("Read will probably return garbage.\n");
237 }
238 return spi_programmer[spi_controller].read(flash, buf, addrbase + start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000239}
240
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000241/*
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000242 * Program chip using page (256 bytes) programming.
243 * Some SPI masters can't do this, they use single byte programming instead.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000244 * The redirect to single byte programming is achieved by setting
245 * .write_256 = spi_chip_write_1
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000246 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000247/* real chunksize is up to 256, logical chunksize is 256 */
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000248int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000249{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000250 if (!spi_programmer[spi_controller].write_256) {
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000251 msg_perr("%s called, but SPI page write is unsupported on this "
252 "hardware. Please report a bug at "
253 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000254 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000255 }
256
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000257 return spi_programmer[spi_controller].write_256(flash, buf, start, len);
258}
259
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000260/*
261 * Get the lowest allowed address for read accesses. This often happens to
262 * be the lowest allowed address for all commands which take an address.
263 * This is a programmer limitation.
264 */
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000265uint32_t spi_get_valid_read_addr(void)
266{
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000267 switch (spi_controller) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000268#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000269#if defined(__i386__) || defined(__x86_64__)
270 case SPI_CONTROLLER_ICH7:
271 /* Return BBAR for ICH chipsets. */
272 return ichspi_bbar;
273#endif
274#endif
275 default:
276 return 0;
277 }
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000278}