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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00004 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000015 */
16
17/*
18 * Contains the generic SPI framework
19 */
20
Patrick Georgi97bc95c2011-03-08 07:17:44 +000021#include <strings.h>
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +000022#include <string.h>
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000023#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000024#include "flashchips.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000025#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000026#include "programmer.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000027#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000028
Edward O'Callaghan5eca4272020-04-12 17:27:53 +100029int spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000030 unsigned int readcnt, const unsigned char *writearr,
31 unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +000032{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000033 return flash->mst->spi.command(flash, writecnt, readcnt, writearr,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000034 readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +000035}
36
Edward O'Callaghan5eca4272020-04-12 17:27:53 +100037int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds)
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +000038{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000039 return flash->mst->spi.multicommand(flash, cmds);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000040}
41
Edward O'Callaghan5eca4272020-04-12 17:27:53 +100042int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000043 unsigned int readcnt,
44 const unsigned char *writearr,
45 unsigned char *readarr)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000046{
47 struct spi_command cmd[] = {
48 {
49 .writecnt = writecnt,
50 .readcnt = readcnt,
51 .writearr = writearr,
52 .readarr = readarr,
53 }, {
54 .writecnt = 0,
55 .writearr = NULL,
56 .readcnt = 0,
57 .readarr = NULL,
58 }};
59
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000060 return spi_send_multicommand(flash, cmd);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000061}
62
Edward O'Callaghan5eca4272020-04-12 17:27:53 +100063int default_spi_send_multicommand(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000064 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000065{
66 int result = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +000067 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000068 result = spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +000069 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000070 }
71 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +000072}
73
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000074int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
75 unsigned int len)
Michael Karcher62797512011-05-11 17:07:02 +000076{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000077 unsigned int max_data = flash->mst->spi.max_data_read;
Michael Karcher62797512011-05-11 17:07:02 +000078 if (max_data == MAX_DATA_UNSPECIFIED) {
Nico Huberac90af62022-12-18 00:22:47 +000079 msg_perr("%s called, but SPI read chunk size not defined on this hardware.\n"
Nico Huberc3b02dc2023-08-12 01:13:45 +020080 "Please report a bug at flashprog@flashprog.org\n", __func__);
Michael Karcher62797512011-05-11 17:07:02 +000081 return 1;
82 }
83 return spi_read_chunked(flash, buf, start, len, max_data);
84}
85
Mark Marshallf20b7be2014-05-09 21:16:21 +000086int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Michael Karcher62797512011-05-11 17:07:02 +000087{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000088 unsigned int max_data = flash->mst->spi.max_data_write;
Michael Karcher62797512011-05-11 17:07:02 +000089 if (max_data == MAX_DATA_UNSPECIFIED) {
Nico Huberac90af62022-12-18 00:22:47 +000090 msg_perr("%s called, but SPI write chunk size not defined on this hardware.\n"
Nico Huberc3b02dc2023-08-12 01:13:45 +020091 "Please report a bug at flashprog@flashprog.org\n", __func__);
Michael Karcher62797512011-05-11 17:07:02 +000092 return 1;
93 }
94 return spi_write_chunked(flash, buf, start, len, max_data);
95}
96
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000097int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
98 unsigned int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +000099{
Nico Huberd8b2e802019-06-18 23:39:56 +0200100 int ret;
101 size_t to_read;
102 for (; len; len -= to_read, buf += to_read, start += to_read) {
103 /* Do not cross 16MiB boundaries in a single transfer.
104 This helps with
105 o multi-die 4-byte-addressing chips,
106 o dediprog that has a protocol limit of 32MiB-512B. */
107 to_read = min(ALIGN_DOWN(start + 16*MiB, 16*MiB) - start, len);
108 ret = flash->mst->spi.read(flash, buf, start, to_read);
109 if (ret)
110 return ret;
111 }
112 return 0;
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000113}
114
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000115/*
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000116 * Program chip using page (256 bytes) programming.
117 * Some SPI masters can't do this, they use single byte programming instead.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000118 * The redirect to single byte programming is achieved by setting
119 * .write_256 = spi_chip_write_1
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000120 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000121/* real chunksize is up to 256, logical chunksize is 256 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000122int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000123{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000124 return flash->mst->spi.write_256(flash, buf, start, len);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000125}
126
Mark Marshallf20b7be2014-05-09 21:16:21 +0000127int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Nico Huber7bca1262012-06-15 22:28:12 +0000128{
Edward O'Callaghan0b587f92022-09-09 23:01:05 +1000129 if (flash->mst->spi.write_aai)
130 return flash->mst->spi.write_aai(flash, buf, start, len);
131 return default_spi_write_aai(flash, buf, start, len);
Nico Huber7bca1262012-06-15 22:28:12 +0000132}
133
Nikolai Artemieve7a41e32022-11-28 17:40:56 +1100134bool default_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
Aarya Chaumal0cea7532022-07-04 18:21:50 +0530135{
136 return true;
137}
138
Nico Huber89569d62023-01-12 23:31:40 +0100139int register_spi_master(const struct spi_master *mst, size_t max_rom_decode, void *data)
Michael Karcherb9dbe482011-05-11 17:07:07 +0000140{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000141 struct registered_master rmst;
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000142
Anastasia Klimchuk7783f2f2021-07-05 09:18:06 +1000143 if (mst->shutdown) {
144 if (register_shutdown(mst->shutdown, data)) {
145 mst->shutdown(data); /* cleanup */
146 return 1;
147 }
148 }
149
Edward O'Callaghan0b587f92022-09-09 23:01:05 +1000150 if (!mst->write_256 || !mst->read || !mst->command ||
Aarya Chaumal0cea7532022-07-04 18:21:50 +0530151 !mst->multicommand || !mst->probe_opcode ||
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000152 ((mst->command == default_spi_send_command) &&
153 (mst->multicommand == default_spi_send_multicommand))) {
Nico Huberac90af62022-12-18 00:22:47 +0000154 msg_perr("%s called with incomplete master definition.\n"
Nico Huberc3b02dc2023-08-12 01:13:45 +0200155 "Please report a bug at flashprog@flashprog.org\n",
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000156 __func__);
Nico Huberc3b02dc2023-08-12 01:13:45 +0200157 return ERROR_FLASHPROG_BUG;
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000158 }
159
Nico Huber89569d62023-01-12 23:31:40 +0100160 if (max_rom_decode)
161 rmst.max_rom_decode = max_rom_decode;
162 else
163 rmst.max_rom_decode = MAX_ROM_DECODE_UNLIMITED;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000164 rmst.buses_supported = BUS_SPI;
165 rmst.spi = *mst;
Nico Huber5e08e3e2021-05-11 17:38:14 +0200166 if (data)
167 rmst.spi.data = data;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000168 return register_master(&rmst);
Stefan Tauner93f70232011-07-26 14:33:46 +0000169}
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200170
Thomas Heijligenb0be3202022-09-20 00:07:23 +0200171/*
172 * The following array has erasefn and opcode list pair. The opcode list pair is
173 * 0 termintated and must have size one more than the maximum number of opcodes
174 * used by any erasefn. Also the opcodes must be in increasing order.
175 */
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200176static const struct {
177 erasefunc_t *func;
Thomas Heijligenb0be3202022-09-20 00:07:23 +0200178 uint8_t opcode[3];
Nico Huber13389362024-03-05 18:35:30 +0100179 bool native_4ba;
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200180} function_opcode_list[] = {
Nico Huber13389362024-03-05 18:35:30 +0100181 {spi_block_erase_20, {0x20}, false},
182 {spi_block_erase_21, {0x21}, true},
183 {spi_block_erase_50, {0x50}, false},
184 {spi_block_erase_52, {0x52}, false},
185 {spi_block_erase_53, {0x53}, true},
186 {spi_block_erase_5c, {0x5c}, true},
187 {spi_block_erase_60, {0x60}, false},
188 {spi_block_erase_62, {0x62}, false},
189 {spi_block_erase_81, {0x81}, false},
190 {spi_block_erase_c4, {0xc4}, false},
191 {spi_block_erase_c7, {0xc7}, false},
192 {spi_block_erase_d7, {0xd7}, false},
193 {spi_block_erase_d8, {0xd8}, false},
194 {spi_block_erase_db, {0xdb}, false},
195 {spi_block_erase_dc, {0xdc}, true},
Thomas Heijligenb0be3202022-09-20 00:07:23 +0200196 //AT45CS1282
Nico Huber13389362024-03-05 18:35:30 +0100197 {spi_erase_at45cs_sector, {0x50, 0x7c, 0}, false},
Thomas Heijligenb0be3202022-09-20 00:07:23 +0200198 //AT45DB**
Nico Huber13389362024-03-05 18:35:30 +0100199 {spi_erase_at45db_page, {0x81}, false},
200 {spi_erase_at45db_block, {0x50}, false},
201 {spi_erase_at45db_sector, {0x7c}, false},
202 {spi_erase_at45db_chip, {0xc7}, false},
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200203};
204
Nico Huber13389362024-03-05 18:35:30 +0100205const uint8_t *spi_get_opcode_from_erasefn(erasefunc_t *func, bool *native_4ba)
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200206{
207 size_t i;
208 for (i = 0; i < ARRAY_SIZE(function_opcode_list); i++) {
Nico Huber13389362024-03-05 18:35:30 +0100209 if (function_opcode_list[i].func == func) {
210 if (native_4ba)
211 *native_4ba = function_opcode_list[i].native_4ba;
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200212 return function_opcode_list[i].opcode;
Nico Huber13389362024-03-05 18:35:30 +0100213 }
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200214 }
215 msg_cinfo("%s: unknown erase function (0x%p). Please report "
Nico Huberc3b02dc2023-08-12 01:13:45 +0200216 "this at flashprog@flashprog.org\n", __func__, func);
Thomas Heijligenb0be3202022-09-20 00:07:23 +0200217 return NULL;
Thomas Heijligene2ff4e92022-09-19 23:31:08 +0200218}