blob: ebacd6072dca3c3dc8f872ca94a3b6bb971aa56b [file] [log] [blame]
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000025#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000026#include "flashchips.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000027#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000028#include "programmer.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000029#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000030
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000031enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +000032
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000033const struct spi_programmer spi_programmer[] = {
34 { /* SPI_CONTROLLER_NONE */
35 .command = NULL,
36 .multicommand = NULL,
37 .read = NULL,
38 .write_256 = NULL,
39 },
40
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000041#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000042#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000043 { /* SPI_CONTROLLER_ICH7 */
44 .command = ich_spi_send_command,
45 .multicommand = ich_spi_send_multicommand,
46 .read = ich_spi_read,
47 .write_256 = ich_spi_write_256,
48 },
49
50 { /* SPI_CONTROLLER_ICH9 */
51 .command = ich_spi_send_command,
52 .multicommand = ich_spi_send_multicommand,
53 .read = ich_spi_read,
54 .write_256 = ich_spi_write_256,
55 },
56
57 { /* SPI_CONTROLLER_IT87XX */
58 .command = it8716f_spi_send_command,
59 .multicommand = default_spi_send_multicommand,
60 .read = it8716f_spi_chip_read,
61 .write_256 = it8716f_spi_chip_write_256,
62 },
63
64 { /* SPI_CONTROLLER_SB600 */
65 .command = sb600_spi_send_command,
66 .multicommand = default_spi_send_multicommand,
67 .read = sb600_spi_read,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +000068 .write_256 = sb600_spi_write_256,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000069 },
70
71 { /* SPI_CONTROLLER_VIA */
72 .command = ich_spi_send_command,
73 .multicommand = ich_spi_send_multicommand,
74 .read = ich_spi_read,
75 .write_256 = ich_spi_write_256,
76 },
77
78 { /* SPI_CONTROLLER_WBSIO */
79 .command = wbsio_spi_send_command,
80 .multicommand = default_spi_send_multicommand,
81 .read = wbsio_spi_read,
Carl-Daniel Hailfingerca812d42010-07-14 19:57:52 +000082 .write_256 = spi_chip_write_1_new,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000083 },
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +000084
85 { /* SPI_CONTROLLER_MCP6X_BITBANG */
86 .command = bitbang_spi_send_command,
87 .multicommand = default_spi_send_multicommand,
88 .read = bitbang_spi_read,
89 .write_256 = bitbang_spi_write_256,
90 },
Carl-Daniel Hailfinger66ef4e52009-12-13 22:28:00 +000091#endif
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000092#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000093
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +000094#if CONFIG_FT2232_SPI == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000095 { /* SPI_CONTROLLER_FT2232 */
96 .command = ft2232_spi_send_command,
97 .multicommand = default_spi_send_multicommand,
98 .read = ft2232_spi_read,
99 .write_256 = ft2232_spi_write_256,
100 },
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000101#endif
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000102
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000103#if CONFIG_DUMMY == 1
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000104 { /* SPI_CONTROLLER_DUMMY */
105 .command = dummy_spi_send_command,
106 .multicommand = default_spi_send_multicommand,
Carl-Daniel Hailfinger1b0ba892010-06-20 10:58:32 +0000107 .read = dummy_spi_read,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000108 .write_256 = dummy_spi_write_256,
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000109 },
Carl-Daniel Hailfinger4740c6f2009-09-16 10:09:21 +0000110#endif
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000111
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000112#if CONFIG_BUSPIRATE_SPI == 1
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000113 { /* SPI_CONTROLLER_BUSPIRATE */
114 .command = buspirate_spi_send_command,
115 .multicommand = default_spi_send_multicommand,
116 .read = buspirate_spi_read,
Carl-Daniel Hailfinger408e47a2010-03-22 03:30:58 +0000117 .write_256 = buspirate_spi_write_256,
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000118 },
119#endif
120
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000121#if CONFIG_DEDIPROG == 1
Carl-Daniel Hailfingerd38fac82010-01-19 11:15:48 +0000122 { /* SPI_CONTROLLER_DEDIPROG */
123 .command = dediprog_spi_send_command,
124 .multicommand = default_spi_send_multicommand,
125 .read = dediprog_spi_read,
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000126 .write_256 = spi_chip_write_1_new,
Carl-Daniel Hailfingerd38fac82010-01-19 11:15:48 +0000127 },
128#endif
129
Carl-Daniel Hailfingere7fdd6e2010-07-21 10:26:01 +0000130#if CONFIG_RAYER_SPI == 1
131 { /* SPI_CONTROLLER_RAYER */
132 .command = bitbang_spi_send_command,
133 .multicommand = default_spi_send_multicommand,
134 .read = bitbang_spi_read,
135 .write_256 = bitbang_spi_write_256,
136 },
137#endif
138
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000139 {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000140};
141
Carl-Daniel Hailfinger3426ef62009-08-19 13:27:58 +0000142const int spi_programmer_count = ARRAY_SIZE(spi_programmer);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000143
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000144int spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000145 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000146{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000147 if (!spi_programmer[spi_controller].command) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000148 msg_perr("%s called, but SPI is unsupported on this "
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000149 "hardware. Please report a bug at "
150 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000151 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000152 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000153
154 return spi_programmer[spi_controller].command(writecnt, readcnt,
155 writearr, readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +0000156}
157
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000158int spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000159{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000160 if (!spi_programmer[spi_controller].multicommand) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000161 msg_perr("%s called, but SPI is unsupported on this "
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000162 "hardware. Please report a bug at "
163 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000164 return 1;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000165 }
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000166
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000167 return spi_programmer[spi_controller].multicommand(cmds);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000168}
169
170int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
171 const unsigned char *writearr, unsigned char *readarr)
172{
173 struct spi_command cmd[] = {
174 {
175 .writecnt = writecnt,
176 .readcnt = readcnt,
177 .writearr = writearr,
178 .readarr = readarr,
179 }, {
180 .writecnt = 0,
181 .writearr = NULL,
182 .readcnt = 0,
183 .readarr = NULL,
184 }};
185
186 return spi_send_multicommand(cmd);
187}
188
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000189int default_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000190{
191 int result = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000192 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
193 result = spi_send_command(cmds->writecnt, cmds->readcnt,
194 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000195 }
196 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000197}
198
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000199int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000200{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000201 if (!spi_programmer[spi_controller].read) {
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000202 msg_perr("%s called, but SPI read is unsupported on this "
203 "hardware. Please report a bug at "
204 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000205 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000206 }
207
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000208 return spi_programmer[spi_controller].read(flash, buf, start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000209}
210
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000211/*
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000212 * Program chip using page (256 bytes) programming.
213 * Some SPI masters can't do this, they use single byte programming instead.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000214 * The redirect to single byte programming is achieved by setting
215 * .write_256 = spi_chip_write_1
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000216 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000217/* real chunksize is up to 256, logical chunksize is 256 */
218int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000219{
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000220 if (!spi_programmer[spi_controller].write_256) {
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000221 msg_perr("%s called, but SPI page write is unsupported on this "
222 "hardware. Please report a bug at "
223 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000224 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000225 }
226
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000227 return spi_programmer[spi_controller].write_256(flash, buf, start, len);
228}
229
230/* Wrapper function until the generic code is converted to partial writes. */
231int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
232{
233 int ret;
234
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000235 msg_pinfo("Erasing flash before programming... ");
236 if (erase_flash(flash)) {
237 msg_perr("ERASE FAILED!\n");
238 return -1;
239 }
240 msg_pinfo("done.\n");
241 msg_pinfo("Programming flash... ");
242 ret = spi_chip_write_256_new(flash, buf, 0, flash->total_size * 1024);
243 if (!ret)
244 msg_pinfo("done.\n");
245 else
246 msg_pinfo("\n");
247 return ret;
Carl-Daniel Hailfinger6b444962007-10-18 00:24:07 +0000248}
Peter Stugefd9217d2009-01-26 03:37:40 +0000249
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000250/*
251 * Get the lowest allowed address for read accesses. This often happens to
252 * be the lowest allowed address for all commands which take an address.
253 * This is a programmer limitation.
254 */
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000255uint32_t spi_get_valid_read_addr(void)
256{
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000257 switch (spi_controller) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000258#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000259#if defined(__i386__) || defined(__x86_64__)
260 case SPI_CONTROLLER_ICH7:
261 /* Return BBAR for ICH chipsets. */
262 return ichspi_bbar;
263#endif
264#endif
265 default:
266 return 0;
267 }
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000268}