blob: 800d9d2250ec8df58908eca613a1b5482a649acc [file] [log] [blame]
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000018 *
Uwe Hermannd1107642007-08-29 17:52:32 +000019 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000022 */
23
24#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000025
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000026#define MAX_REFLASH_TRIES 0x10
27
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000028/* Check one byte for odd parity */
29uint8_t oddparity(uint8_t val)
30{
31 val = (val ^ (val >> 4)) & 0xf;
32 val = (val ^ (val >> 2)) & 0x3;
33 return (val ^ (val >> 1)) & 0x1;
34}
35
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000036void toggle_ready_jedec_common(chipaddr dst, int delay)
Uwe Hermann51582f22007-08-23 10:20:40 +000037{
38 unsigned int i = 0;
39 uint8_t tmp1, tmp2;
40
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000041 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000042
43 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000044 if (delay)
45 programmer_delay(delay);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000046 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000047 if (tmp1 == tmp2) {
48 break;
49 }
50 tmp1 = tmp2;
51 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000052 if (i > 0x100000)
53 printf_debug("%s: excessive loops, i=0x%x\n", __func__, i);
54}
55
56void toggle_ready_jedec(chipaddr dst)
57{
58 toggle_ready_jedec_common(dst, 0);
59}
60
61/* Some chips require a minimum delay between toggle bit reads.
62 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
63 * but experiments show that 2 ms are already enough. Pick a safety factor
64 * of 4 and use an 8 ms delay.
65 * Given that erase is slow on all chips, it is recommended to use
66 * toggle_ready_jedec_slow in erase functions.
67 */
68void toggle_ready_jedec_slow(chipaddr dst)
69{
70 toggle_ready_jedec_common(dst, 8 * 1000);
Uwe Hermann51582f22007-08-23 10:20:40 +000071}
72
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000073void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000074{
75 unsigned int i = 0;
76 uint8_t tmp;
77
78 data &= 0x80;
79
80 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000081 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000082 if (tmp == data) {
83 break;
84 }
85 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000086 if (i > 0x100000)
87 printf_debug("%s: excessive loops, i=0x%x\n", __func__, i);
Uwe Hermann51582f22007-08-23 10:20:40 +000088}
89
Michael Karcher972cec22009-11-26 14:50:52 +000090void start_program_jedec(chipaddr bios)
Uwe Hermann51582f22007-08-23 10:20:40 +000091{
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000092 chip_writeb(0xAA, bios + 0x5555);
93 chip_writeb(0x55, bios + 0x2AAA);
94 chip_writeb(0xA0, bios + 0x5555);
Uwe Hermann51582f22007-08-23 10:20:40 +000095}
96
Ollie Lho761bf1b2004-03-20 16:46:10 +000097int probe_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000098{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000099 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +0000100 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000101 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000102 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +0000103 int probe_timing_enter, probe_timing_exit;
104
105 if (flash->probe_timing > 0)
106 probe_timing_enter = probe_timing_exit = flash->probe_timing;
107 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
108 probe_timing_enter = probe_timing_exit = 0;
109 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
110 printf_debug("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000111 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +0000112 probe_timing_enter = 10000;
113 probe_timing_exit = 40;
114 } else {
115 printf("Chip has negative value in probe_timing, failing "
116 "without chip access\n");
117 return 0;
118 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000119
Ollie Lho761bf1b2004-03-20 16:46:10 +0000120 /* Issue JEDEC Product ID Entry command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000121 chip_writeb(0xAA, bios + 0x5555);
Sean Nelsonc12fc712009-12-17 04:22:40 +0000122 if (probe_timing_enter)
123 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000124 chip_writeb(0x55, bios + 0x2AAA);
Sean Nelsonc12fc712009-12-17 04:22:40 +0000125 if (probe_timing_enter)
126 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000127 chip_writeb(0x90, bios + 0x5555);
Sean Nelsonc12fc712009-12-17 04:22:40 +0000128 if (probe_timing_enter)
129 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000130
Ollie Lho761bf1b2004-03-20 16:46:10 +0000131 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000132 id1 = chip_readb(bios);
133 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000134 largeid1 = id1;
135 largeid2 = id2;
136
137 /* Check if it is a continuation ID, this should be a while loop. */
138 if (id1 == 0x7F) {
139 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000140 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000141 largeid1 |= id1;
142 }
143 if (id2 == 0x7F) {
144 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000145 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000146 largeid2 |= id2;
147 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000148
Ollie Lho761bf1b2004-03-20 16:46:10 +0000149 /* Issue JEDEC Product ID Exit command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000150 chip_writeb(0xAA, bios + 0x5555);
Sean Nelsonc12fc712009-12-17 04:22:40 +0000151 if (probe_timing_exit)
152 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000153 chip_writeb(0x55, bios + 0x2AAA);
Sean Nelsonc12fc712009-12-17 04:22:40 +0000154 if (probe_timing_exit)
155 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000156 chip_writeb(0xF0, bios + 0x5555);
Sean Nelsonc12fc712009-12-17 04:22:40 +0000157 if (probe_timing_exit)
158 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000159
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000160 printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000161 if (!oddparity(id1))
162 printf_debug(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000163
164 /* Read the product ID location again. We should now see normal flash contents. */
165 flashcontent1 = chip_readb(bios);
166 flashcontent2 = chip_readb(bios + 0x01);
167
168 /* Check if it is a continuation ID, this should be a while loop. */
169 if (flashcontent1 == 0x7F) {
170 flashcontent1 <<= 8;
171 flashcontent1 |= chip_readb(bios + 0x100);
172 }
173 if (flashcontent2 == 0x7F) {
174 flashcontent2 <<= 8;
175 flashcontent2 |= chip_readb(bios + 0x101);
176 }
177
178 if (largeid1 == flashcontent1)
179 printf_debug(", id1 is normal flash content");
180 if (largeid2 == flashcontent2)
181 printf_debug(", id2 is normal flash content");
182
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000183 printf_debug("\n");
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000184 if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000185 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000186
Ollie Lho761bf1b2004-03-20 16:46:10 +0000187 return 0;
Ollie Lho73eca802004-03-19 22:10:07 +0000188}
189
Carl-Daniel Hailfingera06287c2009-09-23 22:01:33 +0000190int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize)
Ollie Lho73eca802004-03-19 22:10:07 +0000191{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000192 chipaddr bios = flash->virtual_memory;
193
Ollie Lho761bf1b2004-03-20 16:46:10 +0000194 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000195 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000196 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000197 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000198 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000199 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000200 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000201
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000202 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000203 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000204 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000205 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000206 chip_writeb(0x30, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000207 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000208
Ollie Lho73eca802004-03-19 22:10:07 +0000209 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000210 toggle_ready_jedec_slow(bios);
Ollie Lho73eca802004-03-19 22:10:07 +0000211
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000212 if (check_erased_range(flash, page, pagesize)) {
213 fprintf(stderr,"ERASE FAILED!\n");
214 return -1;
215 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000216 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000217}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000218
Carl-Daniel Hailfingera06287c2009-09-23 22:01:33 +0000219int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000220{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000221 chipaddr bios = flash->virtual_memory;
222
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000223 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000224 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000225 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000226 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000227 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000228 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000229 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000230
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000231 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000232 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000233 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000234 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000235 chip_writeb(0x50, bios + block);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000236 programmer_delay(10);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000237
238 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000239 toggle_ready_jedec_slow(bios);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000240
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000241 if (check_erased_range(flash, block, blocksize)) {
242 fprintf(stderr,"ERASE FAILED!\n");
243 return -1;
244 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000245 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000246}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000247
Ollie Lho761bf1b2004-03-20 16:46:10 +0000248int erase_chip_jedec(struct flashchip *flash)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000249{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000250 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000251 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000252
Ollie Lho761bf1b2004-03-20 16:46:10 +0000253 /* Issue the JEDEC Chip Erase command */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000254 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000255 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000256 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000257 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000258 chip_writeb(0x80, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000259 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000260
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000261 chip_writeb(0xAA, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000262 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000263 chip_writeb(0x55, bios + 0x2AAA);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000264 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000265 chip_writeb(0x10, bios + 0x5555);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000266 programmer_delay(10);
Ollie Lho73eca802004-03-19 22:10:07 +0000267
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000268 toggle_ready_jedec_slow(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000269
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000270 if (check_erased_range(flash, 0, total_size)) {
271 fprintf(stderr,"ERASE FAILED!\n");
272 return -1;
273 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000274 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000275}
276
Urja Rannikko0c854c02009-06-25 13:57:31 +0000277int write_page_write_jedec(struct flashchip *flash, uint8_t *src,
278 int start, int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000279{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000280 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000281 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000282 chipaddr bios = flash->virtual_memory;
283 chipaddr dst = bios + start;
284 chipaddr d = dst;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000285
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000286retry:
Ollie Lho761bf1b2004-03-20 16:46:10 +0000287 /* Issue JEDEC Data Unprotect comand */
Michael Karcher972cec22009-11-26 14:50:52 +0000288 start_program_jedec(bios);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000289
Ollie Lho98bea8a2004-12-07 03:15:51 +0000290 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000291 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000292 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000293 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000294 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000295 dst++;
296 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000297 }
298
Ollie Lho761bf1b2004-03-20 16:46:10 +0000299 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000300
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000301 dst = d;
302 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000303 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000304
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000305 if (failed && tried++ < MAX_REFLASH_TRIES) {
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000306 fprintf(stderr, "retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000307 goto retry;
308 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000309 if (failed) {
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000310 fprintf(stderr, " page 0x%lx failed!\n",
311 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000312 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000313 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000314}
315
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000316int write_byte_program_jedec(chipaddr bios, uint8_t *src,
317 chipaddr dst)
Ollie Lho070647d2004-03-22 22:19:17 +0000318{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000319 int tried = 0, failed = 0;
Ollie Lho1b8b6602004-12-08 02:10:33 +0000320
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000321 /* If the data is 0xFF, don't program it and don't complain. */
Ollie Lho070647d2004-03-22 22:19:17 +0000322 if (*src == 0xFF) {
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000323 return 0;
Ollie Lho070647d2004-03-22 22:19:17 +0000324 }
Ollie Lho98bea8a2004-12-07 03:15:51 +0000325
Ollie Lho1b8b6602004-12-08 02:10:33 +0000326retry:
Ollie Lho070647d2004-03-22 22:19:17 +0000327 /* Issue JEDEC Byte Program command */
Michael Karcher972cec22009-11-26 14:50:52 +0000328 start_program_jedec(bios);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000329
330 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000331 chip_writeb(*src, dst);
Ollie Lho070647d2004-03-22 22:19:17 +0000332 toggle_ready_jedec(bios);
Ollie Lho8b8897a2004-03-27 00:18:15 +0000333
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000334 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000335 goto retry;
336 }
Ollie Lho1b8b6602004-12-08 02:10:33 +0000337
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000338 if (tried >= MAX_REFLASH_TRIES)
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000339 failed = 1;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000340
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000341 return failed;
Ollie Lho070647d2004-03-22 22:19:17 +0000342}
343
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000344int write_sector_jedec(chipaddr bios, uint8_t *src,
345 chipaddr dst, unsigned int page_size)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000346{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000347 int i, failed = 0;
348 chipaddr olddst;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000349
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000350 olddst = dst;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000351 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000352 if (write_byte_program_jedec(bios, src, dst))
353 failed = 1;
Ollie Lho8b8897a2004-03-27 00:18:15 +0000354 dst++, src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000355 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000356 if (failed)
357 fprintf(stderr, " writing sector at 0x%lx failed!\n", olddst);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000358
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000359 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000360}
361
Ollie Lho184a4042005-11-26 21:55:36 +0000362int write_jedec(struct flashchip *flash, uint8_t *buf)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000363{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000364 int i, failed = 0;
Ollie Lho070647d2004-03-22 22:19:17 +0000365 int total_size = flash->total_size * 1024;
366 int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000367
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000368 if (erase_chip_jedec(flash)) {
369 fprintf(stderr,"ERASE FAILED!\n");
370 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000371 }
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000372
Uwe Hermanna502dce2007-10-17 23:55:15 +0000373 printf("Programming page: ");
Ollie Lho761bf1b2004-03-20 16:46:10 +0000374 for (i = 0; i < total_size / page_size; i++) {
375 printf("%04d at address: 0x%08x", i, i * page_size);
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000376 if (write_page_write_jedec(flash, buf + i * page_size,
377 i * page_size, page_size))
378 failed = 1;
Ollie Lho070647d2004-03-22 22:19:17 +0000379 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000380 }
381 printf("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000382
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000383 return failed;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000384}
Michael Karcher1c296ca2009-11-27 17:49:42 +0000385
386int write_jedec_1(struct flashchip *flash, uint8_t * buf)
387{
388 int i;
389 chipaddr bios = flash->virtual_memory;
390 chipaddr dst = bios;
391
392 programmer_delay(10);
393 if (erase_flash(flash)) {
394 fprintf(stderr, "ERASE FAILED!\n");
395 return -1;
396 }
397
398 printf("Programming page: ");
399 for (i = 0; i < flash->total_size; i++) {
400 if ((i & 0x3) == 0)
401 printf("address: 0x%08lx", (unsigned long)i * 1024);
402
403 write_sector_jedec(bios, buf + i * 1024, dst + i * 1024, 1024);
404
405 if ((i & 0x3) == 0)
406 printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
407 }
408
409 printf("\n");
410 return 0;
411}