blob: 48e5b875b69c38bc0b1f591046241da4ba186fd7 [file] [log] [blame]
Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Stefan Tauner1e146392011-09-15 23:52:55 +000016 */
17
Stefan Tauner1e146392011-09-15 23:52:55 +000018#include "ich_descriptors.h"
Thomas Heijligencce1e5b2021-11-02 20:33:35 +010019#include "hwaccess.h"
Stefan Taunerb3850962011-12-24 00:00:32 +000020
Nico Huberad186312016-05-02 15:15:29 +020021#ifdef ICH_DESCRIPTORS_FROM_DUMP_ONLY
Stefan Taunerb3850962011-12-24 00:00:32 +000022#include <stdio.h>
Nico Huber305f4172013-06-14 11:55:26 +020023#include <string.h>
Stefan Taunerb3850962011-12-24 00:00:32 +000024#define print(t, ...) printf(__VA_ARGS__)
Nico Huberad186312016-05-02 15:15:29 +020025#endif
26
Stefan Taunerb3850962011-12-24 00:00:32 +000027#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a
28/* The upper map is located in the word before the 256B-long OEM section at the
29 * end of the 4kB-long flash descriptor.
30 */
31#define UPPER_MAP_OFFSET (4096 - 256 - 4)
32#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0)
33
Felix Singerd68a0ec2022-08-19 03:23:35 +020034#include <stdbool.h>
Nico Huber4d440a72017-08-15 11:26:48 +020035#include <sys/types.h>
Nico Huberad186312016-05-02 15:15:29 +020036#include <string.h>
Stefan Tauner1e146392011-09-15 23:52:55 +000037#include "flash.h" /* for msg_* */
38#include "programmer.h"
39
Nico Huberfa622942017-03-24 17:25:37 +010040ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_content *const cont)
41{
42 switch (cs) {
Nico Huberd2d39932019-01-18 16:49:37 +010043 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +020044 case CHIPSET_GEMINI_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +010045 return 6;
David Hendricksa5216362017-08-08 20:02:22 -070046 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +020047 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +020048 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +010049 case CHIPSET_ELKHART_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -070050 return 16;
Nico Huberfa622942017-03-24 17:25:37 +010051 case CHIPSET_100_SERIES_SUNRISE_POINT:
52 return 10;
53 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
54 case CHIPSET_9_SERIES_WILDCAT_POINT:
55 case CHIPSET_8_SERIES_LYNX_POINT_LP:
56 case CHIPSET_8_SERIES_LYNX_POINT:
57 case CHIPSET_8_SERIES_WELLSBURG:
58 if (cont->NR <= 6)
59 return cont->NR + 1;
60 else
61 return -1;
62 default:
63 if (cont->NR <= 4)
64 return cont->NR + 1;
65 else
66 return -1;
67 }
68}
69
70ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_content *const cont)
71{
David Hendricksa5216362017-08-08 20:02:22 -070072 switch (cs) {
73 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huberd2d39932019-01-18 16:49:37 +010074 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +020075 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +010076 case CHIPSET_ELKHART_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -070077 if (cont->NM <= MAX_NUM_MASTERS)
78 return cont->NM;
Richard Hughesdb7482b2018-12-19 12:04:30 +000079 break;
David Hendricksa5216362017-08-08 20:02:22 -070080 default:
81 if (cont->NM < MAX_NUM_MASTERS)
82 return cont->NM + 1;
83 }
84
85 return -1;
Nico Huberfa622942017-03-24 17:25:37 +010086}
87
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000088void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl)
Stefan Tauner1e146392011-09-15 23:52:55 +000089{
90 print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF);
91 print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF);
92 print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF);
93 print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000094 print(verbosity, "EO=0x%x", (reg_val & VSCC_EO) >> VSCC_EO_OFF);
95 if (print_vcl)
96 print(verbosity, ", VCL=%d", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF);
97 print(verbosity, "\n");
Stefan Tauner1e146392011-09-15 23:52:55 +000098}
99
100#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0)
101#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0)
102#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0)
103#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0)
104#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0)
105
Nico Huber67d71792017-06-17 03:10:15 +0200106void prettyprint_ich_chipset(enum ich_chipset cs)
107{
108 static const char *const chipset_names[] = {
109 "Unknown ICH", "ICH8", "ICH9", "ICH10",
110 "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point",
111 "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
112 "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
Angel Pons4db0fdf2020-07-10 17:04:10 +0200113 "C620 series Lewisburg", "300/400 series Cannon/Comet Point",
Nico Huber29c23dd2022-12-21 15:25:09 +0000114 "500/600 series Tiger/Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
Nico Huber67d71792017-06-17 03:10:15 +0200115 };
116 if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
117 cs = 0;
118 else
119 cs = cs - CHIPSET_ICH8 + 1;
120 msg_pdbg2("Assuming chipset '%s'.\n", chipset_names[cs]);
121}
122
Stefan Tauner1e146392011-09-15 23:52:55 +0000123void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc)
124{
Nico Huberfa622942017-03-24 17:25:37 +0100125 prettyprint_ich_descriptor_content(cs, &desc->content);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000126 prettyprint_ich_descriptor_component(cs, desc);
Nico Huberfa622942017-03-24 17:25:37 +0100127 prettyprint_ich_descriptor_region(cs, desc);
128 prettyprint_ich_descriptor_master(cs, desc);
Nico Huberad186312016-05-02 15:15:29 +0200129#ifdef ICH_DESCRIPTORS_FROM_DUMP_ONLY
Stefan Taunerb3850962011-12-24 00:00:32 +0000130 if (cs >= CHIPSET_ICH8) {
131 prettyprint_ich_descriptor_upper_map(&desc->upper);
132 prettyprint_ich_descriptor_straps(cs, desc);
133 }
Nico Huberad186312016-05-02 15:15:29 +0200134#endif /* ICH_DESCRIPTORS_FROM_DUMP_ONLY */
Stefan Tauner1e146392011-09-15 23:52:55 +0000135}
136
Nico Huberfa622942017-03-24 17:25:37 +0100137void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *cont)
Stefan Tauner1e146392011-09-15 23:52:55 +0000138{
139 msg_pdbg2("=== Content Section ===\n");
140 msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG);
141 msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0);
142 msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1);
143 msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2);
144 msg_pdbg2("\n");
145
146 msg_pdbg2("--- Details ---\n");
Nico Huberfa622942017-03-24 17:25:37 +0100147 msg_pdbg2("NR (Number of Regions): %5zd\n", ich_number_of_regions(cs, cont));
148 msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont));
149 msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1);
150 msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont));
Nico Huberd2d39932019-01-18 16:49:37 +0100151 msg_pdbg2("ISL (ICH/PCH/SoC Strap Length): %5d\n", cont->ISL);
152 msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x%03x\n", getFISBA(cont));
Nico Huberfa622942017-03-24 17:25:37 +0100153 msg_pdbg2("NM (Number of Masters): %5zd\n", ich_number_of_masters(cs, cont));
154 msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont));
155 msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL);
156 msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", getFMSBA(cont));
Stefan Tauner1e146392011-09-15 23:52:55 +0000157 msg_pdbg2("\n");
158}
159
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000160static const char *pprint_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx)
161{
162 if (idx > 1) {
163 msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n");
164 return NULL;
165 }
166
167 if (desc->content.NC == 0 && idx > 0)
168 return "unused";
169
170 static const char * const size_str[] = {
171 "512 kB", /* 0000 */
172 "1 MB", /* 0001 */
173 "2 MB", /* 0010 */
174 "4 MB", /* 0011 */
175 "8 MB", /* 0100 */
176 "16 MB", /* 0101 */ /* Maximum up to Lynx Point (excl.) */
177 "32 MB", /* 0110 */
178 "64 MB", /* 0111 */
179 };
180
181 switch (cs) {
182 case CHIPSET_ICH8:
183 case CHIPSET_ICH9:
184 case CHIPSET_ICH10:
185 case CHIPSET_5_SERIES_IBEX_PEAK:
186 case CHIPSET_6_SERIES_COUGAR_POINT:
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000187 case CHIPSET_7_SERIES_PANTHER_POINT:
188 case CHIPSET_BAYTRAIL: {
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000189 uint8_t size_enc;
190 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000191 size_enc = desc->component.dens_old.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000192 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000193 size_enc = desc->component.dens_old.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000194 }
195 if (size_enc > 5)
196 return "reserved";
197 return size_str[size_enc];
198 }
199 case CHIPSET_8_SERIES_LYNX_POINT:
200 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Duncan Laurie823096e2014-08-20 15:39:38 +0000201 case CHIPSET_8_SERIES_WELLSBURG:
Nico Huber51205912017-03-17 17:59:54 +0100202 case CHIPSET_9_SERIES_WILDCAT_POINT:
Nico Huberfa622942017-03-24 17:25:37 +0100203 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
David Hendricksa5216362017-08-08 20:02:22 -0700204 case CHIPSET_100_SERIES_SUNRISE_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +0100205 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200206 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200207 case CHIPSET_500_SERIES_TIGER_POINT:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200208 case CHIPSET_APOLLO_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +0100209 case CHIPSET_GEMINI_LAKE:
210 case CHIPSET_ELKHART_LAKE: {
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000211 uint8_t size_enc;
212 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000213 size_enc = desc->component.dens_new.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000214 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000215 size_enc = desc->component.dens_new.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000216 }
217 if (size_enc > 7)
218 return "reserved";
219 return size_str[size_enc];
220 }
221 case CHIPSET_ICH_UNKNOWN:
222 default:
223 return "unknown";
224 }
225}
226
227static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
Stefan Tauner1e146392011-09-15 23:52:55 +0000228{
Werner Zehe57d4e42022-01-03 09:44:29 +0100229 static const char *const freq_str[5][8] = { {
Nico Huber129e9382019-06-06 15:43:27 +0200230 "20 MHz",
231 "33 MHz",
232 "reserved",
233 "reserved",
234 "50 MHz", /* New since Ibex Peak */
235 "reserved",
236 "reserved",
237 "reserved"
Nico Huberfa622942017-03-24 17:25:37 +0100238 }, {
Nico Huber129e9382019-06-06 15:43:27 +0200239 "reserved",
240 "reserved",
241 "48 MHz",
242 "reserved",
243 "30 MHz",
244 "reserved",
245 "17 MHz",
246 "reserved"
Nico Huberd2d39932019-01-18 16:49:37 +0100247 }, {
248 "reserved",
249 "50 MHz",
250 "40 MHz",
251 "reserved",
252 "25 MHz",
253 "reserved",
254 "14 MHz / 17 MHz",
255 "reserved"
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200256 }, {
257 "100 MHz",
258 "50 MHz",
259 "reserved",
260 "33 MHz",
261 "25 MHz",
262 "reserved",
263 "14 MHz",
264 "reserved"
Werner Zehe57d4e42022-01-03 09:44:29 +0100265 }, {
266 "reserved",
267 "50 MHz",
268 "reserved",
269 "reserved",
270 "33 MHz",
271 "20 MHz",
272 "reserved",
273 "reserved",
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200274 }};
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000275
276 switch (cs) {
277 case CHIPSET_ICH8:
278 case CHIPSET_ICH9:
279 case CHIPSET_ICH10:
280 if (value > 1)
281 return "reserved";
Richard Hughesdb7482b2018-12-19 12:04:30 +0000282 /* Fall through. */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000283 case CHIPSET_5_SERIES_IBEX_PEAK:
284 case CHIPSET_6_SERIES_COUGAR_POINT:
285 case CHIPSET_7_SERIES_PANTHER_POINT:
286 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000287 case CHIPSET_BAYTRAIL:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000288 case CHIPSET_8_SERIES_LYNX_POINT_LP:
289 case CHIPSET_8_SERIES_WELLSBURG:
Duncan Laurie823096e2014-08-20 15:39:38 +0000290 case CHIPSET_9_SERIES_WILDCAT_POINT:
Nico Huber51205912017-03-17 17:59:54 +0100291 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huberfa622942017-03-24 17:25:37 +0100292 return freq_str[0][value];
293 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700294 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200295 case CHIPSET_300_SERIES_CANNON_POINT:
Nico Huberfa622942017-03-24 17:25:37 +0100296 return freq_str[1][value];
Nico Huberd2d39932019-01-18 16:49:37 +0100297 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200298 case CHIPSET_GEMINI_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +0100299 return freq_str[2][value];
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200300 case CHIPSET_500_SERIES_TIGER_POINT:
301 return freq_str[3][value];
Werner Zehe57d4e42022-01-03 09:44:29 +0100302 case CHIPSET_ELKHART_LAKE:
303 return freq_str[4][value];
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000304 case CHIPSET_ICH_UNKNOWN:
305 default:
306 return "unknown";
307 }
308}
309
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200310static void pprint_read_freq(enum ich_chipset cs, uint8_t value)
311{
312 static const char *const freq_str[1][8] = { {
313 "20 MHz",
314 "24 MHz",
315 "30 MHz",
316 "48 MHz",
317 "60 MHz",
318 "reserved",
319 "reserved",
320 "reserved"
321 }};
322
323 switch (cs) {
324 case CHIPSET_300_SERIES_CANNON_POINT:
325 msg_pdbg2("eSPI/EC Bus Clock Frequency: %s\n", freq_str[0][value]);
326 return;
327 case CHIPSET_500_SERIES_TIGER_POINT:
328 msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
329 return;
330 default:
331 msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, value));
332 return;
333 }
334}
335
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000336void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc)
337{
Nico Huberd2d39932019-01-18 16:49:37 +0100338 bool has_flill1;
339
340 switch (cs) {
341 case CHIPSET_100_SERIES_SUNRISE_POINT:
342 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200343 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200344 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +0100345 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200346 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +0100347 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +0100348 has_flill1 = true;
349 break;
350 default:
351 has_flill1 = false;
352 break;
353 }
Stefan Tauner1e146392011-09-15 23:52:55 +0000354
355 msg_pdbg2("=== Component Section ===\n");
356 msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP);
357 msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL );
Nico Huberd2d39932019-01-18 16:49:37 +0100358 if (has_flill1)
Nico Huberfa622942017-03-24 17:25:37 +0100359 msg_pdbg2("FLILL1 0x%08x\n", desc->component.FLILL1);
Stefan Tauner1e146392011-09-15 23:52:55 +0000360 msg_pdbg2("\n");
361
362 msg_pdbg2("--- Details ---\n");
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000363 msg_pdbg2("Component 1 density: %s\n", pprint_density(cs, desc, 0));
Stefan Tauner1e146392011-09-15 23:52:55 +0000364 if (desc->content.NC)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000365 msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1));
Stefan Tauner1e146392011-09-15 23:52:55 +0000366 else
367 msg_pdbg2("Component 2 is not used.\n");
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200368
369 pprint_read_freq(cs, desc->component.modes.freq_read);
370
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000371 msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id));
372 msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_write));
373 msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not ");
374 if (desc->component.modes.fastread)
Stefan Tauner1e146392011-09-15 23:52:55 +0000375 msg_pdbg2("Fast Read Clock Frequency: %s\n",
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000376 pprint_freq(cs, desc->component.modes.freq_fastread));
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000377 if (cs > CHIPSET_6_SERIES_COUGAR_POINT)
378 msg_pdbg2("Dual Output Fast Read Support: %sabled\n",
Werner Zehd3e8fd92022-01-25 07:02:49 +0100379 desc->component.modes.dual_output ? "en" : "dis");
David Hendricksa5216362017-08-08 20:02:22 -0700380
Felix Singerd68a0ec2022-08-19 03:23:35 +0200381 bool has_forbidden_opcode = false;
David Hendricksa5216362017-08-08 20:02:22 -0700382 if (desc->component.FLILL != 0) {
Felix Singerd68a0ec2022-08-19 03:23:35 +0200383 has_forbidden_opcode = true;
Stefan Tauner1e146392011-09-15 23:52:55 +0000384 msg_pdbg2("Invalid instruction 0: 0x%02x\n",
385 desc->component.invalid_instr0);
386 msg_pdbg2("Invalid instruction 1: 0x%02x\n",
387 desc->component.invalid_instr1);
388 msg_pdbg2("Invalid instruction 2: 0x%02x\n",
389 desc->component.invalid_instr2);
390 msg_pdbg2("Invalid instruction 3: 0x%02x\n",
391 desc->component.invalid_instr3);
David Hendricksa5216362017-08-08 20:02:22 -0700392 }
Nico Huberd2d39932019-01-18 16:49:37 +0100393 if (has_flill1) {
David Hendricksa5216362017-08-08 20:02:22 -0700394 if (desc->component.FLILL1 != 0) {
Felix Singerd68a0ec2022-08-19 03:23:35 +0200395 has_forbidden_opcode = true;
Nico Huberfa622942017-03-24 17:25:37 +0100396 msg_pdbg2("Invalid instruction 4: 0x%02x\n",
397 desc->component.invalid_instr4);
398 msg_pdbg2("Invalid instruction 5: 0x%02x\n",
399 desc->component.invalid_instr5);
400 msg_pdbg2("Invalid instruction 6: 0x%02x\n",
401 desc->component.invalid_instr6);
402 msg_pdbg2("Invalid instruction 7: 0x%02x\n",
403 desc->component.invalid_instr7);
404 }
Stefan Tauner1e146392011-09-15 23:52:55 +0000405 }
David Hendricksa5216362017-08-08 20:02:22 -0700406 if (!has_forbidden_opcode)
407 msg_pdbg2("No forbidden opcodes.\n");
408
Stefan Tauner1e146392011-09-15 23:52:55 +0000409 msg_pdbg2("\n");
410}
411
412static void pprint_freg(const struct ich_desc_region *reg, uint32_t i)
413{
Nico Huberfa622942017-03-24 17:25:37 +0100414 static const char *const region_names[] = {
Nico Huberd2d39932019-01-18 16:49:37 +0100415 "Descr.", "BIOS", "ME", "GbE", "Platf.", "DevExp", "BIOS2", "unknown",
David Hendricksa5216362017-08-08 20:02:22 -0700416 "EC/BMC", "unknown", "IE", "10GbE", "unknown", "unknown", "unknown", "unknown"
Stefan Tauner1e146392011-09-15 23:52:55 +0000417 };
Nico Huberfa622942017-03-24 17:25:37 +0100418 if (i >= ARRAY_SIZE(region_names)) {
Stefan Tauner1e146392011-09-15 23:52:55 +0000419 msg_pdbg2("%s: region index too high.\n", __func__);
420 return;
421 }
422 uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]);
423 uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]);
Nico Huberfa622942017-03-24 17:25:37 +0100424 msg_pdbg2("Region %d (%-7s) ", i, region_names[i]);
Stefan Tauner1e146392011-09-15 23:52:55 +0000425 if (base > limit)
426 msg_pdbg2("is unused.\n");
427 else
Nico Huber0bb3f712017-03-29 16:44:33 +0200428 msg_pdbg2("0x%08x - 0x%08x\n", base, limit);
Stefan Tauner1e146392011-09-15 23:52:55 +0000429}
430
Nico Huberfa622942017-03-24 17:25:37 +0100431void prettyprint_ich_descriptor_region(const enum ich_chipset cs, const struct ich_descriptors *const desc)
Stefan Tauner1e146392011-09-15 23:52:55 +0000432{
Nico Huber519be662018-12-23 20:03:35 +0100433 ssize_t i;
Nico Huberfa622942017-03-24 17:25:37 +0100434 const ssize_t nr = ich_number_of_regions(cs, &desc->content);
Stefan Tauner1e146392011-09-15 23:52:55 +0000435 msg_pdbg2("=== Region Section ===\n");
Nico Huberfa622942017-03-24 17:25:37 +0100436 if (nr < 0) {
Stefan Tauner1e146392011-09-15 23:52:55 +0000437 msg_pdbg2("%s: number of regions too high (%d).\n", __func__,
Nico Huberfa622942017-03-24 17:25:37 +0100438 desc->content.NR + 1);
Stefan Tauner1e146392011-09-15 23:52:55 +0000439 return;
440 }
Nico Huberfa622942017-03-24 17:25:37 +0100441 for (i = 0; i < nr; i++)
Nico Huber519be662018-12-23 20:03:35 +0100442 msg_pdbg2("FLREG%zd 0x%08x\n", i, desc->region.FLREGs[i]);
Stefan Tauner1e146392011-09-15 23:52:55 +0000443 msg_pdbg2("\n");
444
445 msg_pdbg2("--- Details ---\n");
Nico Huberfa622942017-03-24 17:25:37 +0100446 for (i = 0; i < nr; i++)
Nico Huber519be662018-12-23 20:03:35 +0100447 pprint_freg(&desc->region, (uint32_t)i);
Stefan Tauner1e146392011-09-15 23:52:55 +0000448 msg_pdbg2("\n");
449}
450
Nico Huberfa622942017-03-24 17:25:37 +0100451void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct ich_descriptors *const desc)
Stefan Tauner1e146392011-09-15 23:52:55 +0000452{
Nico Huber519be662018-12-23 20:03:35 +0100453 ssize_t i;
Nico Huberfa622942017-03-24 17:25:37 +0100454 const ssize_t nm = ich_number_of_masters(cs, &desc->content);
Stefan Tauner1e146392011-09-15 23:52:55 +0000455 msg_pdbg2("=== Master Section ===\n");
Nico Huberfa622942017-03-24 17:25:37 +0100456 if (nm < 0) {
457 msg_pdbg2("%s: number of masters too high (%d).\n", __func__,
458 desc->content.NM + 1);
459 return;
460 }
461 for (i = 0; i < nm; i++)
Nico Huber519be662018-12-23 20:03:35 +0100462 msg_pdbg2("FLMSTR%zd 0x%08x\n", i + 1, desc->master.FLMSTRs[i]);
Stefan Tauner1e146392011-09-15 23:52:55 +0000463 msg_pdbg2("\n");
464
465 msg_pdbg2("--- Details ---\n");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200466 if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200467 cs == CHIPSET_300_SERIES_CANNON_POINT ||
468 cs == CHIPSET_500_SERIES_TIGER_POINT) {
Nico Huberfa622942017-03-24 17:25:37 +0100469 const char *const master_names[] = {
470 "BIOS", "ME", "GbE", "unknown", "EC",
471 };
Nico Huber519be662018-12-23 20:03:35 +0100472 if (nm >= (ssize_t)ARRAY_SIZE(master_names)) {
Nico Huberfa622942017-03-24 17:25:37 +0100473 msg_pdbg2("%s: number of masters too high (%d).\n", __func__,
474 desc->content.NM + 1);
475 return;
476 }
477
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200478 size_t num_regions;
479 msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9");
480 if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) {
481 num_regions = 10;
482 msg_pdbg2("\n");
483 } else {
484 num_regions = 16;
485 msg_pdbg2(" RegA RegB RegC RegD RegE RegF\n");
486 }
Nico Huberfa622942017-03-24 17:25:37 +0100487 for (i = 0; i < nm; i++) {
aarya0ac29562022-03-13 15:35:12 +0530488 const unsigned int ext_region_start = 12;
Nico Huberfa622942017-03-24 17:25:37 +0100489 size_t j;
490 msg_pdbg2("%-4s", master_names[i]);
aarya0ac29562022-03-13 15:35:12 +0530491 for (j = 0; j < (size_t)min(num_regions, ext_region_start); j++)
Nico Huberfa622942017-03-24 17:25:37 +0100492 msg_pdbg2(" %c%c ",
493 desc->master.mstr[i].read & (1 << j) ? 'r' : ' ',
494 desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
aarya0ac29562022-03-13 15:35:12 +0530495 for (j = ext_region_start; j < num_regions; j++)
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200496 msg_pdbg2(" %c%c ",
aarya0ac29562022-03-13 15:35:12 +0530497 desc->master.mstr[i].ext_read & (1 << (j - ext_region_start)) ? 'r' : ' ',
498 desc->master.mstr[i].ext_write & (1 << (j - ext_region_start)) ? 'w' : ' ');
Nico Huberfa622942017-03-24 17:25:37 +0100499 msg_pdbg2("\n");
500 }
David Hendricksa5216362017-08-08 20:02:22 -0700501 } else if (cs == CHIPSET_C620_SERIES_LEWISBURG) {
502 const char *const master_names[] = {
503 "BIOS", "ME", "GbE", "DE", "BMC", "IE",
504 };
505 /* NM starts at 1 instead of 0 for LBG */
Nico Huber519be662018-12-23 20:03:35 +0100506 if (nm > (ssize_t)ARRAY_SIZE(master_names)) {
David Hendricksa5216362017-08-08 20:02:22 -0700507 msg_pdbg2("%s: number of masters too high (%d).\n", __func__,
508 desc->content.NM);
509 return;
510 }
511
512 msg_pdbg2("%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n",
513 " ", /* width of master name (4 chars minimum) */
514 " FD ", " BIOS", " ME ", " GbE ", " Pltf",
515 " DE ", "BIOS2", " Reg7", " BMC ", " DE2 ",
516 " IE ", "10GbE", "OpROM", "Reg13", "Reg14",
517 "Reg15");
518 for (i = 0; i < nm; i++) {
519 size_t j;
520 msg_pdbg2("%-4s", master_names[i]);
521 for (j = 0; j < 16; j++)
522 msg_pdbg2(" %c%c ",
523 desc->master.mstr[i].read & (1 << j) ? 'r' : ' ',
524 desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
525 msg_pdbg2("\n");
526 }
Werner Zehe57d4e42022-01-03 09:44:29 +0100527 } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE || cs == CHIPSET_ELKHART_LAKE) {
Nico Huberd2d39932019-01-18 16:49:37 +0100528 const char *const master_names[] = { "BIOS", "TXE", };
Nico Huber519be662018-12-23 20:03:35 +0100529 if (nm > (ssize_t)ARRAY_SIZE(master_names)) {
Nico Huberd2d39932019-01-18 16:49:37 +0100530 msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM);
531 return;
532 }
533
534 msg_pdbg2(" FD IFWI TXE n/a Platf DevExp\n");
535 for (i = 0; i < nm; i++) {
Nico Huber519be662018-12-23 20:03:35 +0100536 ssize_t j;
Nico Huberd2d39932019-01-18 16:49:37 +0100537 msg_pdbg2("%-4s", master_names[i]);
538 for (j = 0; j < ich_number_of_regions(cs, &desc->content); j++)
539 msg_pdbg2(" %c%c ",
540 desc->master.mstr[i].read & (1 << j) ? 'r' : ' ',
541 desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
542 msg_pdbg2("\n");
543 }
Nico Huberfa622942017-03-24 17:25:37 +0100544 } else {
545 const struct ich_desc_master *const mstr = &desc->master;
546 msg_pdbg2(" Descr. BIOS ME GbE Platf.\n");
547 msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n",
548 (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ',
549 (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ',
550 (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ',
551 (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ',
552 (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' ');
553 msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n",
554 (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ',
555 (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ',
556 (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ',
557 (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ',
558 (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' ');
559 msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n",
560 (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ',
561 (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ',
562 (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ',
563 (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ',
564 (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' ');
565 }
Stefan Tauner1e146392011-09-15 23:52:55 +0000566 msg_pdbg2("\n");
567}
568
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600569static void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc)
Stefan Taunerb3850962011-12-24 00:00:32 +0000570{
571 static const char * const str_GPIO12[4] = {
572 "GPIO12",
573 "LAN PHY Power Control Function (Native Output)",
574 "GLAN_DOCK# (Native Input)",
575 "invalid configuration",
576 };
577
578 msg_pdbg2("--- MCH details ---\n");
579 msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en");
580 msg_pdbg2("\n");
581
582 msg_pdbg2("--- ICH details ---\n");
583 msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD);
584 msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2);
585 msg_pdbg2("ME SMBus Controller is connected to the %s.\n",
586 desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins");
587 msg_pdbg2("SPI CS1 is used for %s.\n",
588 desc->south.ich8.SPICS1_LANPHYPC_SEL ?
589 "LAN PHY Power Control Function" :
590 "SPI Chip Select");
591 msg_pdbg2("GPIO12 is used as %s.\n",
592 str_GPIO12[desc->south.ich8.GPIO12_SEL]);
593 msg_pdbg2("PCIe Port 6 is used for %s.\n",
594 desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express");
595 msg_pdbg2("%sn BMC Mode: "
596 "Intel AMT SMBus Controller 1 is connected to %s.\n",
597 desc->south.ich8.BMCMODE ? "I" : "Not i",
598 desc->south.ich8.BMCMODE ? "SMLink" : "SMBus");
599 msg_pdbg2("TCO is in %s Mode.\n",
600 desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible");
601 msg_pdbg2("ME A is %sabled.\n",
602 desc->south.ich8.ME_DISABLE ? "dis" : "en");
603 msg_pdbg2("\n");
604}
605
606static void prettyprint_ich_descriptor_straps_56_pciecs(uint8_t conf, uint8_t off)
607{
608 msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1);
609
610 off *= 4;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000611 switch (conf){
Stefan Taunerb3850962011-12-24 00:00:32 +0000612 case 0:
613 msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off);
614 break;
615 case 1:
616 msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), "
617 "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off);
618 break;
619 case 2:
620 msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports "
621 "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off);
622 break;
623 case 3:
624 msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)",
625 1+off, 2+off, 4+off);
626 break;
627 }
628 msg_pdbg2("\n");
629}
630
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600631static void prettyprint_ich_descriptor_pchstraps45678_56(const struct ich_desc_south_strap *s)
Stefan Taunerb3850962011-12-24 00:00:32 +0000632{
633 /* PCHSTRP4 */
634 msg_pdbg2("Intel PHY is %s.\n",
635 (s->ibex.PHYCON == 2) ? "connected" :
636 (s->ibex.PHYCON == 0) ? "disconnected" : "reserved");
637 msg_pdbg2("GbE MAC SMBus address is %sabled.\n",
638 s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis");
639 msg_pdbg2("GbE MAC SMBus address: 0x%02x\n",
640 s->ibex.GBEMAC_SMBUS_ADDR);
641 msg_pdbg2("GbE PHY SMBus address: 0x%02x\n",
642 s->ibex.GBEPHY_SMBUS_ADDR);
643
644 /* PCHSTRP5 */
645 /* PCHSTRP6 */
646 /* PCHSTRP7 */
647 msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n",
648 s->ibex.MESMA2UDID_VENDOR);
649 msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n",
650 s->ibex.MESMA2UDID_VENDOR);
651
652 /* PCHSTRP8 */
653}
654
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600655static void prettyprint_ich_descriptor_pchstraps111213_56(const struct ich_desc_south_strap *s)
Stefan Taunerb3850962011-12-24 00:00:32 +0000656{
657 /* PCHSTRP11 */
658 msg_pdbg2("SMLink1 GP Address is %sabled.\n",
659 s->ibex.SML1GPAEN ? "en" : "dis");
660 msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n",
661 s->ibex.SML1GPA);
662 msg_pdbg2("SMLink1 I2C Target address is %sabled.\n",
663 s->ibex.SML1I2CAEN ? "en" : "dis");
664 msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n",
665 s->ibex.SML1I2CA);
666
667 /* PCHSTRP12 */
668 /* PCHSTRP13 */
669}
670
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600671static void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s)
Stefan Taunerb3850962011-12-24 00:00:32 +0000672{
Stefan Tauner67d163d2013-01-15 17:37:48 +0000673 static const uint8_t dec_t209min[4] = {
Stefan Taunerb3850962011-12-24 00:00:32 +0000674 100,
675 50,
676 5,
677 1
678 };
679
680 msg_pdbg2("--- PCH ---\n");
681
682 /* PCHSTRP0 */
683 msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2);
684 msg_pdbg2("Intel ME SMBus Select is %sabled.\n",
685 s->ibex.SMB_EN ? "en" : "dis");
686 msg_pdbg2("SMLink0 segment is %sabled.\n",
687 s->ibex.SML0_EN ? "en" : "dis");
688 msg_pdbg2("SMLink1 segment is %sabled.\n",
689 s->ibex.SML1_EN ? "en" : "dis");
690 msg_pdbg2("SMLink1 Frequency: %s\n",
691 (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved");
692 msg_pdbg2("Intel ME SMBus Frequency: %s\n",
693 (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved");
694 msg_pdbg2("SMLink0 Frequency: %s\n",
695 (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved");
696 msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ?
697 "LAN_PHY_PWR_CTRL" : "general purpose output");
698 msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->ibex.cs_ss1);
699 msg_pdbg2("DMI RequesterID Checks are %sabled.\n",
700 s->ibex.DMI_REQID_DIS ? "en" : "dis");
701 msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n",
702 1 << (6 + s->ibex.BBBS));
703
704 /* PCHSTRP1 */
705 msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3);
706
707 /* PCHSTRP2 */
708 msg_pdbg2("ME SMBus ASD address is %sabled.\n",
709 s->ibex.MESMASDEN ? "en" : "dis");
710 msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n",
711 s->ibex.MESMASDA);
712 msg_pdbg2("ME SMBus I2C address is %sabled.\n",
713 s->ibex.MESMI2CEN ? "en" : "dis");
714 msg_pdbg2("ME SMBus I2C target address: 0x%02x\n",
715 s->ibex.MESMI2CA);
716
717 /* PCHSTRP3 */
718 prettyprint_ich_descriptor_pchstraps45678_56(s);
719 /* PCHSTRP9 */
720 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0);
721 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1);
722 msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n",
723 s->ibex.PCIELR1 ? "" : "not ");
724 msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n",
725 s->ibex.PCIELR2 ? "" : "not ");
726 msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n",
727 s->ibex.DMILR ? "" : "not ");
728 msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1);
729 msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n",
730 s->ibex.PHY_PCIE_EN ? "en" : "dis");
731
732 /* PCHSTRP10 */
733 msg_pdbg2("Management Engine will boot from %sflash.\n",
734 s->ibex.ME_BOOT_FLASH ? "" : "ROM, then ");
735 msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5);
736 msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n",
737 s->ibex.VE_EN ? "en" : "dis");
738 msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n",
739 s->ibex.MMDDE ? "en" : "dis");
740 msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n",
741 s->ibex.MMADDR);
742 msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7);
743 msg_pdbg2("Integrated Clocking Configuration is %d.\n",
744 (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL);
745 msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a "
746 "reset.\n", s->ibex.MER_CL1 ? "" : "not ");
747
748 prettyprint_ich_descriptor_pchstraps111213_56(s);
749
750 /* PCHSTRP14 */
751 msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n",
752 s->ibex.VE_EN2 ? "en" : "dis");
753 msg_pdbg2("Virtualization Engine will boot from %sflash.\n",
754 s->ibex.VE_BOOT_FLASH ? "" : "ROM, then ");
755 msg_pdbg2("Braidwood SSD functionality is %sabled.\n",
756 s->ibex.BW_SSD ? "en" : "dis");
757 msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n",
758 s->ibex.NVMHCI_EN ? "en" : "dis");
759
760 /* PCHSTRP15 */
761 msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6);
762 msg_pdbg2("Integrated wired LAN Solution is %sabled.\n",
763 s->ibex.IWL_EN ? "en" : "dis");
764 msg_pdbg2("t209 min Timing: %d ms\n",
765 dec_t209min[s->ibex.t209min]);
766 msg_pdbg2("\n");
767}
768
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600769static void prettyprint_ich_descriptor_straps_cougar(const struct ich_desc_south_strap *s)
Stefan Taunerb3850962011-12-24 00:00:32 +0000770{
771 msg_pdbg2("--- PCH ---\n");
772
773 /* PCHSTRP0 */
774 msg_pdbg2("Chipset configuration Softstrap 1: %d\n", s->cougar.cs_ss1);
775 msg_pdbg2("Intel ME SMBus Select is %sabled.\n",
776 s->ibex.SMB_EN ? "en" : "dis");
777 msg_pdbg2("SMLink0 segment is %sabled.\n",
778 s->ibex.SML0_EN ? "en" : "dis");
779 msg_pdbg2("SMLink1 segment is %sabled.\n",
780 s->ibex.SML1_EN ? "en" : "dis");
781 msg_pdbg2("SMLink1 Frequency: %s\n",
782 (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved");
783 msg_pdbg2("Intel ME SMBus Frequency: %s\n",
784 (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved");
785 msg_pdbg2("SMLink0 Frequency: %s\n",
786 (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved");
787 msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ?
788 "LAN_PHY_PWR_CTRL" : "general purpose output");
789 msg_pdbg2("LinkSec is %sabled.\n",
790 s->cougar.LINKSEC_DIS ? "en" : "dis");
791 msg_pdbg2("DMI RequesterID Checks are %sabled.\n",
792 s->ibex.DMI_REQID_DIS ? "en" : "dis");
793 msg_pdbg2("BIOS Boot-Block size (BBBS): %d kB.\n",
794 1 << (6 + s->ibex.BBBS));
795
796 /* PCHSTRP1 */
797 msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3);
798 msg_pdbg2("Chipset configuration Softstrap 2: 0x%x\n", s->ibex.cs_ss2);
799
800 /* PCHSTRP2 */
801 msg_pdbg2("ME SMBus ASD address is %sabled.\n",
802 s->ibex.MESMASDEN ? "en" : "dis");
803 msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n",
804 s->ibex.MESMASDA);
805 msg_pdbg2("ME SMBus MCTP Address is %sabled.\n",
806 s->cougar.MESMMCTPAEN ? "en" : "dis");
807 msg_pdbg2("ME SMBus MCTP target address: 0x%02x\n",
808 s->cougar.MESMMCTPA);
809 msg_pdbg2("ME SMBus I2C address is %sabled.\n",
810 s->ibex.MESMI2CEN ? "en" : "dis");
811 msg_pdbg2("ME SMBus I2C target address: 0x%02x\n",
812 s->ibex.MESMI2CA);
813
814 /* PCHSTRP3 */
815 prettyprint_ich_descriptor_pchstraps45678_56(s);
816 /* PCHSTRP9 */
817 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 0);
818 prettyprint_ich_descriptor_straps_56_pciecs(s->ibex.PCIEPCS1, 1);
819 msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n",
820 s->ibex.PCIELR1 ? "" : "not ");
821 msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n",
822 s->ibex.PCIELR2 ? "" : "not ");
823 msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n",
824 s->ibex.DMILR ? "" : "not ");
825 msg_pdbg2("ME Debug status writes over SMBUS are %sabled.\n",
826 s->cougar.MDSMBE_EN ? "en" : "dis");
827 msg_pdbg2("ME Debug SMBus Emergency Mode address: 0x%02x (raw)\n",
828 s->cougar.MDSMBE_ADD);
829 msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1);
830 msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n",
831 s->ibex.PHY_PCIE_EN ? "en" : "dis");
832 msg_pdbg2("PCIe ports Subtractive Decode Agent is %sabled.\n",
833 s->cougar.SUB_DECODE_EN ? "en" : "dis");
834 msg_pdbg2("GPIO74 is used as %s.\n", s->cougar.PCHHOT_SML1ALERT_SEL ?
835 "PCHHOT#" : "SML1ALERT#");
836
837 /* PCHSTRP10 */
838 msg_pdbg2("Management Engine will boot from %sflash.\n",
839 s->ibex.ME_BOOT_FLASH ? "" : "ROM, then ");
840
841 msg_pdbg2("ME Debug SMBus Emergency Mode is %sabled.\n",
842 s->cougar.MDSMBE_EN ? "en" : "dis");
843 msg_pdbg2("ME Debug SMBus Emergency Mode Address: 0x%02x\n",
844 s->cougar.MDSMBE_ADD);
845
846 msg_pdbg2("Integrated Clocking Configuration used: %d\n",
847 s->cougar.ICC_SEL);
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000848 msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a reset.\n",
849 s->ibex.MER_CL1 ? "" : "not ");
Stefan Taunerb3850962011-12-24 00:00:32 +0000850 msg_pdbg2("ICC Profile is selected by %s.\n",
851 s->cougar.ICC_PRO_SEL ? "Softstraps" : "BIOS");
852 msg_pdbg2("Deep SX is %ssupported on the platform.\n",
853 s->cougar.Deep_SX_EN ? "not " : "");
854 msg_pdbg2("ME Debug LAN Emergency Mode is %sabled.\n",
855 s->cougar.ME_DBG_LAN ? "en" : "dis");
856
857 prettyprint_ich_descriptor_pchstraps111213_56(s);
858
859 /* PCHSTRP14 */
860 /* PCHSTRP15 */
861 msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->cougar.cs_ss6);
862 msg_pdbg2("Integrated wired LAN is %sabled.\n",
863 s->cougar.IWL_EN ? "en" : "dis");
864 msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->cougar.cs_ss5);
865 msg_pdbg2("SMLink1 provides temperature from %s.\n",
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000866 s->cougar.SMLINK1_THERM_SEL ? "PCH only" : "the CPU, PCH and DIMMs");
Stefan Taunerb3850962011-12-24 00:00:32 +0000867 msg_pdbg2("GPIO29 is used as %s.\n", s->cougar.SLP_LAN_GP29_SEL ?
868 "general purpose output" : "SLP_LAN#");
869
870 /* PCHSTRP16 */
871 /* PCHSTRP17 */
872 msg_pdbg2("Integrated Clock: %s Clock Mode\n",
873 s->cougar.ICML ? "Buffered Through" : "Full Integrated");
874 msg_pdbg2("\n");
875}
876
877void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc)
878{
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000879 unsigned int i, max_count;
Stefan Taunerb3850962011-12-24 00:00:32 +0000880 msg_pdbg2("=== Softstraps ===\n");
881
Nico Huber519be662018-12-23 20:03:35 +0100882 max_count = MIN(ARRAY_SIZE(desc->north.STRPs), desc->content.MSL);
Nico Huberd7c75522017-03-29 16:31:49 +0200883 if (max_count < desc->content.MSL) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000884 msg_pdbg2("MSL (%u) is greater than the current maximum of %u entries.\n",
Nico Huberd7c75522017-03-29 16:31:49 +0200885 desc->content.MSL, max_count);
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000886 msg_pdbg2("Only the first %u entries will be printed.\n", max_count);
Nico Huberd7c75522017-03-29 16:31:49 +0200887 }
Stefan Taunerb3850962011-12-24 00:00:32 +0000888
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000889 msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max_count);
890 for (i = 0; i < max_count; i++)
Stefan Taunerb3850962011-12-24 00:00:32 +0000891 msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]);
892 msg_pdbg2("\n");
893
Nico Huber519be662018-12-23 20:03:35 +0100894 max_count = MIN(ARRAY_SIZE(desc->south.STRPs), desc->content.ISL);
Nico Huberd7c75522017-03-29 16:31:49 +0200895 if (max_count < desc->content.ISL) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000896 msg_pdbg2("ISL (%u) is greater than the current maximum of %u entries.\n",
897 desc->content.ISL, max_count);
898 msg_pdbg2("Only the first %u entries will be printed.\n", max_count);
Nico Huberd7c75522017-03-29 16:31:49 +0200899 }
Stefan Taunerb3850962011-12-24 00:00:32 +0000900
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000901 msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max_count);
902 for (i = 0; i < max_count; i++)
Stefan Taunerb3850962011-12-24 00:00:32 +0000903 msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]);
904 msg_pdbg2("\n");
905
906 switch (cs) {
907 case CHIPSET_ICH8:
908 if (sizeof(desc->north.ich8) / 4 != desc->content.MSL)
909 msg_pdbg2("Detailed North/MCH/PROC information is "
910 "probably not reliable, printing anyway.\n");
911 if (sizeof(desc->south.ich8) / 4 != desc->content.ISL)
912 msg_pdbg2("Detailed South/ICH/PCH information is "
913 "probably not reliable, printing anyway.\n");
914 prettyprint_ich_descriptor_straps_ich8(desc);
915 break;
916 case CHIPSET_5_SERIES_IBEX_PEAK:
917 /* PCH straps only. PROCSTRPs are unknown. */
918 if (sizeof(desc->south.ibex) / 4 != desc->content.ISL)
919 msg_pdbg2("Detailed South/ICH/PCH information is "
920 "probably not reliable, printing anyway.\n");
921 prettyprint_ich_descriptor_straps_ibex(&desc->south);
922 break;
923 case CHIPSET_6_SERIES_COUGAR_POINT:
924 /* PCH straps only. PROCSTRP0 is "reserved". */
925 if (sizeof(desc->south.cougar) / 4 != desc->content.ISL)
926 msg_pdbg2("Detailed South/ICH/PCH information is "
927 "probably not reliable, printing anyway.\n");
928 prettyprint_ich_descriptor_straps_cougar(&desc->south);
929 break;
930 case CHIPSET_ICH_UNKNOWN:
931 break;
932 default:
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000933 msg_pdbg2("The meaning of the descriptor straps are unknown yet.\n\n");
Stefan Taunerb3850962011-12-24 00:00:32 +0000934 break;
935 }
936}
937
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600938static void prettyprint_rdid(uint32_t reg_val)
Stefan Taunerb3850962011-12-24 00:00:32 +0000939{
940 uint8_t mid = reg_val & 0xFF;
941 uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00);
942 msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did);
943}
944
945void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap)
946{
947 int i;
948 msg_pdbg2("=== Upper Map Section ===\n");
949 msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1);
950 msg_pdbg2("\n");
951
952 msg_pdbg2("--- Details ---\n");
953 msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL);
954 msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap));
955 msg_pdbg2("\n");
956
957 msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2);
Stefan Taunera1a14ec2012-08-13 08:45:13 +0000958 for (i = 0; i < umap->VTL/2; i++) {
Stefan Taunerb3850962011-12-24 00:00:32 +0000959 uint32_t jid = umap->vscc_table[i].JID;
960 uint32_t vscc = umap->vscc_table[i].VSCC;
961 msg_pdbg2(" JID%d = 0x%08x\n", i, jid);
962 msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc);
Martin Rothf6c1cb12022-03-15 10:55:25 -0600963 msg_pdbg2(" "); /* indentation */
Stefan Taunerb3850962011-12-24 00:00:32 +0000964 prettyprint_rdid(jid);
Martin Rothf6c1cb12022-03-15 10:55:25 -0600965 msg_pdbg2(" "); /* indentation */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000966 prettyprint_ich_reg_vscc(vscc, 0, false);
Stefan Taunerb3850962011-12-24 00:00:32 +0000967 }
968 msg_pdbg2("\n");
969}
970
David Hendricks66565a72021-09-20 21:56:40 -0700971static inline void warn_peculiar_desc(const char *const name)
Nico Huber964007a2021-06-17 21:12:47 +0200972{
Nico Huber964007a2021-06-17 21:12:47 +0200973 msg_pwarn("Peculiar flash descriptor, assuming %s compatibility.\n", name);
974}
975
Nico Huber1dc3d422017-06-17 00:09:31 +0200976/*
977 * Guesses a minimum chipset version based on the maximum number of
Nico Huber3ad9aad2021-06-17 22:05:00 +0200978 * soft straps per generation and presence of the MIP base (MDTBA).
Nico Huber1dc3d422017-06-17 00:09:31 +0200979 */
Nico Huber3ad9aad2021-06-17 22:05:00 +0200980static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_content *const content,
981 const struct ich_desc_upper_map *const upper)
Nico Huber1dc3d422017-06-17 00:09:31 +0200982{
983 if (content->ICCRIBA == 0x00) {
984 if (content->MSL == 0 && content->ISL <= 2)
985 return CHIPSET_ICH8;
Nico Huber83b01c82021-06-17 21:20:09 +0200986 if (content->ISL <= 2)
Nico Huber1dc3d422017-06-17 00:09:31 +0200987 return CHIPSET_ICH9;
Nico Huber83b01c82021-06-17 21:20:09 +0200988 if (content->ISL <= 10)
Nico Huber1dc3d422017-06-17 00:09:31 +0200989 return CHIPSET_ICH10;
David Hendricks66565a72021-09-20 21:56:40 -0700990 if (content->ISL <= 16)
991 return CHIPSET_5_SERIES_IBEX_PEAK;
Nico Huber83b01c82021-06-17 21:20:09 +0200992 if (content->FLMAP2 == 0) {
Nico Huber81965f32021-06-17 23:25:35 +0200993 if (content->ISL == 19)
994 return CHIPSET_APOLLO_LAKE;
David Hendricks66565a72021-09-20 21:56:40 -0700995 if (content->ISL == 23)
996 return CHIPSET_GEMINI_LAKE;
997 warn_peculiar_desc("Gemini Lake");
Nico Huber81965f32021-06-17 23:25:35 +0200998 return CHIPSET_GEMINI_LAKE;
Nico Huberd2d39932019-01-18 16:49:37 +0100999 }
Jonathan Zhang3bf7cfb2021-08-30 23:25:06 -07001000 if (content->ISL <= 80)
1001 return CHIPSET_C620_SERIES_LEWISBURG;
David Hendricks66565a72021-09-20 21:56:40 -07001002 warn_peculiar_desc("Ibex Peak");
Nico Huber1dc3d422017-06-17 00:09:31 +02001003 return CHIPSET_5_SERIES_IBEX_PEAK;
Nico Huber3ad9aad2021-06-17 22:05:00 +02001004 } else if (upper->MDTBA == 0x00) {
1005 if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) {
1006 if (content->MSL == 0 && content->ISL <= 17)
1007 return CHIPSET_BAYTRAIL;
1008 if (content->MSL <= 1 && content->ISL <= 18)
1009 return CHIPSET_6_SERIES_COUGAR_POINT;
David Hendricks66565a72021-09-20 21:56:40 -07001010 if (content->MSL <= 1 && content->ISL <= 21)
1011 return CHIPSET_8_SERIES_LYNX_POINT;
1012 warn_peculiar_desc("Lynx Point");
Nico Huber81965f32021-06-17 23:25:35 +02001013 return CHIPSET_8_SERIES_LYNX_POINT;
Nico Huber3ad9aad2021-06-17 22:05:00 +02001014 }
1015 if (content->NM == 6) {
David Hendricks66565a72021-09-20 21:56:40 -07001016 if (content->ICCRIBA <= 0x34)
1017 return CHIPSET_C620_SERIES_LEWISBURG;
1018 warn_peculiar_desc("C620 series");
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001019 return CHIPSET_C620_SERIES_LEWISBURG;
Nico Huber3ad9aad2021-06-17 22:05:00 +02001020 }
David Hendricks66565a72021-09-20 21:56:40 -07001021 if (content->ICCRIBA == 0x31)
1022 return CHIPSET_100_SERIES_SUNRISE_POINT;
1023 warn_peculiar_desc("100 series");
Nico Huber83b01c82021-06-17 21:20:09 +02001024 return CHIPSET_100_SERIES_SUNRISE_POINT;
Nico Huber1dc3d422017-06-17 00:09:31 +02001025 } else {
David Hendricks66565a72021-09-20 21:56:40 -07001026 if (content->ICCRIBA == 0x34)
1027 return CHIPSET_300_SERIES_CANNON_POINT;
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001028 if (content->CSSL == 0x11)
1029 return CHIPSET_500_SERIES_TIGER_POINT;
Nico Huber29c23dd2022-12-21 15:25:09 +00001030 if (content->CSSL == 0x14) /* backwards compatible Alder Point */
1031 return CHIPSET_500_SERIES_TIGER_POINT;
Nico Huber756b6b32022-12-21 17:15:13 +00001032 if (content->CSSL == 0x03) {
1033 if (content->CSSO == 0x58)
1034 return CHIPSET_ELKHART_LAKE;
1035 else if (content->CSSO == 0x6c) /* backwards compatible Jasper Lake */
1036 return CHIPSET_300_SERIES_CANNON_POINT;
1037 }
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001038 msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
1039 return CHIPSET_500_SERIES_TIGER_POINT;
Nico Huber1dc3d422017-06-17 00:09:31 +02001040 }
1041}
1042
1043/*
1044 * As an additional measure, we check the read frequency like `ifdtool`.
1045 * The frequency value 6 (17MHz) was reserved before Skylake and is the
1046 * only valid value since. Skylake is currently the most important dis-
1047 * tinction because of the dropped number of regions field (NR).
1048 */
Nico Huberfa622942017-03-24 17:25:37 +01001049static enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const content,
Nico Huber3ad9aad2021-06-17 22:05:00 +02001050 const struct ich_desc_component *const component,
1051 const struct ich_desc_upper_map *const upper)
Nico Huber1dc3d422017-06-17 00:09:31 +02001052{
Nico Huber3ad9aad2021-06-17 22:05:00 +02001053 const enum ich_chipset guess = guess_ich_chipset_from_content(content, upper);
Nico Huber1dc3d422017-06-17 00:09:31 +02001054
Nico Huberd2d39932019-01-18 16:49:37 +01001055 switch (guess) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001056 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001057 case CHIPSET_500_SERIES_TIGER_POINT:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001058 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001059 case CHIPSET_ELKHART_LAKE:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001060 /* `freq_read` was repurposed, so can't check on it any more. */
Nico Huber72a9dc02021-06-17 22:47:00 +02001061 break;
Nico Huberd2d39932019-01-18 16:49:37 +01001062 case CHIPSET_100_SERIES_SUNRISE_POINT:
1063 case CHIPSET_C620_SERIES_LEWISBURG:
1064 case CHIPSET_APOLLO_LAKE:
1065 if (component->modes.freq_read != 6) {
Nico Huber964007a2021-06-17 21:12:47 +02001066 msg_pwarn("\nThe flash descriptor looks like a Skylake/Sunrise Point descriptor.\n"
Nico Huberd2d39932019-01-18 16:49:37 +01001067 "However, the read frequency isn't set to 17MHz (the only valid value).\n"
1068 "Please report this message, the output of `ich_descriptors_tool` for\n"
Nico Huberac90af62022-12-18 00:22:47 +00001069 "your descriptor and the output of `lspci -nn` to flashrom-stable@flashrom.org\n\n");
Nico Huberd2d39932019-01-18 16:49:37 +01001070 }
Nico Huber72a9dc02021-06-17 22:47:00 +02001071 break;
Nico Huberd2d39932019-01-18 16:49:37 +01001072 default:
1073 if (component->modes.freq_read == 6) {
Nico Huber964007a2021-06-17 21:12:47 +02001074 msg_pwarn("\nThe flash descriptor has the read frequency set to 17MHz. However,\n"
Nico Huber1dc3d422017-06-17 00:09:31 +02001075 "it doesn't look like a Skylake/Sunrise Point compatible descriptor.\n"
1076 "Please report this message, the output of `ich_descriptors_tool` for\n"
Nico Huberac90af62022-12-18 00:22:47 +00001077 "your descriptor and the output of `lspci -nn` to flashrom-stable@flashrom.org\n\n");
David Hendricksa5216362017-08-08 20:02:22 -07001078 }
Nico Huber1dc3d422017-06-17 00:09:31 +02001079 }
Nico Huber72a9dc02021-06-17 22:47:00 +02001080 return guess;
Nico Huber1dc3d422017-06-17 00:09:31 +02001081}
1082
Stefan Taunerb3850962011-12-24 00:00:32 +00001083/* len is the length of dump in bytes */
Nico Huberfa622942017-03-24 17:25:37 +01001084int read_ich_descriptors_from_dump(const uint32_t *const dump, const size_t len,
1085 enum ich_chipset *const cs, struct ich_descriptors *const desc)
Stefan Taunerb3850962011-12-24 00:00:32 +00001086{
Nico Huber519be662018-12-23 20:03:35 +01001087 ssize_t i, max_count;
1088 size_t pch_bug_offset = 0;
Stefan Taunerb3850962011-12-24 00:00:32 +00001089
1090 if (dump == NULL || desc == NULL)
1091 return ICH_RET_PARAM;
1092
1093 if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) {
1094 if (dump[4] == DESCRIPTOR_MODE_SIGNATURE)
1095 pch_bug_offset = 4;
1096 else
1097 return ICH_RET_ERR;
1098 }
1099
1100 /* map */
Nico Huber9e14aed2017-03-28 17:08:46 +02001101 if (len < (4 + pch_bug_offset) * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +00001102 return ICH_RET_OOB;
1103 desc->content.FLVALSIG = dump[0 + pch_bug_offset];
1104 desc->content.FLMAP0 = dump[1 + pch_bug_offset];
1105 desc->content.FLMAP1 = dump[2 + pch_bug_offset];
1106 desc->content.FLMAP2 = dump[3 + pch_bug_offset];
1107
1108 /* component */
Nico Huber9e14aed2017-03-28 17:08:46 +02001109 if (len < getFCBA(&desc->content) + 3 * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +00001110 return ICH_RET_OOB;
1111 desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0];
1112 desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1];
1113 desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2];
1114
Nico Huber8a03c902021-06-17 21:23:29 +02001115 /* upper map */
1116 desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0];
1117
1118 /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide:
1119 * "Identifies the 1s based number of DWORDS contained in the VSCC
1120 * Table. Each SPI component entry in the table is 2 DWORDS long." So
1121 * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A
1122 * check ensures that the maximum offset actually accessed is available.
1123 */
1124 if (len < getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8))
1125 return ICH_RET_OOB;
1126
1127 for (i = 0; i < desc->upper.VTL/2; i++) {
1128 desc->upper.vscc_table[i].JID = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0];
1129 desc->upper.vscc_table[i].VSCC = dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1];
1130 }
1131
Nico Huber67d71792017-06-17 03:10:15 +02001132 if (*cs == CHIPSET_ICH_UNKNOWN) {
Nico Huber3ad9aad2021-06-17 22:05:00 +02001133 *cs = guess_ich_chipset(&desc->content, &desc->component, &desc->upper);
Nico Huber67d71792017-06-17 03:10:15 +02001134 prettyprint_ich_chipset(*cs);
1135 }
Nico Huberfa622942017-03-24 17:25:37 +01001136
Stefan Taunerb3850962011-12-24 00:00:32 +00001137 /* region */
Nico Huberfa622942017-03-24 17:25:37 +01001138 const ssize_t nr = ich_number_of_regions(*cs, &desc->content);
Nico Huber519be662018-12-23 20:03:35 +01001139 if (nr < 0 || len < getFRBA(&desc->content) + (size_t)nr * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +00001140 return ICH_RET_OOB;
Nico Huberfa622942017-03-24 17:25:37 +01001141 for (i = 0; i < nr; i++)
1142 desc->region.FLREGs[i] = dump[(getFRBA(&desc->content) >> 2) + i];
Stefan Taunerb3850962011-12-24 00:00:32 +00001143
1144 /* master */
Nico Huberfa622942017-03-24 17:25:37 +01001145 const ssize_t nm = ich_number_of_masters(*cs, &desc->content);
Nico Huber519be662018-12-23 20:03:35 +01001146 if (nm < 0 || len < getFMBA(&desc->content) + (size_t)nm * 4)
Stefan Taunerb3850962011-12-24 00:00:32 +00001147 return ICH_RET_OOB;
Nico Huberfa622942017-03-24 17:25:37 +01001148 for (i = 0; i < nm; i++)
1149 desc->master.FLMSTRs[i] = dump[(getFMBA(&desc->content) >> 2) + i];
Stefan Taunerb3850962011-12-24 00:00:32 +00001150
Stefan Taunerb3850962011-12-24 00:00:32 +00001151 /* MCH/PROC (aka. North) straps */
1152 if (len < getFMSBA(&desc->content) + desc->content.MSL * 4)
1153 return ICH_RET_OOB;
1154
1155 /* limit the range to be written */
Nico Huber519be662018-12-23 20:03:35 +01001156 max_count = MIN(sizeof(desc->north.STRPs) / 4, desc->content.MSL);
Stefan Taunera1a14ec2012-08-13 08:45:13 +00001157 for (i = 0; i < max_count; i++)
1158 desc->north.STRPs[i] = dump[(getFMSBA(&desc->content) >> 2) + i];
Stefan Taunerb3850962011-12-24 00:00:32 +00001159
1160 /* ICH/PCH (aka. South) straps */
1161 if (len < getFISBA(&desc->content) + desc->content.ISL * 4)
1162 return ICH_RET_OOB;
1163
1164 /* limit the range to be written */
Nico Huber519be662018-12-23 20:03:35 +01001165 max_count = MIN(sizeof(desc->south.STRPs) / 4, desc->content.ISL);
Stefan Taunera1a14ec2012-08-13 08:45:13 +00001166 for (i = 0; i < max_count; i++)
1167 desc->south.STRPs[i] = dump[(getFISBA(&desc->content) >> 2) + i];
Stefan Taunerb3850962011-12-24 00:00:32 +00001168
1169 return ICH_RET_OK;
1170}
1171
Nico Huberad186312016-05-02 15:15:29 +02001172#ifndef ICH_DESCRIPTORS_FROM_DUMP_ONLY
Stefan Taunerb3850962011-12-24 00:00:32 +00001173
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001174/** Returns the integer representation of the component density with index
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001175\em idx in bytes or -1 if the correct size can not be determined. */
1176int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001177{
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001178 if (idx > 1) {
Stefan Taunera1a14ec2012-08-13 08:45:13 +00001179 msg_perr("Only ICH SPI component index 0 or 1 are supported yet.\n");
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001180 return -1;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001181 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001182
1183 if (desc->content.NC == 0 && idx > 0)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001184 return 0;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001185
1186 uint8_t size_enc;
1187 uint8_t size_max;
1188
1189 switch (cs) {
1190 case CHIPSET_ICH8:
1191 case CHIPSET_ICH9:
1192 case CHIPSET_ICH10:
1193 case CHIPSET_5_SERIES_IBEX_PEAK:
1194 case CHIPSET_6_SERIES_COUGAR_POINT:
1195 case CHIPSET_7_SERIES_PANTHER_POINT:
Tai-Hong Wu60dead42015-01-05 23:00:14 +00001196 case CHIPSET_BAYTRAIL:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001197 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +00001198 size_enc = desc->component.dens_old.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001199 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +00001200 size_enc = desc->component.dens_old.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001201 }
1202 size_max = 5;
1203 break;
1204 case CHIPSET_8_SERIES_LYNX_POINT:
1205 case CHIPSET_8_SERIES_LYNX_POINT_LP:
1206 case CHIPSET_8_SERIES_WELLSBURG:
Duncan Laurie823096e2014-08-20 15:39:38 +00001207 case CHIPSET_9_SERIES_WILDCAT_POINT:
Nico Huber51205912017-03-17 17:59:54 +01001208 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huberd54e4f42017-03-23 23:45:47 +01001209 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -07001210 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001211 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001212 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001213 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001214 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001215 case CHIPSET_ELKHART_LAKE:
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001216 if (idx == 0) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +00001217 size_enc = desc->component.dens_new.comp1_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001218 } else {
Tai-Hong Wu60dead42015-01-05 23:00:14 +00001219 size_enc = desc->component.dens_new.comp2_density;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001220 }
1221 size_max = 7;
1222 break;
1223 case CHIPSET_ICH_UNKNOWN:
1224 default:
1225 msg_pwarn("Density encoding is unknown on this chipset.\n");
1226 return -1;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001227 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001228
1229 if (size_enc > size_max) {
Tai-Hong Wu60dead42015-01-05 23:00:14 +00001230 msg_perr("Density of ICH SPI component with index %d is invalid.\n"
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00001231 "Encoded density is 0x%x while maximum allowed is 0x%x.\n",
1232 idx, size_enc, size_max);
1233 return -1;
1234 }
1235
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001236 return (1 << (19 + size_enc));
1237}
1238
Nico Huber8d494992017-06-19 12:18:33 +02001239/* Only used by ichspi.c */
1240#if CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))
Nico Huberd54e4f42017-03-23 23:45:47 +01001241static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16_t offset, void *spibar)
Stefan Tauner1e146392011-09-15 23:52:55 +00001242{
1243 uint32_t control = 0;
1244 control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS;
1245 control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI;
Nico Huberd2d39932019-01-18 16:49:37 +01001246 switch (cs) {
1247 case CHIPSET_100_SERIES_SUNRISE_POINT:
1248 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001249 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001250 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001251 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001252 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001253 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +01001254 mmio_le_writel(control, spibar + PCH100_REG_FDOC);
1255 return mmio_le_readl(spibar + PCH100_REG_FDOD);
Nico Huberd2d39932019-01-18 16:49:37 +01001256 default:
Nico Huberd54e4f42017-03-23 23:45:47 +01001257 mmio_le_writel(control, spibar + ICH9_REG_FDOC);
1258 return mmio_le_readl(spibar + ICH9_REG_FDOD);
1259 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001260}
1261
Nico Huberd54e4f42017-03-23 23:45:47 +01001262int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc)
Stefan Tauner1e146392011-09-15 23:52:55 +00001263{
Nico Huber519be662018-12-23 20:03:35 +01001264 ssize_t i;
Stefan Tauner1e146392011-09-15 23:52:55 +00001265 struct ich_desc_region *r = &desc->region;
1266
1267 /* Test if bit-fields are working as expected.
1268 * FIXME: Replace this with dynamic bitfield fixup
1269 */
1270 for (i = 0; i < 4; i++)
1271 desc->region.FLREGs[i] = 0x5A << (i * 8);
Nico Huberfa622942017-03-24 17:25:37 +01001272 if (r->old_reg[0].base != 0x005A || r->old_reg[0].limit != 0x0000 ||
1273 r->old_reg[1].base != 0x1A00 || r->old_reg[1].limit != 0x0000 ||
1274 r->old_reg[2].base != 0x0000 || r->old_reg[2].limit != 0x005A ||
1275 r->old_reg[3].base != 0x0000 || r->old_reg[3].limit != 0x1A00) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001276 msg_pdbg("The combination of compiler and CPU architecture used"
1277 "does not lay out bit-fields as expected, sorry.\n");
Nico Huberfa622942017-03-24 17:25:37 +01001278 msg_pspew("r->old_reg[0].base = 0x%04X (0x005A)\n", r->old_reg[0].base);
1279 msg_pspew("r->old_reg[0].limit = 0x%04X (0x0000)\n", r->old_reg[0].limit);
1280 msg_pspew("r->old_reg[1].base = 0x%04X (0x1A00)\n", r->old_reg[1].base);
1281 msg_pspew("r->old_reg[1].limit = 0x%04X (0x0000)\n", r->old_reg[1].limit);
1282 msg_pspew("r->old_reg[2].base = 0x%04X (0x0000)\n", r->old_reg[2].base);
1283 msg_pspew("r->old_reg[2].limit = 0x%04X (0x005A)\n", r->old_reg[2].limit);
1284 msg_pspew("r->old_reg[3].base = 0x%04X (0x0000)\n", r->old_reg[3].base);
1285 msg_pspew("r->old_reg[3].limit = 0x%04X (0x1A00)\n", r->old_reg[3].limit);
Stefan Tauner1e146392011-09-15 23:52:55 +00001286 return ICH_RET_ERR;
1287 }
1288
Stefan Taunera1a14ec2012-08-13 08:45:13 +00001289 msg_pdbg2("Reading flash descriptors mapped by the chipset via FDOC/FDOD...");
Stefan Tauner1e146392011-09-15 23:52:55 +00001290 /* content section */
Nico Huberd54e4f42017-03-23 23:45:47 +01001291 desc->content.FLVALSIG = read_descriptor_reg(cs, 0, 0, spibar);
1292 desc->content.FLMAP0 = read_descriptor_reg(cs, 0, 1, spibar);
1293 desc->content.FLMAP1 = read_descriptor_reg(cs, 0, 2, spibar);
1294 desc->content.FLMAP2 = read_descriptor_reg(cs, 0, 3, spibar);
Stefan Tauner1e146392011-09-15 23:52:55 +00001295
1296 /* component section */
Nico Huberd54e4f42017-03-23 23:45:47 +01001297 desc->component.FLCOMP = read_descriptor_reg(cs, 1, 0, spibar);
1298 desc->component.FLILL = read_descriptor_reg(cs, 1, 1, spibar);
1299 desc->component.FLPB = read_descriptor_reg(cs, 1, 2, spibar);
Stefan Tauner1e146392011-09-15 23:52:55 +00001300
1301 /* region section */
Nico Huberfa622942017-03-24 17:25:37 +01001302 const ssize_t nr = ich_number_of_regions(cs, &desc->content);
1303 if (nr < 0) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001304 msg_pdbg2("%s: number of regions too high (%d) - failed\n",
Nico Huberfa622942017-03-24 17:25:37 +01001305 __func__, desc->content.NR + 1);
Stefan Tauner1e146392011-09-15 23:52:55 +00001306 return ICH_RET_ERR;
1307 }
Nico Huberfa622942017-03-24 17:25:37 +01001308 for (i = 0; i < nr; i++)
Nico Huberd54e4f42017-03-23 23:45:47 +01001309 desc->region.FLREGs[i] = read_descriptor_reg(cs, 2, i, spibar);
Stefan Tauner1e146392011-09-15 23:52:55 +00001310
1311 /* master section */
Nico Huberfa622942017-03-24 17:25:37 +01001312 const ssize_t nm = ich_number_of_masters(cs, &desc->content);
1313 if (nm < 0) {
1314 msg_pdbg2("%s: number of masters too high (%d) - failed\n",
1315 __func__, desc->content.NM + 1);
1316 return ICH_RET_ERR;
1317 }
1318 for (i = 0; i < nm; i++)
1319 desc->master.FLMSTRs[i] = read_descriptor_reg(cs, 3, i, spibar);
Stefan Tauner1e146392011-09-15 23:52:55 +00001320
1321 /* Accessing the strap section via FDOC/D is only possible on ICH8 and
1322 * reading the upper map is impossible on all chipsets, so don't bother.
1323 */
1324
1325 msg_pdbg2(" done.\n");
1326 return ICH_RET_OK;
1327}
Nico Huber8d494992017-06-19 12:18:33 +02001328#endif
Nico Huber305f4172013-06-14 11:55:26 +02001329
1330/**
1331 * @brief Read a layout from the dump of an Intel ICH descriptor.
1332 *
1333 * @param layout Pointer where to store the layout.
1334 * @param dump The descriptor dump to read from.
1335 * @param len The length of the descriptor dump.
1336 *
1337 * @return 0 on success,
Nico Huber70461a92019-06-15 14:56:19 +02001338 * 1 if the descriptor couldn't be parsed,
1339 * 2 when out of memory.
Nico Huber305f4172013-06-14 11:55:26 +02001340 */
Nico Huber5bd990c2019-06-16 19:46:46 +02001341int layout_from_ich_descriptors(
1342 struct flashrom_layout **const layout,
1343 const void *const dump, const size_t len)
Nico Huber305f4172013-06-14 11:55:26 +02001344{
Nico Huberfa622942017-03-24 17:25:37 +01001345 static const char *const regions[] = {
David Hendricksa5216362017-08-08 20:02:22 -07001346 "fd", "bios", "me", "gbe", "pd", "reg5", "bios2", "reg7", "ec", "reg9", "ie",
1347 "10gbe", "reg12", "reg13", "reg14", "reg15"
Nico Huberfa622942017-03-24 17:25:37 +01001348 };
Nico Huber305f4172013-06-14 11:55:26 +02001349
1350 struct ich_descriptors desc;
Nico Huberfa622942017-03-24 17:25:37 +01001351 enum ich_chipset cs = CHIPSET_ICH_UNKNOWN;
1352 if (read_ich_descriptors_from_dump(dump, len, &cs, &desc))
Nico Huber305f4172013-06-14 11:55:26 +02001353 return 1;
1354
Nico Huber671c0f02019-06-16 20:17:19 +02001355 if (flashrom_layout_new(layout))
Nico Huber5bd990c2019-06-16 19:46:46 +02001356 return 2;
Nico Huber305f4172013-06-14 11:55:26 +02001357
Nico Huber92e0b622019-06-15 15:55:11 +02001358 ssize_t i;
Nico Huber519be662018-12-23 20:03:35 +01001359 const ssize_t nr = MIN(ich_number_of_regions(cs, &desc.content), (ssize_t)ARRAY_SIZE(regions));
Nico Huber92e0b622019-06-15 15:55:11 +02001360 for (i = 0; i < nr; ++i) {
Nico Huber305f4172013-06-14 11:55:26 +02001361 const chipoff_t base = ICH_FREG_BASE(desc.region.FLREGs[i]);
Nico Huber0bb3f712017-03-29 16:44:33 +02001362 const chipoff_t limit = ICH_FREG_LIMIT(desc.region.FLREGs[i]);
Nico Huber305f4172013-06-14 11:55:26 +02001363 if (limit <= base)
1364 continue;
Nico Huber5bd990c2019-06-16 19:46:46 +02001365 if (flashrom_layout_add_region(*layout, base, limit, regions[i])) {
1366 flashrom_layout_release(*layout);
1367 *layout = NULL;
Nico Huber70461a92019-06-15 14:56:19 +02001368 return 2;
Nico Huber5bd990c2019-06-16 19:46:46 +02001369 }
Nico Huber305f4172013-06-14 11:55:26 +02001370 }
Nico Huber305f4172013-06-14 11:55:26 +02001371 return 0;
1372}
1373
Nico Huberad186312016-05-02 15:15:29 +02001374#endif /* ICH_DESCRIPTORS_FROM_DUMP_ONLY */