Add Tiger Lake U Premium support
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as unknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,
ICCRIBA is no longer present n descriptor content so a new union has
been defined for new fields and used in descriptor guessing.
freq_read field is not present on Tiger Lake, moreover in CannonPoint
and Comet Point this field is used as eSPI/EC frequency, so a new
function to print read frequency has ben added. Finally Tiger lake
boot straps include eSPI, so a new bus has been added for the new
straps.
Tested: Flash BIOS region on Intel i5-1135G7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71437
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 63d4580..ac3602b 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -44,6 +44,7 @@
return 6;
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_500_SERIES_TIGER_POINT:
return 16;
case CHIPSET_100_SERIES_SUNRISE_POINT:
return 10;
@@ -107,7 +108,7 @@
"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
"C620 series Lewisburg", "300/400 series Cannon/Comet Point",
- "Apollo Lake", "Gemini Lake",
+ "500 series Tiger Point", "Apollo Lake", "Gemini Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -200,6 +201,7 @@
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE: {
uint8_t size_enc;
@@ -220,7 +222,7 @@
static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
{
- static const char *const freq_str[3][8] = { {
+ static const char *const freq_str[4][8] = { {
"20 MHz",
"33 MHz",
"reserved",
@@ -247,7 +249,16 @@
"reserved",
"14 MHz / 17 MHz",
"reserved"
- } };
+ }, {
+ "100 MHz",
+ "50 MHz",
+ "reserved",
+ "33 MHz",
+ "25 MHz",
+ "reserved",
+ "14 MHz",
+ "reserved"
+ }};
switch (cs) {
case CHIPSET_ICH8:
@@ -273,12 +284,40 @@
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
return freq_str[2][value];
+ case CHIPSET_500_SERIES_TIGER_POINT:
+ return freq_str[3][value];
case CHIPSET_ICH_UNKNOWN:
default:
return "unknown";
}
}
+static void pprint_read_freq(enum ich_chipset cs, uint8_t value)
+{
+ static const char *const freq_str[1][8] = { {
+ "20 MHz",
+ "24 MHz",
+ "30 MHz",
+ "48 MHz",
+ "60 MHz",
+ "reserved",
+ "reserved",
+ "reserved"
+ }};
+
+ switch (cs) {
+ case CHIPSET_300_SERIES_CANNON_POINT:
+ msg_pdbg2("eSPI/EC Bus Clock Frequency: %s\n", freq_str[0][value]);
+ return;
+ case CHIPSET_500_SERIES_TIGER_POINT:
+ msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
+ return;
+ default:
+ msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, value));
+ return;
+ }
+}
+
void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc)
{
bool has_flill1;
@@ -287,6 +326,7 @@
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
has_flill1 = true;
@@ -309,7 +349,9 @@
msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1));
else
msg_pdbg2("Component 2 is not used.\n");
- msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.modes.freq_read));
+
+ pprint_read_freq(cs, desc->component.modes.freq_read);
+
msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id));
msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_write));
msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not ");
@@ -406,7 +448,8 @@
msg_pdbg2("--- Details ---\n");
if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
- cs == CHIPSET_300_SERIES_CANNON_POINT) {
+ cs == CHIPSET_300_SERIES_CANNON_POINT ||
+ cs == CHIPSET_500_SERIES_TIGER_POINT) {
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
};
@@ -965,8 +1008,10 @@
} else {
if (content->ICCRIBA == 0x34)
return CHIPSET_300_SERIES_CANNON_POINT;
- msg_pwarn("Unknown flash descriptor, assuming 300 series compatibility.\n");
- return CHIPSET_300_SERIES_CANNON_POINT;
+ if (content->CSSL == 0x11)
+ return CHIPSET_500_SERIES_TIGER_POINT;
+ msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
+ return CHIPSET_500_SERIES_TIGER_POINT;
}
}
@@ -984,6 +1029,7 @@
switch (guess) {
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_GEMINI_LAKE:
/* `freq_read` was repurposed, so can't check on it any more. */
break;
@@ -1137,6 +1183,7 @@
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
if (idx == 0) {
@@ -1173,6 +1220,7 @@
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
mmio_le_writel(control, spibar + PCH100_REG_FDOC);