Add Gemini Lake support
The SPI hardware is pretty much unchanged from Apollo Lake. However, the
IFD differs significantly enough to require special handling.
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71354
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 5f581b6..a1fed0f 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -39,6 +39,7 @@
{
switch (cs) {
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE:
return 6;
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
@@ -67,6 +68,7 @@
switch (cs) {
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE:
if (cont->NM <= MAX_NUM_MASTERS)
return cont->NM;
break;
@@ -103,7 +105,8 @@
"5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point",
"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
- "C620 series Lewisburg", "300/400 series Cannon/Comet Point", "Apollo Lake",
+ "C620 series Lewisburg", "300/400 series Cannon/Comet Point",
+ "Apollo Lake", "Gemini Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -196,7 +199,8 @@
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
- case CHIPSET_APOLLO_LAKE: {
+ case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE: {
uint8_t size_enc;
if (idx == 0) {
size_enc = desc->component.dens_new.comp1_density;
@@ -266,6 +270,7 @@
case CHIPSET_300_SERIES_CANNON_POINT:
return freq_str[1][value];
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE:
return freq_str[2][value];
case CHIPSET_ICH_UNKNOWN:
default:
@@ -282,6 +287,7 @@
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE:
has_flill1 = true;
break;
default:
@@ -457,7 +463,7 @@
desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
msg_pdbg2("\n");
}
- } else if (cs == CHIPSET_APOLLO_LAKE) {
+ } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE) {
const char *const master_names[] = { "BIOS", "TXE", };
if (nm > (ssize_t)ARRAY_SIZE(master_names)) {
msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM);
@@ -917,7 +923,9 @@
else if (content->ISL <= 16)
return CHIPSET_5_SERIES_IBEX_PEAK;
else if (content->FLMAP2 == 0) {
- if (content->ISL != 19)
+ if (content->ISL == 23)
+ return CHIPSET_GEMINI_LAKE;
+ else if (content->ISL != 19)
msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n");
return CHIPSET_APOLLO_LAKE;
}
@@ -961,6 +969,7 @@
switch (guess) {
case CHIPSET_300_SERIES_CANNON_POINT:
+ case CHIPSET_GEMINI_LAKE:
/* `freq_read` was repurposed, so can't check on it any more. */
return guess;
case CHIPSET_100_SERIES_SUNRISE_POINT:
@@ -1116,6 +1125,7 @@
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE:
if (idx == 0) {
size_enc = desc->component.dens_new.comp1_density;
} else {
@@ -1151,6 +1161,7 @@
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_GEMINI_LAKE:
mmio_le_writel(control, spibar + PCH100_REG_FDOC);
return mmio_le_readl(spibar + PCH100_REG_FDOD);
default: