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Ronald G. Minnichb1934902002-06-11 19:15:55 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnichb1934902002-06-11 19:15:55 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnichb1934902002-06-11 19:15:55 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnichb1934902002-06-11 19:15:55 +000019 */
20
21#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include "chipdrivers.h"
Ronald G. Minnichb1934902002-06-11 19:15:55 +000023
Michael Karcher1c296ca2009-11-27 17:49:42 +000024/* WARNING!
25 This chip uses the standard JEDEC Addresses in 16-bit mode as word
26 addresses. In byte mode, 0xAAA has to be used instead of 0x555 and
27 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC
28 functions. */
29
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000030void write_page_m29f400bt(chipaddr bios, uint8_t *src,
31 chipaddr dst, int page_size)
Uwe Hermann51582f22007-08-23 10:20:40 +000032{
33 int i;
34
35 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000036 chip_writeb(0xAA, bios + 0xAAA);
37 chip_writeb(0x55, bios + 0x555);
38 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000039
40 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000041 chip_writeb(*src, dst);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000042 //chip_writeb(0xF0, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000043 //programmer_delay(5);
Uwe Hermannfd374142007-08-23 15:20:38 +000044 toggle_ready_jedec(dst);
Sean Nelsoned479d22010-03-24 23:14:32 +000045 msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000046 (dst - bios), chip_readb(dst), *src);
Uwe Hermann51582f22007-08-23 10:20:40 +000047 dst++;
48 src++;
49 }
50}
51
Ollie Lho761bf1b2004-03-20 16:46:10 +000052int probe_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000053{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000054 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000055 uint8_t id1, id2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000056
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000057 chip_writeb(0xAA, bios + 0xAAA);
58 chip_writeb(0x55, bios + 0x555);
59 chip_writeb(0x90, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000060
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000061 programmer_delay(10);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000062
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000063 id1 = chip_readb(bios);
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +000064 /* The data sheet says id2 is at (bios + 0x01) and id2 listed in
65 * flash.h does not match. It should be possible to use JEDEC probe.
66 */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000067 id2 = chip_readb(bios + 0x02);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000068
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000069 chip_writeb(0xAA, bios + 0xAAA);
70 chip_writeb(0x55, bios + 0x555);
71 chip_writeb(0xF0, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000072
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000073 programmer_delay(10);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000074
Sean Nelsoned479d22010-03-24 23:14:32 +000075 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000076
Ronald G. Minnichb1934902002-06-11 19:15:55 +000077 if (id1 == flash->manufacture_id && id2 == flash->model_id)
78 return 1;
79
80 return 0;
81}
82
Ollie Lho761bf1b2004-03-20 16:46:10 +000083int erase_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000084{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000085 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000086
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000087 chip_writeb(0xAA, bios + 0xAAA);
88 chip_writeb(0x55, bios + 0x555);
89 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000090
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000091 chip_writeb(0xAA, bios + 0xAAA);
92 chip_writeb(0x55, bios + 0x555);
93 chip_writeb(0x10, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000094
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000095 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +000096 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000097
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000098 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +000099 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000100 return -1;
101 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000102 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000103}
104
Sean Nelson6b11ad22009-12-23 17:05:59 +0000105int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000106{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000107 chipaddr bios = flash->virtual_memory;
108 chipaddr dst = bios + start;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000109
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000110 chip_writeb(0xAA, bios + 0xAAA);
111 chip_writeb(0x55, bios + 0x555);
112 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000113
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000114 chip_writeb(0xAA, bios + 0xAAA);
115 chip_writeb(0x55, bios + 0x555);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000116 //chip_writeb(0x10, bios + 0xAAA);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000117 chip_writeb(0x30, dst);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000118
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000119 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000120 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000121
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000122 if (check_erased_range(flash, start, len)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000123 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000124 return -1;
125 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000126 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000127}
128
Sean Nelson6b11ad22009-12-23 17:05:59 +0000129int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen)
130{
131 if ((address != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000132 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson6b11ad22009-12-23 17:05:59 +0000133 __func__);
134 return -1;
135 }
136 return erase_m29f400bt(flash);
137}
138
Ollie Lho184a4042005-11-26 21:55:36 +0000139int write_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000140{
141 int i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000142 int total_size = flash->total_size * 1024;
143 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000144 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000145
146 //erase_m29f400bt (flash);
Sean Nelsoned479d22010-03-24 23:14:32 +0000147 msg_cinfo("Programming page:\n ");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000148 /*********************************
149 *Pages for M29F400BT:
150 * 16 0x7c000 0x7ffff TOP
151 * 8 0x7a000 0x7bfff
152 * 8 0x78000 0x79fff
153 * 32 0x70000 0x77fff
154 * 64 0x60000 0x6ffff
155 * 64 0x50000 0x5ffff
156 * 64 0x40000 0x4ffff
157 *---------------------------------
158 * 64 0x30000 0x3ffff
159 * 64 0x20000 0x2ffff
160 * 64 0x10000 0x1ffff
161 * 64 0x00000 0x0ffff BOTTOM
162 *********************************/
Sean Nelsoned479d22010-03-24 23:14:32 +0000163 msg_cinfo("total_size/page_size = %d\n", total_size / page_size);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000164 for (i = 0; i < (total_size / page_size) - 1; i++) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000165 msg_cinfo("%04d at address: 0x%08x\n", i, i * page_size);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000166 if (block_erase_m29f400bt(flash, i * page_size, page_size)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000167 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000168 return -1;
169 }
Ollie Lho761bf1b2004-03-20 16:46:10 +0000170 write_page_m29f400bt(bios, buf + i * page_size,
171 bios + i * page_size, page_size);
Sean Nelsoned479d22010-03-24 23:14:32 +0000172 msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000173 }
174
Sean Nelsoned479d22010-03-24 23:14:32 +0000175 msg_cinfo("%04d at address: 0x%08x\n", 7, 0x70000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000176 if (block_erase_m29f400bt(flash, 0x70000, 32 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000177 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000178 return -1;
179 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000180 write_page_m29f400bt(bios, buf + 0x70000, bios + 0x70000, 32 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000181
Sean Nelsoned479d22010-03-24 23:14:32 +0000182 msg_cinfo("%04d at address: 0x%08x\n", 8, 0x78000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000183 if (block_erase_m29f400bt(flash, 0x78000, 8 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000184 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000185 return -1;
186 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000187 write_page_m29f400bt(bios, buf + 0x78000, bios + 0x78000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000188
Sean Nelsoned479d22010-03-24 23:14:32 +0000189 msg_cinfo("%04d at address: 0x%08x\n", 9, 0x7a000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000190 if (block_erase_m29f400bt(flash, 0x7a000, 8 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000191 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000192 return -1;
193 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000194 write_page_m29f400bt(bios, buf + 0x7a000, bios + 0x7a000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000195
Sean Nelsoned479d22010-03-24 23:14:32 +0000196 msg_cinfo("%04d at address: 0x%08x\n", 10, 0x7c000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000197 if (block_erase_m29f400bt(flash, 0x7c000, 16 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000198 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000199 return -1;
200 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000201 write_page_m29f400bt(bios, buf + 0x7c000, bios + 0x7c000, 16 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000202
Sean Nelsoned479d22010-03-24 23:14:32 +0000203 msg_cinfo("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000204
Uwe Hermannffec5f32007-08-23 16:08:21 +0000205 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000206}
207
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +0000208int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000209{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000210 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000211
Sean Nelsoned479d22010-03-24 23:14:32 +0000212 msg_cinfo("Programming page:\n ");
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000213 /*********************************
214 *Pages for M29F400BT:
215 * 16 0x7c000 0x7ffff TOP
216 * 8 0x7a000 0x7bfff
217 * 8 0x78000 0x79fff
218 * 32 0x70000 0x77fff
219 * 64 0x60000 0x6ffff
220 * 64 0x50000 0x5ffff
221 * 64 0x40000 0x4ffff
222 *---------------------------------
223 * 64 0x30000 0x3ffff
224 * 64 0x20000 0x2ffff
225 * 64 0x10000 0x1ffff
226 * 64 0x00000 0x0ffff BOTTOM
227 *********************************/
Sean Nelsoned479d22010-03-24 23:14:32 +0000228 msg_cinfo("%04d at address: 0x%08x\n", 7, 0x00000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000229 if (block_erase_m29f400bt(flash, 0x00000, 64 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000230 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000231 return -1;
232 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000233 write_page_m29f400bt(bios, buf + 0x00000, bios + 0x00000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000234
Sean Nelsoned479d22010-03-24 23:14:32 +0000235 msg_cinfo("%04d at address: 0x%08x\n", 7, 0x10000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000236 if (block_erase_m29f400bt(flash, 0x10000, 64 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000237 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000238 return -1;
239 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000240 write_page_m29f400bt(bios, buf + 0x10000, bios + 0x10000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000241
Sean Nelsoned479d22010-03-24 23:14:32 +0000242 msg_cinfo("%04d at address: 0x%08x\n", 7, 0x20000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000243 if (block_erase_m29f400bt(flash, 0x20000, 64 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000244 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000245 return -1;
246 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000247 write_page_m29f400bt(bios, buf + 0x20000, bios + 0x20000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000248
Sean Nelsoned479d22010-03-24 23:14:32 +0000249 msg_cinfo("%04d at address: 0x%08x\n", 7, 0x30000);
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000250 if (block_erase_m29f400bt(flash, 0x30000, 64 * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000251 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000252 return -1;
253 }
Uwe Hermanna7e05482007-05-09 10:17:44 +0000254 write_page_m29f400bt(bios, buf + 0x30000, bios + 0x30000, 64 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000255
Sean Nelsoned479d22010-03-24 23:14:32 +0000256 msg_cinfo("\n");
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000257
Uwe Hermannffec5f32007-08-23 16:08:21 +0000258 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000259}