Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * It handles everything related to status registers of the JEDEC family 25. |
| 4 | * |
| 5 | * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger |
| 6 | * Copyright (C) 2008 coresystems GmbH |
| 7 | * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl> |
| 8 | * Copyright (C) 2012 Stefan Tauner |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include "flash.h" |
| 21 | #include "chipdrivers.h" |
| 22 | #include "spi.h" |
| 23 | |
| 24 | /* === Generic functions === */ |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 25 | static int spi_write_register_flag(const struct flashctx *flash, uint8_t enable_opcode, uint8_t *write_cmd, size_t write_cmd_len, enum flash_reg reg) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 26 | { |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 27 | /* |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 28 | * Enabling register writes requires either EWSR or WREN depending on |
| 29 | * chip type. The code below relies on the fact hat EWSR and WREN have |
| 30 | * the same INSIZE and OUTSIZE. |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 31 | */ |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 32 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 33 | struct spi_command cmds[] = { |
| 34 | { |
| 35 | .writecnt = JEDEC_WREN_OUTSIZE, |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 36 | .writearr = &enable_opcode, |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 37 | .readcnt = 0, |
| 38 | .readarr = NULL, |
| 39 | }, { |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 40 | .writecnt = write_cmd_len, |
| 41 | .writearr = write_cmd, |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 42 | .readcnt = 0, |
| 43 | .readarr = NULL, |
| 44 | }, { |
| 45 | .writecnt = 0, |
| 46 | .writearr = NULL, |
| 47 | .readcnt = 0, |
| 48 | .readarr = NULL, |
| 49 | }}; |
| 50 | |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 51 | int result = spi_send_multicommand(flash, cmds); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 52 | if (result) { |
| 53 | msg_cerr("%s failed during command execution\n", __func__); |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 54 | /* |
| 55 | * No point in waiting for the command to complete if execution |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 56 | * failed. |
| 57 | */ |
| 58 | return result; |
| 59 | } |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 60 | |
| 61 | /* |
| 62 | * WRSR performs a self-timed erase before the changes take effect. |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 63 | * This may take 50-85 ms in most cases, and some chips apparently |
| 64 | * allow running RDSR only once. Therefore pick an initial delay of |
| 65 | * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 66 | * |
| 67 | * Newer chips with multiple status registers (SR2 etc.) are unlikely |
| 68 | * to have problems with multiple RDSR commands, so only wait for the |
| 69 | * initial 100 ms if the register we wrote to was SR1. |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 70 | */ |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 71 | int delay_ms = 5000; |
| 72 | if (reg == STATUS1) { |
| 73 | programmer_delay(100 * 1000); |
| 74 | delay_ms -= 100; |
| 75 | } |
| 76 | |
| 77 | for (; delay_ms > 0; delay_ms -= 10) { |
| 78 | if ((spi_read_status_register(flash) & SPI_SR_WIP) == 0) |
| 79 | return 0; |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 80 | programmer_delay(10 * 1000); |
| 81 | } |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 82 | |
| 83 | msg_cerr("Error: WIP bit after WRSR never cleared\n"); |
| 84 | return TIMEOUT_ERROR; |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 85 | } |
| 86 | |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 87 | int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t value) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 88 | { |
| 89 | int feature_bits = flash->chip->feature_bits; |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 90 | |
| 91 | uint8_t write_cmd[3]; |
| 92 | size_t write_cmd_len = 0; |
| 93 | |
| 94 | /* |
| 95 | * Create SPI write command sequence based on the destination register |
| 96 | * and the chip's supported command set. |
| 97 | */ |
| 98 | switch (reg) { |
| 99 | case STATUS1: |
| 100 | write_cmd[0] = JEDEC_WRSR; |
| 101 | write_cmd[1] = value; |
| 102 | write_cmd_len = JEDEC_WRSR_OUTSIZE; |
| 103 | break; |
| 104 | default: |
| 105 | msg_cerr("Cannot write register: unknown register\n"); |
| 106 | return 1; |
| 107 | } |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 108 | |
| 109 | if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) { |
| 110 | msg_cdbg("Missing status register write definition, assuming " |
| 111 | "EWSR is needed\n"); |
| 112 | feature_bits |= FEATURE_WRSR_EWSR; |
| 113 | } |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 114 | |
| 115 | int ret = 1; |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 116 | if (feature_bits & FEATURE_WRSR_WREN) |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 117 | ret = spi_write_register_flag(flash, JEDEC_WREN, write_cmd, write_cmd_len, reg); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 118 | if (ret && (feature_bits & FEATURE_WRSR_EWSR)) |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 119 | ret = spi_write_register_flag(flash, JEDEC_EWSR, write_cmd, write_cmd_len, reg); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 120 | return ret; |
| 121 | } |
| 122 | |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 123 | int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t *value) |
| 124 | { |
| 125 | uint8_t read_cmd; |
| 126 | |
| 127 | switch (reg) { |
| 128 | case STATUS1: |
| 129 | read_cmd = JEDEC_RDSR; |
| 130 | break; |
| 131 | default: |
| 132 | msg_cerr("Cannot read register: unknown register\n"); |
| 133 | return 1; |
| 134 | } |
| 135 | |
| 136 | /* FIXME: No workarounds for driver/hardware bugs in generic code. */ |
| 137 | /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ |
| 138 | uint8_t readarr[2]; |
| 139 | |
| 140 | int ret = spi_send_command(flash, sizeof(read_cmd), sizeof(readarr), &read_cmd, readarr); |
| 141 | if (ret) { |
| 142 | msg_cerr("Register read failed!\n"); |
| 143 | return ret; |
| 144 | } |
| 145 | |
| 146 | *value = readarr[0]; |
| 147 | return 0; |
| 148 | } |
| 149 | |
Edward O'Callaghan | 5eca427 | 2020-04-12 17:27:53 +1000 | [diff] [blame] | 150 | uint8_t spi_read_status_register(const struct flashctx *flash) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 151 | { |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 152 | uint8_t status = 0; |
| 153 | /* FIXME: We should propagate the error. */ |
| 154 | spi_read_register(flash, STATUS1, &status); |
| 155 | return status; |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Nikolai Artemiev | 721a4f3 | 2020-12-14 07:39:02 +1100 | [diff] [blame] | 158 | static int spi_restore_status(struct flashctx *flash, uint8_t status) |
| 159 | { |
| 160 | msg_cdbg("restoring chip status (0x%02x)\n", status); |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 161 | return spi_write_register(flash, STATUS1, status); |
Nikolai Artemiev | 721a4f3 | 2020-12-14 07:39:02 +1100 | [diff] [blame] | 162 | } |
| 163 | |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 164 | /* A generic block protection disable. |
| 165 | * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise. |
| 166 | * Tests if the register bits are locked with the lock_mask (lock_mask). |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 167 | * Tests if a hardware protection is active (i.e. low pin/high bit value) with the write protection mask |
| 168 | * (wp_mask) and bails out in that case. |
| 169 | * If there are register lock bits set we try to disable them by unsetting those bits of the previous register |
| 170 | * contents that are set in the lock_mask. We then check if removing the lock bits has worked and continue as if |
| 171 | * they never had been engaged: |
| 172 | * If the lock bits are out of the way try to disable engaged protections. |
| 173 | * To support uncommon global unprotects (e.g. on most AT2[56]xx1(A)) unprotect_mask can be used to force |
| 174 | * bits to 0 additionally to those set in bp_mask and lock_mask. Only bits set in unprotect_mask are potentially |
| 175 | * preserved when doing the final unprotect. |
| 176 | * |
| 177 | * To sum up: |
| 178 | * bp_mask: set those bits that correspond to the bits in the status register that indicate an active protection |
| 179 | * (which should be unset after this function returns). |
| 180 | * lock_mask: set the bits that correspond to the bits that lock changing the bits above. |
| 181 | * wp_mask: set the bits that correspond to bits indicating non-software revocable protections. |
| 182 | * unprotect_mask: set the bits that should be preserved if possible when unprotecting. |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 183 | */ |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 184 | static int spi_disable_blockprotect_generic(struct flashctx *flash, uint8_t bp_mask, uint8_t lock_mask, uint8_t wp_mask, uint8_t unprotect_mask) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 185 | { |
| 186 | uint8_t status; |
| 187 | int result; |
| 188 | |
| 189 | status = spi_read_status_register(flash); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 190 | if ((status & bp_mask) == 0) { |
| 191 | msg_cdbg2("Block protection is disabled.\n"); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 192 | return 0; |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 193 | } |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 194 | |
Nikolai Artemiev | 721a4f3 | 2020-12-14 07:39:02 +1100 | [diff] [blame] | 195 | /* Restore status register content upon exit in finalize_flash_access(). */ |
| 196 | register_chip_restore(spi_restore_status, flash, status); |
| 197 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 198 | msg_cdbg("Some block protection in effect, disabling... "); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 199 | if ((status & lock_mask) != 0) { |
| 200 | msg_cdbg("\n\tNeed to disable the register lock first... "); |
| 201 | if (wp_mask != 0 && (status & wp_mask) == 0) { |
| 202 | msg_cerr("Hardware protection is active, disabling write protection is impossible.\n"); |
| 203 | return 1; |
| 204 | } |
| 205 | /* All bits except the register lock bit (often called SPRL, SRWD, WPEN) are readonly. */ |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 206 | result = spi_write_register(flash, STATUS1, status & ~lock_mask); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 207 | if (result) { |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 208 | msg_cerr("Could not write status register 1.\n"); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 209 | return result; |
| 210 | } |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 211 | status = spi_read_status_register(flash); |
| 212 | if ((status & lock_mask) != 0) { |
| 213 | msg_cerr("Unsetting lock bit(s) failed.\n"); |
| 214 | return 1; |
| 215 | } |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 216 | msg_cdbg("done.\n"); |
| 217 | } |
| 218 | /* Global unprotect. Make sure to mask the register lock bit as well. */ |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 219 | result = spi_write_register(flash, STATUS1, status & ~(bp_mask | lock_mask) & unprotect_mask); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 220 | if (result) { |
Nikolai Artemiev | 0167522 | 2021-10-20 22:30:41 +1100 | [diff] [blame^] | 221 | msg_cerr("Could not write status register 1.\n"); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 222 | return result; |
| 223 | } |
| 224 | status = spi_read_status_register(flash); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 225 | if ((status & bp_mask) != 0) { |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 226 | msg_cerr("Block protection could not be disabled!\n"); |
Yuji Sasaki | 4af3609 | 2019-03-22 10:59:50 -0700 | [diff] [blame] | 227 | if (flash->chip->printlock) |
| 228 | flash->chip->printlock(flash); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 229 | return 1; |
| 230 | } |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 231 | msg_cdbg("disabled.\n"); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 232 | return 0; |
| 233 | } |
| 234 | |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 235 | /* A common block protection disable that tries to unset the status register bits masked by 0x3C. */ |
| 236 | int spi_disable_blockprotect(struct flashctx *flash) |
| 237 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 238 | return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 239 | } |
| 240 | |
Wei Hu | 25584de | 2018-04-30 14:02:08 -0700 | [diff] [blame] | 241 | int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash) |
| 242 | { |
| 243 | int result = spi_write_enable(flash); |
| 244 | if (result) |
| 245 | return result; |
| 246 | |
| 247 | static const unsigned char cmd[] = { 0x98 }; /* ULBPR */ |
| 248 | result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); |
| 249 | if (result) |
| 250 | msg_cerr("ULBPR failed\n"); |
| 251 | return result; |
| 252 | } |
| 253 | |
Stefan Tauner | a60d408 | 2014-06-04 16:17:03 +0000 | [diff] [blame] | 254 | /* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and |
| 255 | * protected/locked by bit #7. Useful when bits 4-5 may be non-0). */ |
| 256 | int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash) |
| 257 | { |
| 258 | return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF); |
| 259 | } |
| 260 | |
Stefan Tauner | 278ba6e | 2013-06-28 21:28:27 +0000 | [diff] [blame] | 261 | /* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and |
| 262 | * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly |
| 263 | * non-0). */ |
| 264 | int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash) |
| 265 | { |
| 266 | return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF); |
| 267 | } |
| 268 | |
| 269 | /* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and |
| 270 | * protected/locked by bit #7. */ |
| 271 | int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash) |
| 272 | { |
| 273 | return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0, 0xFF); |
| 274 | } |
| 275 | |
| 276 | /* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and |
| 277 | * protected/locked by bit #7. */ |
| 278 | int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash) |
| 279 | { |
| 280 | return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); |
| 281 | } |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 282 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 283 | static void spi_prettyprint_status_register_hex(uint8_t status) |
| 284 | { |
| 285 | msg_cdbg("Chip status register is 0x%02x.\n", status); |
| 286 | } |
| 287 | |
Stefan Tauner | b6b00e9 | 2013-06-28 21:28:43 +0000 | [diff] [blame] | 288 | /* Common highest bit: Status Register Write Disable (SRWD) or Status Register Protect (SRP). */ |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 289 | static void spi_prettyprint_status_register_srwd(uint8_t status) |
| 290 | { |
Stefan Tauner | b6b00e9 | 2013-06-28 21:28:43 +0000 | [diff] [blame] | 291 | msg_cdbg("Chip status register: Status Register Write Disable (SRWD, SRP, ...) is %sset\n", |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 292 | (status & (1 << 7)) ? "" : "not "); |
| 293 | } |
| 294 | |
| 295 | /* Common highest bit: Block Protect Write Disable (BPL). */ |
| 296 | static void spi_prettyprint_status_register_bpl(uint8_t status) |
| 297 | { |
| 298 | msg_cdbg("Chip status register: Block Protect Write Disable (BPL) is %sset\n", |
| 299 | (status & (1 << 7)) ? "" : "not "); |
| 300 | } |
| 301 | |
| 302 | /* Common lowest 2 bits: WEL and WIP. */ |
| 303 | static void spi_prettyprint_status_register_welwip(uint8_t status) |
| 304 | { |
| 305 | msg_cdbg("Chip status register: Write Enable Latch (WEL) is %sset\n", |
| 306 | (status & (1 << 1)) ? "" : "not "); |
| 307 | msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is %sset\n", |
| 308 | (status & (1 << 0)) ? "" : "not "); |
| 309 | } |
| 310 | |
| 311 | /* Common block protection (BP) bits. */ |
| 312 | static void spi_prettyprint_status_register_bp(uint8_t status, int bp) |
| 313 | { |
| 314 | switch (bp) { |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 315 | case 4: |
| 316 | msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n", |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 317 | (status & (1 << 6)) ? "" : "not "); |
Richard Hughes | db7482b | 2018-12-19 12:04:30 +0000 | [diff] [blame] | 318 | /* Fall through. */ |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 319 | case 3: |
| 320 | msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n", |
| 321 | (status & (1 << 5)) ? "" : "not "); |
Richard Hughes | db7482b | 2018-12-19 12:04:30 +0000 | [diff] [blame] | 322 | /* Fall through. */ |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 323 | case 2: |
| 324 | msg_cdbg("Chip status register: Block Protect 2 (BP2) is %sset\n", |
| 325 | (status & (1 << 4)) ? "" : "not "); |
Richard Hughes | db7482b | 2018-12-19 12:04:30 +0000 | [diff] [blame] | 326 | /* Fall through. */ |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 327 | case 1: |
| 328 | msg_cdbg("Chip status register: Block Protect 1 (BP1) is %sset\n", |
| 329 | (status & (1 << 3)) ? "" : "not "); |
Richard Hughes | db7482b | 2018-12-19 12:04:30 +0000 | [diff] [blame] | 330 | /* Fall through. */ |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 331 | case 0: |
| 332 | msg_cdbg("Chip status register: Block Protect 0 (BP0) is %sset\n", |
| 333 | (status & (1 << 2)) ? "" : "not "); |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | /* Unnamed bits. */ |
Aidan Thornton | db4e87d | 2013-08-27 18:01:53 +0000 | [diff] [blame] | 338 | void spi_prettyprint_status_register_bit(uint8_t status, int bit) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 339 | { |
| 340 | msg_cdbg("Chip status register: Bit %i is %sset\n", bit, (status & (1 << bit)) ? "" : "not "); |
| 341 | } |
| 342 | |
| 343 | int spi_prettyprint_status_register_plain(struct flashctx *flash) |
| 344 | { |
| 345 | uint8_t status = spi_read_status_register(flash); |
| 346 | spi_prettyprint_status_register_hex(status); |
| 347 | return 0; |
| 348 | } |
| 349 | |
Stefan Tauner | 278ba6e | 2013-06-28 21:28:27 +0000 | [diff] [blame] | 350 | /* Print the plain hex value and the welwip bits only. */ |
| 351 | int spi_prettyprint_status_register_default_welwip(struct flashctx *flash) |
| 352 | { |
| 353 | uint8_t status = spi_read_status_register(flash); |
| 354 | spi_prettyprint_status_register_hex(status); |
| 355 | |
| 356 | spi_prettyprint_status_register_welwip(status); |
| 357 | return 0; |
| 358 | } |
| 359 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 360 | /* Works for many chips of the |
| 361 | * AMIC A25L series |
| 362 | * and MX MX25L512 |
| 363 | */ |
Stefan Tauner | 12f3d51 | 2014-05-27 21:27:27 +0000 | [diff] [blame] | 364 | int spi_prettyprint_status_register_bp1_srwd(struct flashctx *flash) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 365 | { |
| 366 | uint8_t status = spi_read_status_register(flash); |
| 367 | spi_prettyprint_status_register_hex(status); |
| 368 | |
| 369 | spi_prettyprint_status_register_srwd(status); |
| 370 | spi_prettyprint_status_register_bit(status, 6); |
| 371 | spi_prettyprint_status_register_bit(status, 5); |
| 372 | spi_prettyprint_status_register_bit(status, 4); |
| 373 | spi_prettyprint_status_register_bp(status, 1); |
| 374 | spi_prettyprint_status_register_welwip(status); |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | /* Works for many chips of the |
| 379 | * AMIC A25L series |
Stefan Tauner | f445161 | 2013-04-19 01:59:15 +0000 | [diff] [blame] | 380 | * PMC Pm25LD series |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 381 | */ |
Stefan Tauner | 12f3d51 | 2014-05-27 21:27:27 +0000 | [diff] [blame] | 382 | int spi_prettyprint_status_register_bp2_srwd(struct flashctx *flash) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 383 | { |
| 384 | uint8_t status = spi_read_status_register(flash); |
| 385 | spi_prettyprint_status_register_hex(status); |
| 386 | |
| 387 | spi_prettyprint_status_register_srwd(status); |
| 388 | spi_prettyprint_status_register_bit(status, 6); |
| 389 | spi_prettyprint_status_register_bit(status, 5); |
| 390 | spi_prettyprint_status_register_bp(status, 2); |
| 391 | spi_prettyprint_status_register_welwip(status); |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | /* Works for many chips of the |
| 396 | * ST M25P series |
| 397 | * MX MX25L series |
| 398 | */ |
Stefan Tauner | 12f3d51 | 2014-05-27 21:27:27 +0000 | [diff] [blame] | 399 | int spi_prettyprint_status_register_bp3_srwd(struct flashctx *flash) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 400 | { |
| 401 | uint8_t status = spi_read_status_register(flash); |
| 402 | spi_prettyprint_status_register_hex(status); |
| 403 | |
| 404 | spi_prettyprint_status_register_srwd(status); |
| 405 | spi_prettyprint_status_register_bit(status, 6); |
| 406 | spi_prettyprint_status_register_bp(status, 3); |
| 407 | spi_prettyprint_status_register_welwip(status); |
| 408 | return 0; |
| 409 | } |
| 410 | |
Stefan Tauner | 12f3d51 | 2014-05-27 21:27:27 +0000 | [diff] [blame] | 411 | int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash) |
Stefan Tauner | 278ba6e | 2013-06-28 21:28:27 +0000 | [diff] [blame] | 412 | { |
| 413 | uint8_t status = spi_read_status_register(flash); |
| 414 | spi_prettyprint_status_register_hex(status); |
| 415 | |
| 416 | spi_prettyprint_status_register_srwd(status); |
| 417 | spi_prettyprint_status_register_bp(status, 4); |
| 418 | spi_prettyprint_status_register_welwip(status); |
| 419 | return 0; |
| 420 | } |
| 421 | |
Stefan Tauner | 85f09f7 | 2014-05-27 21:27:14 +0000 | [diff] [blame] | 422 | int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash) |
| 423 | { |
| 424 | uint8_t status = spi_read_status_register(flash); |
| 425 | spi_prettyprint_status_register_hex(status); |
| 426 | |
| 427 | spi_prettyprint_status_register_bpl(status); |
| 428 | spi_prettyprint_status_register_bit(status, 6); |
| 429 | spi_prettyprint_status_register_bit(status, 5); |
| 430 | spi_prettyprint_status_register_bp(status, 2); |
| 431 | spi_prettyprint_status_register_welwip(status); |
| 432 | return 0; |
| 433 | } |
| 434 | |
Ben Gardner | bcf6109 | 2015-11-22 02:23:31 +0000 | [diff] [blame] | 435 | int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash) |
| 436 | { |
| 437 | uint8_t status = spi_read_status_register(flash); |
| 438 | spi_prettyprint_status_register_hex(status); |
| 439 | |
| 440 | spi_prettyprint_status_register_bpl(status); |
| 441 | spi_prettyprint_status_register_bit(status, 6); |
| 442 | msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top"); |
| 443 | spi_prettyprint_status_register_bp(status, 2); |
| 444 | spi_prettyprint_status_register_welwip(status); |
| 445 | return 0; |
| 446 | } |
| 447 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 448 | /* === Amic === |
| 449 | * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using |
Stefan Tauner | 12f3d51 | 2014-05-27 21:27:27 +0000 | [diff] [blame] | 450 | * spi_prettyprint_status_register_bp1_srwd or |
| 451 | * spi_prettyprint_status_register_bp2_srwd. |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 452 | * FIXME: spi_disable_blockprotect is incorrect and will fail for chips using |
| 453 | * spi_prettyprint_status_register_amic_a25l032 if those have locks controlled |
| 454 | * by the second status register. |
| 455 | */ |
| 456 | |
| 457 | int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash) |
| 458 | { |
| 459 | uint8_t status = spi_read_status_register(flash); |
| 460 | spi_prettyprint_status_register_hex(status); |
| 461 | |
| 462 | spi_prettyprint_status_register_srwd(status); |
| 463 | msg_cdbg("Chip status register: Sector Protect Size (SEC) is %i KB\n", (status & (1 << 6)) ? 4 : 64); |
| 464 | msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top"); |
| 465 | spi_prettyprint_status_register_bp(status, 2); |
| 466 | spi_prettyprint_status_register_welwip(status); |
| 467 | msg_cdbg("Chip status register 2 is NOT decoded!\n"); |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | /* === Atmel === */ |
| 472 | |
| 473 | static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status) |
| 474 | { |
| 475 | msg_cdbg("Chip status register: Write Protect Enable (WPEN) is %sset\n", |
| 476 | (status & (1 << 7)) ? "" : "not "); |
| 477 | } |
| 478 | |
| 479 | static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) |
| 480 | { |
| 481 | msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) is %sset\n", |
| 482 | (status & (1 << 7)) ? "" : "not "); |
| 483 | } |
| 484 | |
| 485 | static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status) |
| 486 | { |
| 487 | msg_cdbg("Chip status register: Erase/Program Error (EPE) is %sset\n", |
| 488 | (status & (1 << 5)) ? "" : "not "); |
| 489 | msg_cdbg("Chip status register: WP# pin (WPP) is %sasserted\n", |
| 490 | (status & (1 << 4)) ? "not " : ""); |
| 491 | } |
| 492 | |
| 493 | static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status) |
| 494 | { |
| 495 | msg_cdbg("Chip status register: Software Protection Status (SWP): "); |
| 496 | switch (status & (3 << 2)) { |
| 497 | case 0x0 << 2: |
| 498 | msg_cdbg("no sectors are protected\n"); |
| 499 | break; |
| 500 | case 0x1 << 2: |
| 501 | msg_cdbg("some sectors are protected\n"); |
| 502 | /* FIXME: Read individual Sector Protection Registers. */ |
| 503 | break; |
| 504 | case 0x3 << 2: |
| 505 | msg_cdbg("all sectors are protected\n"); |
| 506 | break; |
| 507 | default: |
| 508 | msg_cdbg("reserved for future use\n"); |
| 509 | break; |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | int spi_prettyprint_status_register_at25df(struct flashctx *flash) |
| 514 | { |
| 515 | uint8_t status = spi_read_status_register(flash); |
| 516 | spi_prettyprint_status_register_hex(status); |
| 517 | |
| 518 | spi_prettyprint_status_register_atmel_at25_srpl(status); |
| 519 | spi_prettyprint_status_register_bit(status, 6); |
| 520 | spi_prettyprint_status_register_atmel_at25_epewpp(status); |
| 521 | spi_prettyprint_status_register_atmel_at25_swp(status); |
| 522 | spi_prettyprint_status_register_welwip(status); |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash) |
| 527 | { |
| 528 | /* FIXME: We should check the security lockdown. */ |
| 529 | msg_cdbg("Ignoring security lockdown (if present)\n"); |
| 530 | msg_cdbg("Ignoring status register byte 2\n"); |
| 531 | return spi_prettyprint_status_register_at25df(flash); |
| 532 | } |
| 533 | |
Stefan Tauner | 57794ac | 2012-12-29 15:04:20 +0000 | [diff] [blame] | 534 | /* used for AT25F512, AT25F1024(A), AT25F2048 */ |
| 535 | int spi_prettyprint_status_register_at25f(struct flashctx *flash) |
| 536 | { |
| 537 | uint8_t status; |
| 538 | |
| 539 | status = spi_read_status_register(flash); |
| 540 | spi_prettyprint_status_register_hex(status); |
| 541 | |
| 542 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 543 | spi_prettyprint_status_register_bit(status, 6); |
| 544 | spi_prettyprint_status_register_bit(status, 5); |
| 545 | spi_prettyprint_status_register_bit(status, 4); |
| 546 | spi_prettyprint_status_register_bp(status, 1); |
| 547 | spi_prettyprint_status_register_welwip(status); |
| 548 | return 0; |
| 549 | } |
| 550 | |
| 551 | int spi_prettyprint_status_register_at25f512a(struct flashctx *flash) |
| 552 | { |
| 553 | uint8_t status; |
| 554 | |
| 555 | status = spi_read_status_register(flash); |
| 556 | spi_prettyprint_status_register_hex(status); |
| 557 | |
| 558 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 559 | spi_prettyprint_status_register_bit(status, 6); |
| 560 | spi_prettyprint_status_register_bit(status, 5); |
| 561 | spi_prettyprint_status_register_bit(status, 4); |
| 562 | spi_prettyprint_status_register_bit(status, 3); |
| 563 | spi_prettyprint_status_register_bp(status, 0); |
| 564 | spi_prettyprint_status_register_welwip(status); |
| 565 | return 0; |
| 566 | } |
| 567 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 568 | int spi_prettyprint_status_register_at25f512b(struct flashctx *flash) |
| 569 | { |
| 570 | uint8_t status = spi_read_status_register(flash); |
| 571 | spi_prettyprint_status_register_hex(status); |
| 572 | |
| 573 | spi_prettyprint_status_register_atmel_at25_srpl(status); |
| 574 | spi_prettyprint_status_register_bit(status, 6); |
| 575 | spi_prettyprint_status_register_atmel_at25_epewpp(status); |
| 576 | spi_prettyprint_status_register_bit(status, 3); |
| 577 | spi_prettyprint_status_register_bp(status, 0); |
| 578 | spi_prettyprint_status_register_welwip(status); |
| 579 | return 0; |
| 580 | } |
| 581 | |
Stefan Tauner | 57794ac | 2012-12-29 15:04:20 +0000 | [diff] [blame] | 582 | int spi_prettyprint_status_register_at25f4096(struct flashctx *flash) |
| 583 | { |
| 584 | uint8_t status; |
| 585 | |
| 586 | status = spi_read_status_register(flash); |
| 587 | spi_prettyprint_status_register_hex(status); |
| 588 | |
| 589 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 590 | spi_prettyprint_status_register_bit(status, 6); |
| 591 | spi_prettyprint_status_register_bit(status, 5); |
| 592 | spi_prettyprint_status_register_bp(status, 2); |
| 593 | spi_prettyprint_status_register_welwip(status); |
| 594 | return 0; |
| 595 | } |
| 596 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 597 | int spi_prettyprint_status_register_at25fs010(struct flashctx *flash) |
| 598 | { |
| 599 | uint8_t status = spi_read_status_register(flash); |
| 600 | spi_prettyprint_status_register_hex(status); |
| 601 | |
| 602 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 603 | msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " |
| 604 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
| 605 | msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
| 606 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
| 607 | spi_prettyprint_status_register_bit(status, 4); |
| 608 | msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
| 609 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
| 610 | msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
| 611 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
| 612 | /* FIXME: Pretty-print detailed sector protection status. */ |
| 613 | spi_prettyprint_status_register_welwip(status); |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | int spi_prettyprint_status_register_at25fs040(struct flashctx *flash) |
| 618 | { |
| 619 | uint8_t status = spi_read_status_register(flash); |
| 620 | spi_prettyprint_status_register_hex(status); |
| 621 | |
| 622 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 623 | spi_prettyprint_status_register_bp(status, 4); |
| 624 | /* FIXME: Pretty-print detailed sector protection status. */ |
| 625 | spi_prettyprint_status_register_welwip(status); |
| 626 | return 0; |
| 627 | } |
| 628 | |
| 629 | int spi_prettyprint_status_register_at26df081a(struct flashctx *flash) |
| 630 | { |
| 631 | uint8_t status = spi_read_status_register(flash); |
| 632 | spi_prettyprint_status_register_hex(status); |
| 633 | |
| 634 | spi_prettyprint_status_register_atmel_at25_srpl(status); |
| 635 | msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) is %sset\n", |
| 636 | (status & (1 << 6)) ? "" : "not "); |
| 637 | spi_prettyprint_status_register_atmel_at25_epewpp(status); |
| 638 | spi_prettyprint_status_register_atmel_at25_swp(status); |
| 639 | spi_prettyprint_status_register_welwip(status); |
| 640 | return 0; |
| 641 | } |
| 642 | |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 643 | /* Some Atmel DataFlash chips support per sector protection bits and the write protection bits in the status |
| 644 | * register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all |
| 645 | * sectors at once by writing 0 not only the protection bits (2 and 3) but also completely unrelated bits (4 and |
| 646 | * 5) which normally are not touched. |
| 647 | * Affected are all known Atmel chips matched by AT2[56]D[FLQ]..1A? but the AT26DF041. */ |
| 648 | int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 649 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 650 | return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 1 << 4, 0x00); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 651 | } |
| 652 | |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 653 | int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash) |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 654 | { |
| 655 | /* FIXME: We should check the security lockdown. */ |
| 656 | msg_cinfo("Ignoring security lockdown (if present)\n"); |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 657 | return spi_disable_blockprotect_at2x_global_unprotect(flash); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 658 | } |
| 659 | |
Stefan Tauner | 57794ac | 2012-12-29 15:04:20 +0000 | [diff] [blame] | 660 | int spi_disable_blockprotect_at25f(struct flashctx *flash) |
| 661 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 662 | return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF); |
Stefan Tauner | 57794ac | 2012-12-29 15:04:20 +0000 | [diff] [blame] | 663 | } |
| 664 | |
| 665 | int spi_disable_blockprotect_at25f512a(struct flashctx *flash) |
| 666 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 667 | return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 0, 0xFF); |
Stefan Tauner | 57794ac | 2012-12-29 15:04:20 +0000 | [diff] [blame] | 668 | } |
| 669 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 670 | int spi_disable_blockprotect_at25f512b(struct flashctx *flash) |
| 671 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 672 | return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 1 << 4, 0xFF); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 673 | } |
| 674 | |
| 675 | int spi_disable_blockprotect_at25fs010(struct flashctx *flash) |
| 676 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 677 | return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0, 0xFF); |
Stefan Tauner | 9530a02 | 2012-12-29 15:04:05 +0000 | [diff] [blame] | 678 | } |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 679 | |
| 680 | int spi_disable_blockprotect_at25fs040(struct flashctx *flash) |
| 681 | { |
Stefan Tauner | cecb2c5 | 2013-06-20 22:55:41 +0000 | [diff] [blame] | 682 | return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 683 | } |
| 684 | |
Nikolay Nikolaev | d0e3ea1 | 2013-06-28 21:29:08 +0000 | [diff] [blame] | 685 | /* === Eon === */ |
| 686 | |
| 687 | int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash) |
| 688 | { |
| 689 | uint8_t status = spi_read_status_register(flash); |
| 690 | spi_prettyprint_status_register_hex(status); |
| 691 | |
| 692 | spi_prettyprint_status_register_srwd(status); |
| 693 | msg_cdbg("Chip status register: WP# disable (WPDIS) is %sabled\n", (status & (1 << 6)) ? "en " : "dis"); |
| 694 | spi_prettyprint_status_register_bp(status, 3); |
| 695 | spi_prettyprint_status_register_welwip(status); |
| 696 | return 0; |
| 697 | } |
| 698 | |
Nikolay Nikolaev | c80c4a3 | 2013-06-28 21:29:44 +0000 | [diff] [blame] | 699 | /* === Intel/Numonyx/Micron - Spansion === */ |
Stefan Tauner | 54aaa4a | 2012-12-29 15:04:12 +0000 | [diff] [blame] | 700 | |
Nikolay Nikolaev | 6f59b0b | 2013-06-28 21:29:51 +0000 | [diff] [blame] | 701 | int spi_disable_blockprotect_n25q(struct flashctx *flash) |
| 702 | { |
| 703 | return spi_disable_blockprotect_generic(flash, 0x5C, 1 << 7, 0, 0xFF); |
| 704 | } |
| 705 | |
| 706 | int spi_prettyprint_status_register_n25q(struct flashctx *flash) |
| 707 | { |
| 708 | uint8_t status = spi_read_status_register(flash); |
| 709 | spi_prettyprint_status_register_hex(status); |
| 710 | |
| 711 | spi_prettyprint_status_register_srwd(status); |
| 712 | if (flash->chip->total_size <= 32 / 8 * 1024) /* N25Q16 and N25Q32: reserved */ |
| 713 | spi_prettyprint_status_register_bit(status, 6); |
| 714 | else |
| 715 | msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n", |
| 716 | (status & (1 << 6)) ? "" : "not "); |
| 717 | msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top"); |
| 718 | spi_prettyprint_status_register_bp(status, 2); |
| 719 | spi_prettyprint_status_register_welwip(status); |
| 720 | return 0; |
| 721 | } |
| 722 | |
Nikolay Nikolaev | c80c4a3 | 2013-06-28 21:29:44 +0000 | [diff] [blame] | 723 | /* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */ |
Stefan Tauner | 54aaa4a | 2012-12-29 15:04:12 +0000 | [diff] [blame] | 724 | /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ |
Nikolay Nikolaev | c80c4a3 | 2013-06-28 21:29:44 +0000 | [diff] [blame] | 725 | int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash) |
Stefan Tauner | 54aaa4a | 2012-12-29 15:04:12 +0000 | [diff] [blame] | 726 | { |
Stefan Tauner | 278ba6e | 2013-06-28 21:28:27 +0000 | [diff] [blame] | 727 | return spi_disable_blockprotect_bp2_srwd(flash); |
Stefan Tauner | 54aaa4a | 2012-12-29 15:04:12 +0000 | [diff] [blame] | 728 | } |
| 729 | |
Nikolay Nikolaev | c80c4a3 | 2013-06-28 21:29:44 +0000 | [diff] [blame] | 730 | /* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */ |
| 731 | int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash) |
Stefan Tauner | 54aaa4a | 2012-12-29 15:04:12 +0000 | [diff] [blame] | 732 | { |
| 733 | uint8_t status = spi_read_status_register(flash); |
Stefan Tauner | c2eec2c | 2014-05-03 21:33:01 +0000 | [diff] [blame] | 734 | spi_prettyprint_status_register_hex(status); |
Stefan Tauner | 54aaa4a | 2012-12-29 15:04:12 +0000 | [diff] [blame] | 735 | |
| 736 | spi_prettyprint_status_register_srwd(status); |
| 737 | msg_cdbg("Chip status register: Program Fail Flag (P_FAIL) is %sset\n", |
| 738 | (status & (1 << 6)) ? "" : "not "); |
| 739 | msg_cdbg("Chip status register: Erase Fail Flag (E_FAIL) is %sset\n", |
| 740 | (status & (1 << 5)) ? "" : "not "); |
| 741 | spi_prettyprint_status_register_bp(status, 2); |
| 742 | spi_prettyprint_status_register_welwip(status); |
| 743 | return 0; |
| 744 | } |
| 745 | |
Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame] | 746 | /* === SST === */ |
| 747 | |
| 748 | static void spi_prettyprint_status_register_sst25_common(uint8_t status) |
| 749 | { |
| 750 | spi_prettyprint_status_register_hex(status); |
| 751 | |
| 752 | spi_prettyprint_status_register_bpl(status); |
| 753 | msg_cdbg("Chip status register: Auto Address Increment Programming (AAI) is %sset\n", |
| 754 | (status & (1 << 6)) ? "" : "not "); |
| 755 | spi_prettyprint_status_register_bp(status, 3); |
| 756 | spi_prettyprint_status_register_welwip(status); |
| 757 | } |
| 758 | |
| 759 | int spi_prettyprint_status_register_sst25(struct flashctx *flash) |
| 760 | { |
| 761 | uint8_t status = spi_read_status_register(flash); |
| 762 | spi_prettyprint_status_register_sst25_common(status); |
| 763 | return 0; |
| 764 | } |
| 765 | |
| 766 | int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash) |
| 767 | { |
| 768 | static const char *const bpt[] = { |
| 769 | "none", |
| 770 | "1F0000H-1FFFFFH", |
| 771 | "1E0000H-1FFFFFH", |
| 772 | "1C0000H-1FFFFFH", |
| 773 | "180000H-1FFFFFH", |
| 774 | "100000H-1FFFFFH", |
| 775 | "all", "all" |
| 776 | }; |
| 777 | uint8_t status = spi_read_status_register(flash); |
| 778 | spi_prettyprint_status_register_sst25_common(status); |
| 779 | msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); |
| 780 | return 0; |
| 781 | } |
| 782 | |
| 783 | int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash) |
| 784 | { |
| 785 | static const char *const bpt[] = { |
| 786 | "none", |
| 787 | "0x70000-0x7ffff", |
| 788 | "0x60000-0x7ffff", |
| 789 | "0x40000-0x7ffff", |
| 790 | "all blocks", "all blocks", "all blocks", "all blocks" |
| 791 | }; |
| 792 | uint8_t status = spi_read_status_register(flash); |
| 793 | spi_prettyprint_status_register_sst25_common(status); |
| 794 | msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); |
| 795 | return 0; |
| 796 | } |