const'ify flashctx to align signatures with cros flashrom
The ChromiumOS flashrom fork has since const'ify flashctx
in a few places. This aligns the function signatures to
match with downstream to ease forward porting patches
out of downstream back into mainline flashrom.
This patch is minimum viable alignment and so feedback is
welcome.
Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70933
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index bb09e58..34f9ad4 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -22,7 +22,7 @@
#include "spi.h"
/* === Generic functions === */
-static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode)
+static int spi_write_status_register_flag(const struct flashctx *flash, int status, const unsigned char enable_opcode)
{
int result;
int i = 0;
@@ -73,7 +73,7 @@
return 0;
}
-int spi_write_status_register(struct flashctx *flash, int status)
+int spi_write_status_register(const struct flashctx *flash, int status)
{
int feature_bits = flash->chip->feature_bits;
int ret = 1;
@@ -90,7 +90,7 @@
return ret;
}
-uint8_t spi_read_status_register(struct flashctx *flash)
+uint8_t spi_read_status_register(const struct flashctx *flash)
{
static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
/* FIXME: No workarounds for driver/hardware bugs in generic code. */