Stefan Tauner | 6ee37e2 | 2012-12-29 15:03:51 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * It handles everything related to status registers of the JEDEC family 25. |
| 4 | * |
| 5 | * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger |
| 6 | * Copyright (C) 2008 coresystems GmbH |
| 7 | * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl> |
| 8 | * Copyright (C) 2012 Stefan Tauner |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | */ |
| 23 | |
| 24 | #include "flash.h" |
| 25 | #include "chipdrivers.h" |
| 26 | #include "spi.h" |
| 27 | |
| 28 | /* === Generic functions === */ |
| 29 | int spi_write_status_enable(struct flashctx *flash) |
| 30 | { |
| 31 | static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; |
| 32 | int result; |
| 33 | |
| 34 | /* Send EWSR (Enable Write Status Register). */ |
| 35 | result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); |
| 36 | |
| 37 | if (result) |
| 38 | msg_cerr("%s failed\n", __func__); |
| 39 | |
| 40 | return result; |
| 41 | } |
| 42 | |
| 43 | static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode) |
| 44 | { |
| 45 | int result; |
| 46 | int i = 0; |
| 47 | /* |
| 48 | * WRSR requires either EWSR or WREN depending on chip type. |
| 49 | * The code below relies on the fact hat EWSR and WREN have the same |
| 50 | * INSIZE and OUTSIZE. |
| 51 | */ |
| 52 | struct spi_command cmds[] = { |
| 53 | { |
| 54 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 55 | .writearr = (const unsigned char[]){ enable_opcode }, |
| 56 | .readcnt = 0, |
| 57 | .readarr = NULL, |
| 58 | }, { |
| 59 | .writecnt = JEDEC_WRSR_OUTSIZE, |
| 60 | .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, |
| 61 | .readcnt = 0, |
| 62 | .readarr = NULL, |
| 63 | }, { |
| 64 | .writecnt = 0, |
| 65 | .writearr = NULL, |
| 66 | .readcnt = 0, |
| 67 | .readarr = NULL, |
| 68 | }}; |
| 69 | |
| 70 | result = spi_send_multicommand(flash, cmds); |
| 71 | if (result) { |
| 72 | msg_cerr("%s failed during command execution\n", __func__); |
| 73 | /* No point in waiting for the command to complete if execution |
| 74 | * failed. |
| 75 | */ |
| 76 | return result; |
| 77 | } |
| 78 | /* WRSR performs a self-timed erase before the changes take effect. |
| 79 | * This may take 50-85 ms in most cases, and some chips apparently |
| 80 | * allow running RDSR only once. Therefore pick an initial delay of |
| 81 | * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed. |
| 82 | */ |
| 83 | programmer_delay(100 * 1000); |
| 84 | while (spi_read_status_register(flash) & SPI_SR_WIP) { |
| 85 | if (++i > 490) { |
| 86 | msg_cerr("Error: WIP bit after WRSR never cleared\n"); |
| 87 | return TIMEOUT_ERROR; |
| 88 | } |
| 89 | programmer_delay(10 * 1000); |
| 90 | } |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | int spi_write_status_register(struct flashctx *flash, int status) |
| 95 | { |
| 96 | int feature_bits = flash->chip->feature_bits; |
| 97 | int ret = 1; |
| 98 | |
| 99 | if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) { |
| 100 | msg_cdbg("Missing status register write definition, assuming " |
| 101 | "EWSR is needed\n"); |
| 102 | feature_bits |= FEATURE_WRSR_EWSR; |
| 103 | } |
| 104 | if (feature_bits & FEATURE_WRSR_WREN) |
| 105 | ret = spi_write_status_register_flag(flash, status, JEDEC_WREN); |
| 106 | if (ret && (feature_bits & FEATURE_WRSR_EWSR)) |
| 107 | ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR); |
| 108 | return ret; |
| 109 | } |
| 110 | |
| 111 | uint8_t spi_read_status_register(struct flashctx *flash) |
| 112 | { |
| 113 | static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; |
| 114 | /* FIXME: No workarounds for driver/hardware bugs in generic code. */ |
| 115 | unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ |
| 116 | int ret; |
| 117 | |
| 118 | /* Read Status Register */ |
| 119 | ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); |
| 120 | if (ret) |
| 121 | msg_cerr("RDSR failed!\n"); |
| 122 | |
| 123 | return readarr[0]; |
| 124 | } |
| 125 | |
| 126 | /* A generic brute-force block protection disable works like this: |
| 127 | * Write 0x00 to the status register. Check if any locks are still set (that |
| 128 | * part is chip specific). Repeat once. |
| 129 | */ |
| 130 | int spi_disable_blockprotect(struct flashctx *flash) |
| 131 | { |
| 132 | uint8_t status; |
| 133 | int result; |
| 134 | |
| 135 | status = spi_read_status_register(flash); |
| 136 | /* If block protection is disabled, stop here. */ |
| 137 | if ((status & 0x3c) == 0) |
| 138 | return 0; |
| 139 | |
| 140 | msg_cdbg("Some block protection in effect, disabling... "); |
| 141 | result = spi_write_status_register(flash, status & ~0x3c); |
| 142 | if (result) { |
| 143 | msg_cerr("spi_write_status_register failed.\n"); |
| 144 | return result; |
| 145 | } |
| 146 | status = spi_read_status_register(flash); |
| 147 | if ((status & 0x3c) != 0) { |
| 148 | msg_cerr("Block protection could not be disabled!\n"); |
| 149 | return 1; |
| 150 | } |
| 151 | msg_cdbg("done.\n"); |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | static void spi_prettyprint_status_register_hex(uint8_t status) |
| 156 | { |
| 157 | msg_cdbg("Chip status register is 0x%02x.\n", status); |
| 158 | } |
| 159 | |
| 160 | /* Common highest bit: Status Register Write Disable (SRWD). */ |
| 161 | static void spi_prettyprint_status_register_srwd(uint8_t status) |
| 162 | { |
| 163 | msg_cdbg("Chip status register: Status Register Write Disable (SRWD) is %sset\n", |
| 164 | (status & (1 << 7)) ? "" : "not "); |
| 165 | } |
| 166 | |
| 167 | /* Common highest bit: Block Protect Write Disable (BPL). */ |
| 168 | static void spi_prettyprint_status_register_bpl(uint8_t status) |
| 169 | { |
| 170 | msg_cdbg("Chip status register: Block Protect Write Disable (BPL) is %sset\n", |
| 171 | (status & (1 << 7)) ? "" : "not "); |
| 172 | } |
| 173 | |
| 174 | /* Common lowest 2 bits: WEL and WIP. */ |
| 175 | static void spi_prettyprint_status_register_welwip(uint8_t status) |
| 176 | { |
| 177 | msg_cdbg("Chip status register: Write Enable Latch (WEL) is %sset\n", |
| 178 | (status & (1 << 1)) ? "" : "not "); |
| 179 | msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is %sset\n", |
| 180 | (status & (1 << 0)) ? "" : "not "); |
| 181 | } |
| 182 | |
| 183 | /* Common block protection (BP) bits. */ |
| 184 | static void spi_prettyprint_status_register_bp(uint8_t status, int bp) |
| 185 | { |
| 186 | switch (bp) { |
| 187 | /* Fall through. */ |
| 188 | case 4: |
| 189 | msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n", |
| 190 | (status & (1 << 5)) ? "" : "not "); |
| 191 | case 3: |
| 192 | msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n", |
| 193 | (status & (1 << 5)) ? "" : "not "); |
| 194 | case 2: |
| 195 | msg_cdbg("Chip status register: Block Protect 2 (BP2) is %sset\n", |
| 196 | (status & (1 << 4)) ? "" : "not "); |
| 197 | case 1: |
| 198 | msg_cdbg("Chip status register: Block Protect 1 (BP1) is %sset\n", |
| 199 | (status & (1 << 3)) ? "" : "not "); |
| 200 | case 0: |
| 201 | msg_cdbg("Chip status register: Block Protect 0 (BP0) is %sset\n", |
| 202 | (status & (1 << 2)) ? "" : "not "); |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | /* Unnamed bits. */ |
| 207 | static void spi_prettyprint_status_register_bit(uint8_t status, int bit) |
| 208 | { |
| 209 | msg_cdbg("Chip status register: Bit %i is %sset\n", bit, (status & (1 << bit)) ? "" : "not "); |
| 210 | } |
| 211 | |
| 212 | int spi_prettyprint_status_register_plain(struct flashctx *flash) |
| 213 | { |
| 214 | uint8_t status = spi_read_status_register(flash); |
| 215 | spi_prettyprint_status_register_hex(status); |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | /* Works for many chips of the |
| 220 | * AMIC A25L series |
| 221 | * and MX MX25L512 |
| 222 | */ |
| 223 | int spi_prettyprint_status_register_default_bp1(struct flashctx *flash) |
| 224 | { |
| 225 | uint8_t status = spi_read_status_register(flash); |
| 226 | spi_prettyprint_status_register_hex(status); |
| 227 | |
| 228 | spi_prettyprint_status_register_srwd(status); |
| 229 | spi_prettyprint_status_register_bit(status, 6); |
| 230 | spi_prettyprint_status_register_bit(status, 5); |
| 231 | spi_prettyprint_status_register_bit(status, 4); |
| 232 | spi_prettyprint_status_register_bp(status, 1); |
| 233 | spi_prettyprint_status_register_welwip(status); |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | /* Works for many chips of the |
| 238 | * AMIC A25L series |
| 239 | */ |
| 240 | int spi_prettyprint_status_register_default_bp2(struct flashctx *flash) |
| 241 | { |
| 242 | uint8_t status = spi_read_status_register(flash); |
| 243 | spi_prettyprint_status_register_hex(status); |
| 244 | |
| 245 | spi_prettyprint_status_register_srwd(status); |
| 246 | spi_prettyprint_status_register_bit(status, 6); |
| 247 | spi_prettyprint_status_register_bit(status, 5); |
| 248 | spi_prettyprint_status_register_bp(status, 2); |
| 249 | spi_prettyprint_status_register_welwip(status); |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | /* Works for many chips of the |
| 254 | * ST M25P series |
| 255 | * MX MX25L series |
| 256 | */ |
| 257 | int spi_prettyprint_status_register_default_bp3(struct flashctx *flash) |
| 258 | { |
| 259 | uint8_t status = spi_read_status_register(flash); |
| 260 | spi_prettyprint_status_register_hex(status); |
| 261 | |
| 262 | spi_prettyprint_status_register_srwd(status); |
| 263 | spi_prettyprint_status_register_bit(status, 6); |
| 264 | spi_prettyprint_status_register_bp(status, 3); |
| 265 | spi_prettyprint_status_register_welwip(status); |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | /* === Amic === |
| 270 | * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using |
| 271 | * spi_prettyprint_status_register_default_bp1 or |
| 272 | * spi_prettyprint_status_register_default_bp2. |
| 273 | * FIXME: spi_disable_blockprotect is incorrect and will fail for chips using |
| 274 | * spi_prettyprint_status_register_amic_a25l032 if those have locks controlled |
| 275 | * by the second status register. |
| 276 | */ |
| 277 | |
| 278 | int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash) |
| 279 | { |
| 280 | uint8_t status = spi_read_status_register(flash); |
| 281 | spi_prettyprint_status_register_hex(status); |
| 282 | |
| 283 | spi_prettyprint_status_register_srwd(status); |
| 284 | msg_cdbg("Chip status register: Sector Protect Size (SEC) is %i KB\n", (status & (1 << 6)) ? 4 : 64); |
| 285 | msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top"); |
| 286 | spi_prettyprint_status_register_bp(status, 2); |
| 287 | spi_prettyprint_status_register_welwip(status); |
| 288 | msg_cdbg("Chip status register 2 is NOT decoded!\n"); |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | /* === Atmel === */ |
| 293 | |
| 294 | static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status) |
| 295 | { |
| 296 | msg_cdbg("Chip status register: Write Protect Enable (WPEN) is %sset\n", |
| 297 | (status & (1 << 7)) ? "" : "not "); |
| 298 | } |
| 299 | |
| 300 | static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) |
| 301 | { |
| 302 | msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) is %sset\n", |
| 303 | (status & (1 << 7)) ? "" : "not "); |
| 304 | } |
| 305 | |
| 306 | static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status) |
| 307 | { |
| 308 | msg_cdbg("Chip status register: Erase/Program Error (EPE) is %sset\n", |
| 309 | (status & (1 << 5)) ? "" : "not "); |
| 310 | msg_cdbg("Chip status register: WP# pin (WPP) is %sasserted\n", |
| 311 | (status & (1 << 4)) ? "not " : ""); |
| 312 | } |
| 313 | |
| 314 | static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status) |
| 315 | { |
| 316 | msg_cdbg("Chip status register: Software Protection Status (SWP): "); |
| 317 | switch (status & (3 << 2)) { |
| 318 | case 0x0 << 2: |
| 319 | msg_cdbg("no sectors are protected\n"); |
| 320 | break; |
| 321 | case 0x1 << 2: |
| 322 | msg_cdbg("some sectors are protected\n"); |
| 323 | /* FIXME: Read individual Sector Protection Registers. */ |
| 324 | break; |
| 325 | case 0x3 << 2: |
| 326 | msg_cdbg("all sectors are protected\n"); |
| 327 | break; |
| 328 | default: |
| 329 | msg_cdbg("reserved for future use\n"); |
| 330 | break; |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | int spi_prettyprint_status_register_at25df(struct flashctx *flash) |
| 335 | { |
| 336 | uint8_t status = spi_read_status_register(flash); |
| 337 | spi_prettyprint_status_register_hex(status); |
| 338 | |
| 339 | spi_prettyprint_status_register_atmel_at25_srpl(status); |
| 340 | spi_prettyprint_status_register_bit(status, 6); |
| 341 | spi_prettyprint_status_register_atmel_at25_epewpp(status); |
| 342 | spi_prettyprint_status_register_atmel_at25_swp(status); |
| 343 | spi_prettyprint_status_register_welwip(status); |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash) |
| 348 | { |
| 349 | /* FIXME: We should check the security lockdown. */ |
| 350 | msg_cdbg("Ignoring security lockdown (if present)\n"); |
| 351 | msg_cdbg("Ignoring status register byte 2\n"); |
| 352 | return spi_prettyprint_status_register_at25df(flash); |
| 353 | } |
| 354 | |
| 355 | int spi_prettyprint_status_register_at25f512b(struct flashctx *flash) |
| 356 | { |
| 357 | uint8_t status = spi_read_status_register(flash); |
| 358 | spi_prettyprint_status_register_hex(status); |
| 359 | |
| 360 | spi_prettyprint_status_register_atmel_at25_srpl(status); |
| 361 | spi_prettyprint_status_register_bit(status, 6); |
| 362 | spi_prettyprint_status_register_atmel_at25_epewpp(status); |
| 363 | spi_prettyprint_status_register_bit(status, 3); |
| 364 | spi_prettyprint_status_register_bp(status, 0); |
| 365 | spi_prettyprint_status_register_welwip(status); |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | int spi_prettyprint_status_register_at25fs010(struct flashctx *flash) |
| 370 | { |
| 371 | uint8_t status = spi_read_status_register(flash); |
| 372 | spi_prettyprint_status_register_hex(status); |
| 373 | |
| 374 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 375 | msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " |
| 376 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
| 377 | msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
| 378 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
| 379 | spi_prettyprint_status_register_bit(status, 4); |
| 380 | msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
| 381 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
| 382 | msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
| 383 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
| 384 | /* FIXME: Pretty-print detailed sector protection status. */ |
| 385 | spi_prettyprint_status_register_welwip(status); |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | int spi_prettyprint_status_register_at25fs040(struct flashctx *flash) |
| 390 | { |
| 391 | uint8_t status = spi_read_status_register(flash); |
| 392 | spi_prettyprint_status_register_hex(status); |
| 393 | |
| 394 | spi_prettyprint_status_register_atmel_at25_wpen(status); |
| 395 | spi_prettyprint_status_register_bp(status, 4); |
| 396 | /* FIXME: Pretty-print detailed sector protection status. */ |
| 397 | spi_prettyprint_status_register_welwip(status); |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | int spi_prettyprint_status_register_at26df081a(struct flashctx *flash) |
| 402 | { |
| 403 | uint8_t status = spi_read_status_register(flash); |
| 404 | spi_prettyprint_status_register_hex(status); |
| 405 | |
| 406 | spi_prettyprint_status_register_atmel_at25_srpl(status); |
| 407 | msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) is %sset\n", |
| 408 | (status & (1 << 6)) ? "" : "not "); |
| 409 | spi_prettyprint_status_register_atmel_at25_epewpp(status); |
| 410 | spi_prettyprint_status_register_atmel_at25_swp(status); |
| 411 | spi_prettyprint_status_register_welwip(status); |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | int spi_disable_blockprotect_at25df(struct flashctx *flash) |
| 416 | { |
| 417 | uint8_t status; |
| 418 | int result; |
| 419 | |
| 420 | status = spi_read_status_register(flash); |
| 421 | /* If block protection is disabled, stop here. */ |
| 422 | if ((status & (3 << 2)) == 0) |
| 423 | return 0; |
| 424 | |
| 425 | msg_cdbg("Some block protection in effect, disabling... "); |
| 426 | if (status & (1 << 7)) { |
| 427 | msg_cdbg("Need to disable Sector Protection Register Lock\n"); |
| 428 | if ((status & (1 << 4)) == 0) { |
| 429 | msg_cerr("WP# pin is active, disabling " |
| 430 | "write protection is impossible.\n"); |
| 431 | return 1; |
| 432 | } |
| 433 | /* All bits except bit 7 (SPRL) are readonly. */ |
| 434 | result = spi_write_status_register(flash, status & ~(1 << 7)); |
| 435 | if (result) { |
| 436 | msg_cerr("spi_write_status_register failed.\n"); |
| 437 | return result; |
| 438 | } |
| 439 | |
| 440 | } |
| 441 | /* Global unprotect. Make sure to mask SPRL as well. */ |
| 442 | result = spi_write_status_register(flash, status & ~0xbc); |
| 443 | if (result) { |
| 444 | msg_cerr("spi_write_status_register failed.\n"); |
| 445 | return result; |
| 446 | } |
| 447 | status = spi_read_status_register(flash); |
| 448 | if ((status & (3 << 2)) != 0) { |
| 449 | msg_cerr("Block protection could not be disabled!\n"); |
| 450 | return 1; |
| 451 | } |
| 452 | msg_cdbg("done.\n"); |
| 453 | return 0; |
| 454 | } |
| 455 | |
| 456 | int spi_disable_blockprotect_at25df_sec(struct flashctx *flash) |
| 457 | { |
| 458 | /* FIXME: We should check the security lockdown. */ |
| 459 | msg_cinfo("Ignoring security lockdown (if present)\n"); |
| 460 | return spi_disable_blockprotect_at25df(flash); |
| 461 | } |
| 462 | |
| 463 | int spi_disable_blockprotect_at25f512b(struct flashctx *flash) |
| 464 | { |
| 465 | /* spi_disable_blockprotect_at25df is not really the right way to do |
| 466 | * this, but the side effects of said function work here as well. |
| 467 | */ |
| 468 | return spi_disable_blockprotect_at25df(flash); |
| 469 | } |
| 470 | |
| 471 | int spi_disable_blockprotect_at25fs010(struct flashctx *flash) |
| 472 | { |
| 473 | uint8_t status; |
| 474 | int result; |
| 475 | |
| 476 | status = spi_read_status_register(flash); |
| 477 | /* If block protection is disabled, stop here. */ |
| 478 | if ((status & 0x6c) == 0) |
| 479 | return 0; |
| 480 | |
| 481 | msg_cdbg("Some block protection in effect, disabling... "); |
| 482 | if (status & (1 << 7)) { |
| 483 | msg_cdbg("Need to disable Status Register Write Protect\n"); |
| 484 | /* Clear bit 7 (WPEN). */ |
| 485 | result = spi_write_status_register(flash, status & ~(1 << 7)); |
| 486 | if (result) { |
| 487 | msg_cerr("spi_write_status_register failed.\n"); |
| 488 | return result; |
| 489 | } |
| 490 | } |
| 491 | /* Global unprotect. Make sure to mask WPEN as well. */ |
| 492 | result = spi_write_status_register(flash, status & ~0xec); |
| 493 | if (result) { |
| 494 | msg_cerr("spi_write_status_register failed.\n"); |
| 495 | return result; |
| 496 | } |
| 497 | status = spi_read_status_register(flash); |
| 498 | if ((status & 0x6c) != 0) { |
| 499 | msg_cerr("Block protection could not be disabled!\n"); |
| 500 | return 1; |
| 501 | } |
| 502 | msg_cdbg("done.\n"); |
| 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | int spi_disable_blockprotect_at25fs040(struct flashctx *flash) |
| 507 | { |
| 508 | uint8_t status; |
| 509 | int result; |
| 510 | |
| 511 | status = spi_read_status_register(flash); |
| 512 | /* If block protection is disabled, stop here. */ |
| 513 | if ((status & 0x7c) == 0) |
| 514 | return 0; |
| 515 | |
| 516 | msg_cdbg("Some block protection in effect, disabling... "); |
| 517 | if (status & (1 << 7)) { |
| 518 | msg_cdbg("Need to disable Status Register Write Protect\n"); |
| 519 | /* Clear bit 7 (WPEN). */ |
| 520 | result = spi_write_status_register(flash, status & ~(1 << 7)); |
| 521 | if (result) { |
| 522 | msg_cerr("spi_write_status_register failed.\n"); |
| 523 | return result; |
| 524 | } |
| 525 | } |
| 526 | /* Global unprotect. Make sure to mask WPEN as well. */ |
| 527 | result = spi_write_status_register(flash, status & ~0xfc); |
| 528 | if (result) { |
| 529 | msg_cerr("spi_write_status_register failed.\n"); |
| 530 | return result; |
| 531 | } |
| 532 | status = spi_read_status_register(flash); |
| 533 | if ((status & 0x7c) != 0) { |
| 534 | msg_cerr("Block protection could not be disabled!\n"); |
| 535 | return 1; |
| 536 | } |
| 537 | msg_cdbg("done.\n"); |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | /* === SST === */ |
| 542 | |
| 543 | static void spi_prettyprint_status_register_sst25_common(uint8_t status) |
| 544 | { |
| 545 | spi_prettyprint_status_register_hex(status); |
| 546 | |
| 547 | spi_prettyprint_status_register_bpl(status); |
| 548 | msg_cdbg("Chip status register: Auto Address Increment Programming (AAI) is %sset\n", |
| 549 | (status & (1 << 6)) ? "" : "not "); |
| 550 | spi_prettyprint_status_register_bp(status, 3); |
| 551 | spi_prettyprint_status_register_welwip(status); |
| 552 | } |
| 553 | |
| 554 | int spi_prettyprint_status_register_sst25(struct flashctx *flash) |
| 555 | { |
| 556 | uint8_t status = spi_read_status_register(flash); |
| 557 | spi_prettyprint_status_register_sst25_common(status); |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash) |
| 562 | { |
| 563 | static const char *const bpt[] = { |
| 564 | "none", |
| 565 | "1F0000H-1FFFFFH", |
| 566 | "1E0000H-1FFFFFH", |
| 567 | "1C0000H-1FFFFFH", |
| 568 | "180000H-1FFFFFH", |
| 569 | "100000H-1FFFFFH", |
| 570 | "all", "all" |
| 571 | }; |
| 572 | uint8_t status = spi_read_status_register(flash); |
| 573 | spi_prettyprint_status_register_sst25_common(status); |
| 574 | msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); |
| 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash) |
| 579 | { |
| 580 | static const char *const bpt[] = { |
| 581 | "none", |
| 582 | "0x70000-0x7ffff", |
| 583 | "0x60000-0x7ffff", |
| 584 | "0x40000-0x7ffff", |
| 585 | "all blocks", "all blocks", "all blocks", "all blocks" |
| 586 | }; |
| 587 | uint8_t status = spi_read_status_register(flash); |
| 588 | spi_prettyprint_status_register_sst25_common(status); |
| 589 | msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); |
| 590 | return 0; |
| 591 | } |