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Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __PROGRAMMER_H__
25#define __PROGRAMMER_H__ 1
26
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +000027#include "flash.h" /* for chipaddr and flashchip */
28
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029enum programmer {
30#if CONFIG_INTERNAL == 1
31 PROGRAMMER_INTERNAL,
32#endif
33#if CONFIG_DUMMY == 1
34 PROGRAMMER_DUMMY,
35#endif
36#if CONFIG_NIC3COM == 1
37 PROGRAMMER_NIC3COM,
38#endif
39#if CONFIG_NICREALTEK == 1
40 PROGRAMMER_NICREALTEK,
Idwer Vollering004f4b72010-09-03 18:21:21 +000041#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000042#if CONFIG_NICNATSEMI == 1
43 PROGRAMMER_NICNATSEMI,
Idwer Vollering004f4b72010-09-03 18:21:21 +000044#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000045#if CONFIG_GFXNVIDIA == 1
46 PROGRAMMER_GFXNVIDIA,
47#endif
48#if CONFIG_DRKAISER == 1
49 PROGRAMMER_DRKAISER,
50#endif
51#if CONFIG_SATASII == 1
52 PROGRAMMER_SATASII,
53#endif
54#if CONFIG_ATAHPT == 1
55 PROGRAMMER_ATAHPT,
56#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000057#if CONFIG_FT2232_SPI == 1
58 PROGRAMMER_FT2232_SPI,
59#endif
60#if CONFIG_SERPROG == 1
61 PROGRAMMER_SERPROG,
62#endif
63#if CONFIG_BUSPIRATE_SPI == 1
64 PROGRAMMER_BUSPIRATE_SPI,
65#endif
66#if CONFIG_DEDIPROG == 1
67 PROGRAMMER_DEDIPROG,
68#endif
69#if CONFIG_RAYER_SPI == 1
70 PROGRAMMER_RAYER_SPI,
71#endif
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000072#if CONFIG_NICINTEL == 1
73 PROGRAMMER_NICINTEL,
74#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +000075#if CONFIG_NICINTEL_SPI == 1
76 PROGRAMMER_NICINTEL_SPI,
77#endif
Mark Marshall90021f22010-12-03 14:48:11 +000078#if CONFIG_OGP_SPI == 1
79 PROGRAMMER_OGP_SPI,
80#endif
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000081#if CONFIG_SATAMV == 1
82 PROGRAMMER_SATAMV,
83#endif
Sven Schnelle5ce5f702011-09-03 18:37:52 +000084#if CONFIG_LINUX_SPI == 1
85 PROGRAMMER_LINUX_SPI,
86#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000087 PROGRAMMER_INVALID /* This must always be the last entry. */
88};
89
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000090struct programmer_entry {
91 const char *vendor;
92 const char *name;
93
94 int (*init) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000095
96 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,
97 size_t len);
98 void (*unmap_flash_region) (void *virt_addr, size_t len);
99
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000100 void (*delay) (int usecs);
101};
102
103extern const struct programmer_entry programmer_table[];
104
Carl-Daniel Hailfinger2e681602011-09-08 00:00:29 +0000105int programmer_init(enum programmer prog, char *param);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000106int programmer_shutdown(void);
107
108enum bitbang_spi_master_type {
109 BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */
110#if CONFIG_RAYER_SPI == 1
111 BITBANG_SPI_MASTER_RAYER,
112#endif
Idwer Vollering004f4b72010-09-03 18:21:21 +0000113#if CONFIG_NICINTEL_SPI == 1
114 BITBANG_SPI_MASTER_NICINTEL,
115#endif
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000116#if CONFIG_INTERNAL == 1
117#if defined(__i386__) || defined(__x86_64__)
118 BITBANG_SPI_MASTER_MCP,
119#endif
120#endif
Mark Marshall90021f22010-12-03 14:48:11 +0000121#if CONFIG_OGP_SPI == 1
122 BITBANG_SPI_MASTER_OGP,
123#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000124};
125
126struct bitbang_spi_master {
127 enum bitbang_spi_master_type type;
128
129 /* Note that CS# is active low, so val=0 means the chip is active. */
130 void (*set_cs) (int val);
131 void (*set_sck) (int val);
132 void (*set_mosi) (int val);
133 int (*get_miso) (void);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000134 void (*request_bus) (void);
135 void (*release_bus) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000136};
137
138#if CONFIG_INTERNAL == 1
139struct penable {
140 uint16_t vendor_id;
141 uint16_t device_id;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000142 int status; /* OK=0 and NT=1 are defines only. Beware! */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000143 const char *vendor_name;
144 const char *device_name;
145 int (*doit) (struct pci_dev *dev, const char *name);
146};
147
148extern const struct penable chipset_enables[];
149
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000150enum board_match_phase {
151 P1,
152 P2,
153 P3
154};
155
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +0000156struct board_match {
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000157 /* Any device, but make it sensible, like the ISA bridge. */
158 uint16_t first_vendor;
159 uint16_t first_device;
160 uint16_t first_card_vendor;
161 uint16_t first_card_device;
162
163 /* Any device, but make it sensible, like
164 * the host bridge. May be NULL.
165 */
166 uint16_t second_vendor;
167 uint16_t second_device;
168 uint16_t second_card_vendor;
169 uint16_t second_card_device;
170
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000171 /* Pattern to match DMI entries. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000172 const char *dmi_pattern;
173
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000174 /* The vendor / part name from the coreboot table. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000175 const char *lb_vendor;
176 const char *lb_part;
177
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000178 enum board_match_phase phase;
179
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000180 const char *vendor_name;
181 const char *board_name;
182
183 int max_rom_decode_parallel;
184 int status;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000185 int (*enable) (void); /* May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000186};
187
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +0000188extern const struct board_match board_matches[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000189
190struct board_info {
191 const char *vendor;
192 const char *name;
193 const int working;
194#ifdef CONFIG_PRINT_WIKI
195 const char *url;
196 const char *note;
197#endif
198};
199
200extern const struct board_info boards_known[];
201extern const struct board_info laptops_known[];
202#endif
203
204/* udelay.c */
205void myusec_delay(int usecs);
206void myusec_calibrate_delay(void);
207void internal_delay(int usecs);
208
209#if NEED_PCI == 1
210/* pcidev.c */
211extern uint32_t io_base_addr;
212extern struct pci_access *pacc;
213extern struct pci_dev *pcidev_dev;
214struct pcidev_status {
215 uint16_t vendor_id;
216 uint16_t device_id;
217 int status;
218 const char *vendor_name;
219 const char *device_name;
220};
Carl-Daniel Hailfinger8a19ef12011-02-15 22:44:27 +0000221uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +0000222uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000223/* rpci_write_* are reversible writes. The original PCI config space register
224 * contents will be restored on shutdown.
225 */
Idwer Vollering1a6162e2010-12-26 23:55:19 +0000226int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
227int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
228int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000229#endif
230
231/* print.c */
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000232#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000233void print_supported_pcidevs(const struct pcidev_status *devs);
234#endif
235
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000236#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000237/* board_enable.c */
238void w836xx_ext_enter(uint16_t port);
239void w836xx_ext_leave(uint16_t port);
240int it8705f_write_enable(uint8_t port);
241uint8_t sio_read(uint16_t port, uint8_t reg);
242void sio_write(uint16_t port, uint8_t reg, uint8_t data);
243void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000244void board_handle_before_superio(void);
245void board_handle_before_laptop(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000246int board_flash_enable(const char *vendor, const char *part);
247
248/* chipset_enable.c */
249int chipset_flash_enable(void);
250
251/* processor_enable.c */
252int processor_flash_enable(void);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000253#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000254
255/* physmap.c */
256void *physmap(const char *descr, unsigned long phys_addr, size_t len);
257void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);
258void physunmap(void *virt_addr, size_t len);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000259#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000260int setup_cpu_msr(int cpu);
261void cleanup_cpu_msr(void);
262
263/* cbtable.c */
264void lb_vendor_dev_from_string(char *boardstring);
265int coreboot_init(void);
266extern char *lb_part, *lb_vendor;
267extern int partvendor_from_cbtable;
268
269/* dmi.c */
270extern int has_dmi_support;
271void dmi_init(void);
272int dmi_match(const char *pattern);
273
274/* internal.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000275struct superio {
276 uint16_t vendor;
277 uint16_t port;
278 uint16_t model;
279};
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000280extern struct superio superios[];
281extern int superio_count;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000282#define SUPERIO_VENDOR_NONE 0x0
283#define SUPERIO_VENDOR_ITE 0x1
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000284#endif
285#if NEED_PCI == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000286struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
Uwe Hermann24c35e42011-07-13 11:22:03 +0000287struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000288struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
289struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
290 uint16_t card_vendor, uint16_t card_device);
291#endif
292void get_io_perms(void);
293void release_io_perms(void);
294#if CONFIG_INTERNAL == 1
295extern int is_laptop;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000296extern int laptop_ok;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000297extern int force_boardenable;
298extern int force_boardmismatch;
299void probe_superio(void);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000300int register_superio(struct superio s);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000301extern enum chipbustype internal_buses_supported;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000302int internal_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000303void internal_chip_writeb(uint8_t val, chipaddr addr);
304void internal_chip_writew(uint16_t val, chipaddr addr);
305void internal_chip_writel(uint32_t val, chipaddr addr);
306uint8_t internal_chip_readb(const chipaddr addr);
307uint16_t internal_chip_readw(const chipaddr addr);
308uint32_t internal_chip_readl(const chipaddr addr);
309void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
310#endif
311
312/* hwaccess.c */
313void mmio_writeb(uint8_t val, void *addr);
314void mmio_writew(uint16_t val, void *addr);
315void mmio_writel(uint32_t val, void *addr);
316uint8_t mmio_readb(void *addr);
317uint16_t mmio_readw(void *addr);
318uint32_t mmio_readl(void *addr);
319void mmio_le_writeb(uint8_t val, void *addr);
320void mmio_le_writew(uint16_t val, void *addr);
321void mmio_le_writel(uint32_t val, void *addr);
322uint8_t mmio_le_readb(void *addr);
323uint16_t mmio_le_readw(void *addr);
324uint32_t mmio_le_readl(void *addr);
325#define pci_mmio_writeb mmio_le_writeb
326#define pci_mmio_writew mmio_le_writew
327#define pci_mmio_writel mmio_le_writel
328#define pci_mmio_readb mmio_le_readb
329#define pci_mmio_readw mmio_le_readw
330#define pci_mmio_readl mmio_le_readl
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000331void rmmio_writeb(uint8_t val, void *addr);
332void rmmio_writew(uint16_t val, void *addr);
333void rmmio_writel(uint32_t val, void *addr);
334void rmmio_le_writeb(uint8_t val, void *addr);
335void rmmio_le_writew(uint16_t val, void *addr);
336void rmmio_le_writel(uint32_t val, void *addr);
337#define pci_rmmio_writeb rmmio_le_writeb
338#define pci_rmmio_writew rmmio_le_writew
339#define pci_rmmio_writel rmmio_le_writel
340void rmmio_valb(void *addr);
341void rmmio_valw(void *addr);
342void rmmio_vall(void *addr);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000343
344/* programmer.c */
345int noop_shutdown(void);
346void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);
347void fallback_unmap(void *virt_addr, size_t len);
348uint8_t noop_chip_readb(const chipaddr addr);
349void noop_chip_writeb(uint8_t val, chipaddr addr);
350void fallback_chip_writew(uint16_t val, chipaddr addr);
351void fallback_chip_writel(uint32_t val, chipaddr addr);
352void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
353uint16_t fallback_chip_readw(const chipaddr addr);
354uint32_t fallback_chip_readl(const chipaddr addr);
355void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000356struct par_programmer {
357 void (*chip_writeb) (uint8_t val, chipaddr addr);
358 void (*chip_writew) (uint16_t val, chipaddr addr);
359 void (*chip_writel) (uint32_t val, chipaddr addr);
360 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
361 uint8_t (*chip_readb) (const chipaddr addr);
362 uint16_t (*chip_readw) (const chipaddr addr);
363 uint32_t (*chip_readl) (const chipaddr addr);
364 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
365};
366extern const struct par_programmer *par_programmer;
367void register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000368
369/* dummyflasher.c */
370#if CONFIG_DUMMY == 1
371int dummy_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000372void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);
373void dummy_unmap(void *virt_addr, size_t len);
374void dummy_chip_writeb(uint8_t val, chipaddr addr);
375void dummy_chip_writew(uint16_t val, chipaddr addr);
376void dummy_chip_writel(uint32_t val, chipaddr addr);
377void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
378uint8_t dummy_chip_readb(const chipaddr addr);
379uint16_t dummy_chip_readw(const chipaddr addr);
380uint32_t dummy_chip_readl(const chipaddr addr);
381void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000382#endif
383
384/* nic3com.c */
385#if CONFIG_NIC3COM == 1
386int nic3com_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000387void nic3com_chip_writeb(uint8_t val, chipaddr addr);
388uint8_t nic3com_chip_readb(const chipaddr addr);
389extern const struct pcidev_status nics_3com[];
390#endif
391
392/* gfxnvidia.c */
393#if CONFIG_GFXNVIDIA == 1
394int gfxnvidia_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000395void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr);
396uint8_t gfxnvidia_chip_readb(const chipaddr addr);
397extern const struct pcidev_status gfx_nvidia[];
398#endif
399
400/* drkaiser.c */
401#if CONFIG_DRKAISER == 1
402int drkaiser_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000403void drkaiser_chip_writeb(uint8_t val, chipaddr addr);
404uint8_t drkaiser_chip_readb(const chipaddr addr);
405extern const struct pcidev_status drkaiser_pcidev[];
406#endif
407
408/* nicrealtek.c */
409#if CONFIG_NICREALTEK == 1
410int nicrealtek_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000411void nicrealtek_chip_writeb(uint8_t val, chipaddr addr);
412uint8_t nicrealtek_chip_readb(const chipaddr addr);
413extern const struct pcidev_status nics_realtek[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000414#endif
415
416/* nicnatsemi.c */
417#if CONFIG_NICNATSEMI == 1
418int nicnatsemi_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000419void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr);
420uint8_t nicnatsemi_chip_readb(const chipaddr addr);
421extern const struct pcidev_status nics_natsemi[];
422#endif
423
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000424/* nicintel.c */
425#if CONFIG_NICINTEL == 1
426int nicintel_init(void);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000427void nicintel_chip_writeb(uint8_t val, chipaddr addr);
428uint8_t nicintel_chip_readb(const chipaddr addr);
429extern const struct pcidev_status nics_intel[];
430#endif
431
Idwer Vollering004f4b72010-09-03 18:21:21 +0000432/* nicintel_spi.c */
433#if CONFIG_NICINTEL_SPI == 1
434int nicintel_spi_init(void);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000435extern const struct pcidev_status nics_intel_spi[];
436#endif
437
Mark Marshall90021f22010-12-03 14:48:11 +0000438/* ogp_spi.c */
439#if CONFIG_OGP_SPI == 1
440int ogp_spi_init(void);
Mark Marshall90021f22010-12-03 14:48:11 +0000441extern const struct pcidev_status ogp_spi[];
442#endif
443
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000444/* satamv.c */
445#if CONFIG_SATAMV == 1
446int satamv_init(void);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000447void satamv_chip_writeb(uint8_t val, chipaddr addr);
448uint8_t satamv_chip_readb(const chipaddr addr);
449extern const struct pcidev_status satas_mv[];
450#endif
451
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000452/* satasii.c */
453#if CONFIG_SATASII == 1
454int satasii_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000455void satasii_chip_writeb(uint8_t val, chipaddr addr);
456uint8_t satasii_chip_readb(const chipaddr addr);
457extern const struct pcidev_status satas_sii[];
458#endif
459
460/* atahpt.c */
461#if CONFIG_ATAHPT == 1
462int atahpt_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000463void atahpt_chip_writeb(uint8_t val, chipaddr addr);
464uint8_t atahpt_chip_readb(const chipaddr addr);
465extern const struct pcidev_status ata_hpt[];
466#endif
467
468/* ft2232_spi.c */
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000469#if CONFIG_FT2232_SPI == 1
470struct usbdev_status {
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000471 uint16_t vendor_id;
472 uint16_t device_id;
473 int status;
474 const char *vendor_name;
475 const char *device_name;
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000476};
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000477int ft2232_spi_init(void);
Jörg Fischer6529b9f2010-07-29 15:54:53 +0000478extern const struct usbdev_status devs_ft2232spi[];
479void print_supported_usbdevs(const struct usbdev_status *devs);
480#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000481
482/* rayer_spi.c */
483#if CONFIG_RAYER_SPI == 1
484int rayer_spi_init(void);
485#endif
486
487/* bitbang_spi.c */
488int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod);
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000489int bitbang_spi_shutdown(const struct bitbang_spi_master *master);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000490
491/* buspirate_spi.c */
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000492#if CONFIG_BUSPIRATE_SPI == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000493int buspirate_spi_init(void);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000494#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000495
Sven Schnelle5ce5f702011-09-03 18:37:52 +0000496/* linux_spi.c */
497#if CONFIG_LINUX_SPI == 1
498int linux_spi_init(void);
499#endif
500
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000501/* dediprog.c */
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000502#if CONFIG_DEDIPROG == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000503int dediprog_init(void);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000504#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000505
506/* flashrom.c */
507struct decode_sizes {
508 uint32_t parallel;
509 uint32_t lpc;
510 uint32_t fwh;
511 uint32_t spi;
512};
513extern struct decode_sizes max_rom_decode;
514extern int programmer_may_write;
515extern unsigned long flashbase;
Carl-Daniel Hailfinger4c823182011-05-04 00:39:50 +0000516void check_chip_supported(const struct flashchip *flash);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000517int check_max_decode(enum chipbustype buses, uint32_t size);
Stefan Tauner66652442011-06-26 17:38:17 +0000518char *extract_programmer_param(const char *param_name);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000519
520/* layout.c */
521int show_id(uint8_t *bios, int size, int force);
522
523/* spi.c */
524enum spi_controller {
525 SPI_CONTROLLER_NONE,
526#if CONFIG_INTERNAL == 1
527#if defined(__i386__) || defined(__x86_64__)
528 SPI_CONTROLLER_ICH7,
529 SPI_CONTROLLER_ICH9,
David Hendricks4e748392011-02-28 23:58:15 +0000530 SPI_CONTROLLER_IT85XX,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000531 SPI_CONTROLLER_IT87XX,
532 SPI_CONTROLLER_SB600,
533 SPI_CONTROLLER_VIA,
534 SPI_CONTROLLER_WBSIO,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000535#endif
536#endif
537#if CONFIG_FT2232_SPI == 1
538 SPI_CONTROLLER_FT2232,
539#endif
540#if CONFIG_DUMMY == 1
541 SPI_CONTROLLER_DUMMY,
542#endif
543#if CONFIG_BUSPIRATE_SPI == 1
544 SPI_CONTROLLER_BUSPIRATE,
545#endif
546#if CONFIG_DEDIPROG == 1
547 SPI_CONTROLLER_DEDIPROG,
548#endif
Michael Karcherb9dbe482011-05-11 17:07:07 +0000549#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))
550 SPI_CONTROLLER_BITBANG,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000551#endif
Sven Schnelle5ce5f702011-09-03 18:37:52 +0000552#if CONFIG_LINUX_SPI == 1
553 SPI_CONTROLLER_LINUX,
554#endif
Urja Rannikkoc93f5f12011-09-15 23:38:14 +0000555#if CONFIG_SERPROG == 1
556 SPI_CONTROLLER_SERPROG,
557#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000558};
559extern const int spi_programmer_count;
Michael Karcher62797512011-05-11 17:07:02 +0000560
561#define MAX_DATA_UNSPECIFIED 0
562#define MAX_DATA_READ_UNLIMITED 64 * 1024
563#define MAX_DATA_WRITE_UNLIMITED 256
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000564struct spi_programmer {
Michael Karcherb9dbe482011-05-11 17:07:07 +0000565 enum spi_controller type;
Stefan Tauner8c357452011-09-18 22:42:18 +0000566 int max_data_read;
567 int max_data_write;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000568 int (*command)(unsigned int writecnt, unsigned int readcnt,
569 const unsigned char *writearr, unsigned char *readarr);
570 int (*multicommand)(struct spi_command *cmds);
571
572 /* Optimized functions for this programmer */
Stefan Tauner8c357452011-09-18 22:42:18 +0000573 int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len);
574 int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000575};
576
Michael Karcherb9dbe482011-05-11 17:07:07 +0000577extern const struct spi_programmer *spi_programmer;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000578int default_spi_send_command(unsigned int writecnt, unsigned int readcnt,
579 const unsigned char *writearr, unsigned char *readarr);
580int default_spi_send_multicommand(struct spi_command *cmds);
Stefan Tauner8c357452011-09-18 22:42:18 +0000581int default_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
582int default_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000583void register_spi_programmer(const struct spi_programmer *programmer);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000584
585/* ichspi.c */
586#if CONFIG_INTERNAL == 1
Stefan Taunera8d838d2011-11-06 23:51:09 +0000587enum ich_chipset {
588 CHIPSET_ICH_UNKNOWN,
589 CHIPSET_ICH7 = 7,
590 CHIPSET_ICH8,
591 CHIPSET_ICH9,
592 CHIPSET_ICH10,
593 CHIPSET_5_SERIES_IBEX_PEAK,
594 CHIPSET_6_SERIES_COUGAR_POINT,
595 CHIPSET_7_SERIES_PANTHER_POINT
596};
597
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000598extern uint32_t ichspi_bbar;
599int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
Stefan Taunera8d838d2011-11-06 23:51:09 +0000600 enum ich_chipset ich_generation);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000601int via_init_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000602
David Hendricks4e748392011-02-28 23:58:15 +0000603/* it85spi.c */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000604int it85xx_spi_init(struct superio s);
David Hendricks4e748392011-02-28 23:58:15 +0000605
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000606/* it87spi.c */
607void enter_conf_mode_ite(uint16_t port);
608void exit_conf_mode_ite(uint16_t port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000609void probe_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000610int init_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000611
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000612/* mcp6x_spi.c */
613int mcp6x_spi_init(int want_spi);
614
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000615/* sb600spi.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000616int sb600_probe_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000617
618/* wbsio_spi.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000619int wbsio_check_for_spi(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000620#endif
621
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +0000622/* opaque.c */
623struct opaque_programmer {
624 int max_data_read;
625 int max_data_write;
626 /* Specific functions for this programmer */
627 int (*probe) (struct flashchip *flash);
628 int (*read) (struct flashchip *flash, uint8_t *buf, int start, int len);
629 int (*write) (struct flashchip *flash, uint8_t *buf, int start, int len);
630 int (*erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen);
631};
632extern const struct opaque_programmer *opaque_programmer;
633void register_opaque_programmer(const struct opaque_programmer *pgm);
634
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000635/* serprog.c */
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000636#if CONFIG_SERPROG == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000637int serprog_init(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000638void serprog_chip_writeb(uint8_t val, chipaddr addr);
639uint8_t serprog_chip_readb(const chipaddr addr);
640void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Stefan Tauner31019d42011-10-22 21:45:27 +0000641void serprog_delay(int usecs);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000642#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000643
644/* serial.c */
645#if _WIN32
646typedef HANDLE fdtype;
647#else
648typedef int fdtype;
649#endif
650
651void sp_flush_incoming(void);
652fdtype sp_openserport(char *dev, unsigned int baud);
653void __attribute__((noreturn)) sp_die(char *msg);
654extern fdtype sp_fd;
David Hendricks8bb20212011-06-14 01:35:36 +0000655/* expose serialport_shutdown as it's currently used by buspirate */
656int serialport_shutdown(void *data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000657int serialport_write(unsigned char *buf, unsigned int writecnt);
658int serialport_read(unsigned char *buf, unsigned int readcnt);
659
660#endif /* !__PROGRAMMER_H__ */