Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 5 | * Copyright (C) 2008 coresystems GmbH |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Contains the generic SPI framework |
| 23 | */ |
| 24 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 25 | #include <string.h> |
| 26 | #include "flash.h" |
Carl-Daniel Hailfinger | 0845464 | 2009-06-15 14:14:48 +0000 | [diff] [blame] | 27 | #include "flashchips.h" |
Carl-Daniel Hailfinger | d6cbf76 | 2008-05-13 14:58:23 +0000 | [diff] [blame] | 28 | #include "spi.h" |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 29 | |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 30 | enum spi_controller spi_controller = SPI_CONTROLLER_NONE; |
| 31 | void *spibar = NULL; |
| 32 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 33 | void spi_prettyprint_status_register(struct flashchip *flash); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 34 | |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 35 | const struct spi_programmer spi_programmer[] = { |
| 36 | { /* SPI_CONTROLLER_NONE */ |
| 37 | .command = NULL, |
| 38 | .multicommand = NULL, |
| 39 | .read = NULL, |
| 40 | .write_256 = NULL, |
| 41 | }, |
| 42 | |
Carl-Daniel Hailfinger | 66ef4e5 | 2009-12-13 22:28:00 +0000 | [diff] [blame] | 43 | #if INTERNAL_SUPPORT == 1 |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 44 | { /* SPI_CONTROLLER_ICH7 */ |
| 45 | .command = ich_spi_send_command, |
| 46 | .multicommand = ich_spi_send_multicommand, |
| 47 | .read = ich_spi_read, |
| 48 | .write_256 = ich_spi_write_256, |
| 49 | }, |
| 50 | |
| 51 | { /* SPI_CONTROLLER_ICH9 */ |
| 52 | .command = ich_spi_send_command, |
| 53 | .multicommand = ich_spi_send_multicommand, |
| 54 | .read = ich_spi_read, |
| 55 | .write_256 = ich_spi_write_256, |
| 56 | }, |
| 57 | |
| 58 | { /* SPI_CONTROLLER_IT87XX */ |
| 59 | .command = it8716f_spi_send_command, |
| 60 | .multicommand = default_spi_send_multicommand, |
| 61 | .read = it8716f_spi_chip_read, |
| 62 | .write_256 = it8716f_spi_chip_write_256, |
| 63 | }, |
| 64 | |
| 65 | { /* SPI_CONTROLLER_SB600 */ |
| 66 | .command = sb600_spi_send_command, |
| 67 | .multicommand = default_spi_send_multicommand, |
| 68 | .read = sb600_spi_read, |
| 69 | .write_256 = sb600_spi_write_1, |
| 70 | }, |
| 71 | |
| 72 | { /* SPI_CONTROLLER_VIA */ |
| 73 | .command = ich_spi_send_command, |
| 74 | .multicommand = ich_spi_send_multicommand, |
| 75 | .read = ich_spi_read, |
| 76 | .write_256 = ich_spi_write_256, |
| 77 | }, |
| 78 | |
| 79 | { /* SPI_CONTROLLER_WBSIO */ |
| 80 | .command = wbsio_spi_send_command, |
| 81 | .multicommand = default_spi_send_multicommand, |
| 82 | .read = wbsio_spi_read, |
| 83 | .write_256 = wbsio_spi_write_1, |
| 84 | }, |
Carl-Daniel Hailfinger | 66ef4e5 | 2009-12-13 22:28:00 +0000 | [diff] [blame] | 85 | #endif |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 86 | |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 87 | #if FT2232_SPI_SUPPORT == 1 |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 88 | { /* SPI_CONTROLLER_FT2232 */ |
| 89 | .command = ft2232_spi_send_command, |
| 90 | .multicommand = default_spi_send_multicommand, |
| 91 | .read = ft2232_spi_read, |
| 92 | .write_256 = ft2232_spi_write_256, |
| 93 | }, |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 94 | #endif |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 95 | |
Carl-Daniel Hailfinger | 4740c6f | 2009-09-16 10:09:21 +0000 | [diff] [blame] | 96 | #if DUMMY_SUPPORT == 1 |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 97 | { /* SPI_CONTROLLER_DUMMY */ |
| 98 | .command = dummy_spi_send_command, |
| 99 | .multicommand = default_spi_send_multicommand, |
| 100 | .read = NULL, |
| 101 | .write_256 = NULL, |
| 102 | }, |
Carl-Daniel Hailfinger | 4740c6f | 2009-09-16 10:09:21 +0000 | [diff] [blame] | 103 | #endif |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 104 | |
Carl-Daniel Hailfinger | 5cca01f | 2009-11-24 00:20:03 +0000 | [diff] [blame] | 105 | #if BUSPIRATE_SPI_SUPPORT == 1 |
| 106 | { /* SPI_CONTROLLER_BUSPIRATE */ |
| 107 | .command = buspirate_spi_send_command, |
| 108 | .multicommand = default_spi_send_multicommand, |
| 109 | .read = buspirate_spi_read, |
| 110 | .write_256 = spi_chip_write_1, |
| 111 | }, |
| 112 | #endif |
| 113 | |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 114 | {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 115 | }; |
| 116 | |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 117 | const int spi_programmer_count = ARRAY_SIZE(spi_programmer); |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 118 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 119 | int spi_send_command(unsigned int writecnt, unsigned int readcnt, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 120 | const unsigned char *writearr, unsigned char *readarr) |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 121 | { |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 122 | if (!spi_programmer[spi_controller].command) { |
| 123 | fprintf(stderr, "%s called, but SPI is unsupported on this " |
| 124 | "hardware. Please report a bug.\n", __func__); |
| 125 | return 1; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 126 | } |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 127 | |
| 128 | return spi_programmer[spi_controller].command(writecnt, readcnt, |
| 129 | writearr, readarr); |
Carl-Daniel Hailfinger | 3d94a0e | 2007-10-16 21:09:06 +0000 | [diff] [blame] | 130 | } |
| 131 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 132 | int spi_send_multicommand(struct spi_command *cmds) |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 133 | { |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 134 | if (!spi_programmer[spi_controller].multicommand) { |
| 135 | fprintf(stderr, "%s called, but SPI is unsupported on this " |
| 136 | "hardware. Please report a bug.\n", __func__); |
| 137 | return 1; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 138 | } |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 139 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 140 | return spi_programmer[spi_controller].multicommand(cmds); |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, |
| 144 | const unsigned char *writearr, unsigned char *readarr) |
| 145 | { |
| 146 | struct spi_command cmd[] = { |
| 147 | { |
| 148 | .writecnt = writecnt, |
| 149 | .readcnt = readcnt, |
| 150 | .writearr = writearr, |
| 151 | .readarr = readarr, |
| 152 | }, { |
| 153 | .writecnt = 0, |
| 154 | .writearr = NULL, |
| 155 | .readcnt = 0, |
| 156 | .readarr = NULL, |
| 157 | }}; |
| 158 | |
| 159 | return spi_send_multicommand(cmd); |
| 160 | } |
| 161 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 162 | int default_spi_send_multicommand(struct spi_command *cmds) |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 163 | { |
| 164 | int result = 0; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 165 | for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { |
| 166 | result = spi_send_command(cmds->writecnt, cmds->readcnt, |
| 167 | cmds->writearr, cmds->readarr); |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 168 | } |
| 169 | return result; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 170 | } |
| 171 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 172 | static int spi_rdid(unsigned char *readarr, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 173 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 174 | const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 175 | int ret; |
Carl-Daniel Hailfinger | bfe2e0c | 2009-05-14 12:59:36 +0000 | [diff] [blame] | 176 | int i; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 177 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 178 | ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 179 | if (ret) |
| 180 | return ret; |
Carl-Daniel Hailfinger | bfe2e0c | 2009-05-14 12:59:36 +0000 | [diff] [blame] | 181 | printf_debug("RDID returned"); |
| 182 | for (i = 0; i < bytes; i++) |
| 183 | printf_debug(" 0x%02x", readarr[i]); |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 184 | printf_debug(". "); |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 185 | return 0; |
| 186 | } |
| 187 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 188 | static int spi_rems(unsigned char *readarr) |
| 189 | { |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 190 | unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; |
| 191 | uint32_t readaddr; |
| 192 | int ret; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 193 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 194 | ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 195 | if (ret == SPI_INVALID_ADDRESS) { |
| 196 | /* Find the lowest even address allowed for reads. */ |
| 197 | readaddr = (spi_get_valid_read_addr() + 1) & ~1; |
| 198 | cmd[1] = (readaddr >> 16) & 0xff, |
| 199 | cmd[2] = (readaddr >> 8) & 0xff, |
| 200 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 201 | ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 202 | } |
| 203 | if (ret) |
| 204 | return ret; |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 205 | printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]); |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 206 | return 0; |
| 207 | } |
| 208 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 209 | static int spi_res(unsigned char *readarr) |
| 210 | { |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 211 | unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; |
| 212 | uint32_t readaddr; |
| 213 | int ret; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 214 | |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 215 | ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 216 | if (ret == SPI_INVALID_ADDRESS) { |
| 217 | /* Find the lowest even address allowed for reads. */ |
| 218 | readaddr = (spi_get_valid_read_addr() + 1) & ~1; |
| 219 | cmd[1] = (readaddr >> 16) & 0xff, |
| 220 | cmd[2] = (readaddr >> 8) & 0xff, |
| 221 | cmd[3] = (readaddr >> 0) & 0xff, |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 222 | ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 223 | } |
| 224 | if (ret) |
| 225 | return ret; |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 226 | printf_debug("RES returned %02x. ", readarr[0]); |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 227 | return 0; |
| 228 | } |
| 229 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 230 | int spi_write_enable(void) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 231 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 232 | const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 233 | int result; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 234 | |
| 235 | /* Send WREN (Write Enable) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 236 | result = spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 237 | |
| 238 | if (result) |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 239 | fprintf(stderr, "%s failed\n", __func__); |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 240 | |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 241 | return result; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 242 | } |
| 243 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 244 | int spi_write_disable(void) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 245 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 246 | const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 247 | |
| 248 | /* Send WRDI (Write Disable) */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 249 | return spi_send_command(sizeof(cmd), 0, cmd, NULL); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 250 | } |
| 251 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 252 | static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 253 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 254 | unsigned char readarr[4]; |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 255 | uint32_t id1; |
| 256 | uint32_t id2; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 257 | |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 258 | if (spi_rdid(readarr, bytes)) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 259 | return 0; |
| 260 | |
| 261 | if (!oddparity(readarr[0])) |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 262 | printf_debug("RDID byte 0 parity violation. "); |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 263 | |
| 264 | /* Check if this is a continuation vendor ID */ |
| 265 | if (readarr[0] == 0x7f) { |
| 266 | if (!oddparity(readarr[1])) |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 267 | printf_debug("RDID byte 1 parity violation. "); |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 268 | id1 = (readarr[0] << 8) | readarr[1]; |
| 269 | id2 = readarr[2]; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 270 | if (bytes > 3) { |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 271 | id2 <<= 8; |
| 272 | id2 |= readarr[3]; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 273 | } |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 274 | } else { |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 275 | id1 = readarr[0]; |
| 276 | id2 = (readarr[1] << 8) | readarr[2]; |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 277 | } |
| 278 | |
Uwe Hermann | 04aa59a | 2009-09-02 22:09:00 +0000 | [diff] [blame] | 279 | printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 280 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 281 | if (id1 == flash->manufacture_id && id2 == flash->model_id) { |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 282 | /* Print the status register to tell the |
| 283 | * user about possible write protection. |
| 284 | */ |
| 285 | spi_prettyprint_status_register(flash); |
| 286 | |
| 287 | return 1; |
| 288 | } |
| 289 | |
| 290 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 291 | if (id1 == flash->manufacture_id && |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 292 | GENERIC_DEVICE_ID == flash->model_id) |
| 293 | return 1; |
| 294 | |
Carl-Daniel Hailfinger | 01d49ed | 2009-11-20 01:12:45 +0000 | [diff] [blame] | 295 | /* Test if there is any vendor ID. */ |
| 296 | if (GENERIC_MANUF_ID == flash->manufacture_id && |
| 297 | id1 != 0xff) |
| 298 | return 1; |
| 299 | |
Carl-Daniel Hailfinger | 7053926 | 2007-10-15 21:45:29 +0000 | [diff] [blame] | 300 | return 0; |
| 301 | } |
| 302 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 303 | int probe_spi_rdid(struct flashchip *flash) |
| 304 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 305 | return probe_spi_rdid_generic(flash, 3); |
| 306 | } |
| 307 | |
| 308 | /* support 4 bytes flash ID */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 309 | int probe_spi_rdid4(struct flashchip *flash) |
| 310 | { |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 311 | /* only some SPI chipsets support 4 bytes commands */ |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 312 | switch (spi_controller) { |
Carl-Daniel Hailfinger | 66ef4e5 | 2009-12-13 22:28:00 +0000 | [diff] [blame] | 313 | #if INTERNAL_SUPPORT == 1 |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 314 | case SPI_CONTROLLER_ICH7: |
| 315 | case SPI_CONTROLLER_ICH9: |
| 316 | case SPI_CONTROLLER_VIA: |
| 317 | case SPI_CONTROLLER_SB600: |
| 318 | case SPI_CONTROLLER_WBSIO: |
Carl-Daniel Hailfinger | 66ef4e5 | 2009-12-13 22:28:00 +0000 | [diff] [blame] | 319 | #endif |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 320 | #if FT2232_SPI_SUPPORT == 1 |
Paul Fox | 05dfbe6 | 2009-06-16 21:08:06 +0000 | [diff] [blame] | 321 | case SPI_CONTROLLER_FT2232: |
Carl-Daniel Hailfinger | 3426ef6 | 2009-08-19 13:27:58 +0000 | [diff] [blame] | 322 | #endif |
Carl-Daniel Hailfinger | 4740c6f | 2009-09-16 10:09:21 +0000 | [diff] [blame] | 323 | #if DUMMY_SUPPORT == 1 |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 324 | case SPI_CONTROLLER_DUMMY: |
Carl-Daniel Hailfinger | 4740c6f | 2009-09-16 10:09:21 +0000 | [diff] [blame] | 325 | #endif |
Carl-Daniel Hailfinger | d5b28fa | 2009-11-24 18:27:10 +0000 | [diff] [blame] | 326 | #if BUSPIRATE_SPI_SUPPORT == 1 |
| 327 | case SPI_CONTROLLER_BUSPIRATE: |
| 328 | #endif |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 329 | return probe_spi_rdid_generic(flash, 4); |
| 330 | default: |
| 331 | printf_debug("4b ID not supported on this SPI controller\n"); |
| 332 | } |
| 333 | |
| 334 | return 0; |
Rudolf Marek | 48a85e4 | 2008-06-30 21:45:17 +0000 | [diff] [blame] | 335 | } |
| 336 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 337 | int probe_spi_rems(struct flashchip *flash) |
| 338 | { |
| 339 | unsigned char readarr[JEDEC_REMS_INSIZE]; |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 340 | uint32_t id1, id2; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 341 | |
| 342 | if (spi_rems(readarr)) |
| 343 | return 0; |
| 344 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 345 | id1 = readarr[0]; |
| 346 | id2 = readarr[1]; |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 347 | |
Uwe Hermann | 04aa59a | 2009-09-02 22:09:00 +0000 | [diff] [blame] | 348 | printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 349 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 350 | if (id1 == flash->manufacture_id && id2 == flash->model_id) { |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 351 | /* Print the status register to tell the |
| 352 | * user about possible write protection. |
| 353 | */ |
| 354 | spi_prettyprint_status_register(flash); |
| 355 | |
| 356 | return 1; |
| 357 | } |
| 358 | |
| 359 | /* Test if this is a pure vendor match. */ |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 360 | if (id1 == flash->manufacture_id && |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 361 | GENERIC_DEVICE_ID == flash->model_id) |
| 362 | return 1; |
| 363 | |
Carl-Daniel Hailfinger | 01d49ed | 2009-11-20 01:12:45 +0000 | [diff] [blame] | 364 | /* Test if there is any vendor ID. */ |
| 365 | if (GENERIC_MANUF_ID == flash->manufacture_id && |
| 366 | id1 != 0xff) |
| 367 | return 1; |
| 368 | |
Carl-Daniel Hailfinger | 14e50ac | 2008-11-28 01:25:00 +0000 | [diff] [blame] | 369 | return 0; |
| 370 | } |
| 371 | |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 372 | int probe_spi_res(struct flashchip *flash) |
| 373 | { |
| 374 | unsigned char readarr[3]; |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 375 | uint32_t id2; |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 376 | |
Carl-Daniel Hailfinger | 92a54ca | 2008-11-27 22:48:48 +0000 | [diff] [blame] | 377 | /* Check if RDID was successful and did not return 0xff 0xff 0xff. |
| 378 | * In that case, RES is pointless. |
| 379 | */ |
| 380 | if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) || |
| 381 | (readarr[1] != 0xff) || (readarr[2] != 0xff))) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 382 | return 0; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 383 | |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 384 | if (spi_res(readarr)) |
| 385 | return 0; |
| 386 | |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 387 | id2 = readarr[0]; |
Uwe Hermann | 04aa59a | 2009-09-02 22:09:00 +0000 | [diff] [blame] | 388 | printf_debug("%s: id 0x%x\n", __func__, id2); |
Carl-Daniel Hailfinger | 2ad267d | 2009-05-27 11:40:08 +0000 | [diff] [blame] | 389 | if (id2 != flash->model_id) |
Peter Stuge | da4e5f3 | 2008-06-24 01:22:03 +0000 | [diff] [blame] | 390 | return 0; |
| 391 | |
| 392 | /* Print the status register to tell the |
| 393 | * user about possible write protection. |
| 394 | */ |
| 395 | spi_prettyprint_status_register(flash); |
| 396 | return 1; |
Carl-Daniel Hailfinger | 42c5497 | 2008-05-15 03:19:49 +0000 | [diff] [blame] | 397 | } |
| 398 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 399 | uint8_t spi_read_status_register(void) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 400 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 401 | const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR }; |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 402 | /* FIXME: No workarounds for driver/hardware bugs in generic code. */ |
Peter Stuge | bf196e9 | 2009-01-26 03:08:45 +0000 | [diff] [blame] | 403 | unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 404 | int ret; |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 405 | |
| 406 | /* Read Status Register */ |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 407 | ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); |
| 408 | if (ret) |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 409 | fprintf(stderr, "RDSR failed!\n"); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 410 | |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 411 | return readarr[0]; |
| 412 | } |
| 413 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 414 | /* Prettyprint the status register. Common definitions. */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 415 | void spi_prettyprint_status_register_common(uint8_t status) |
| 416 | { |
| 417 | printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 418 | "%sset\n", (status & (1 << 5)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 419 | printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 420 | "%sset\n", (status & (1 << 4)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 421 | printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 422 | "%sset\n", (status & (1 << 3)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 423 | printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 424 | "%sset\n", (status & (1 << 2)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 425 | printf_debug("Chip status register: Write Enable Latch (WEL) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 426 | "%sset\n", (status & (1 << 1)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 427 | printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 428 | "%sset\n", (status & (1 << 0)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 429 | } |
| 430 | |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 431 | /* Prettyprint the status register. Works for |
| 432 | * ST M25P series |
| 433 | * MX MX25L series |
| 434 | */ |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 435 | void spi_prettyprint_status_register_st_m25p(uint8_t status) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 436 | { |
| 437 | printf_debug("Chip status register: Status Register Write Disable " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 438 | "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 439 | printf_debug("Chip status register: Bit 6 is " |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 440 | "%sset\n", (status & (1 << 6)) ? "" : "not "); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 441 | spi_prettyprint_status_register_common(status); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 442 | } |
| 443 | |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 444 | void spi_prettyprint_status_register_sst25(uint8_t status) |
| 445 | { |
| 446 | printf_debug("Chip status register: Block Protect Write Disable " |
| 447 | "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); |
| 448 | printf_debug("Chip status register: Auto Address Increment Programming " |
| 449 | "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); |
| 450 | spi_prettyprint_status_register_common(status); |
| 451 | } |
| 452 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 453 | /* Prettyprint the status register. Works for |
| 454 | * SST 25VF016 |
| 455 | */ |
| 456 | void spi_prettyprint_status_register_sst25vf016(uint8_t status) |
| 457 | { |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 458 | const char *bpt[] = { |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 459 | "none", |
| 460 | "1F0000H-1FFFFFH", |
| 461 | "1E0000H-1FFFFFH", |
| 462 | "1C0000H-1FFFFFH", |
| 463 | "180000H-1FFFFFH", |
| 464 | "100000H-1FFFFFH", |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 465 | "all", "all" |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 466 | }; |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 467 | spi_prettyprint_status_register_sst25(status); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 468 | printf_debug("Resulting block protection : %s\n", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 469 | bpt[(status & 0x1c) >> 2]); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 470 | } |
| 471 | |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 472 | void spi_prettyprint_status_register_sst25vf040b(uint8_t status) |
| 473 | { |
| 474 | const char *bpt[] = { |
| 475 | "none", |
| 476 | "0x70000-0x7ffff", |
| 477 | "0x60000-0x7ffff", |
| 478 | "0x40000-0x7ffff", |
| 479 | "all blocks", "all blocks", "all blocks", "all blocks" |
| 480 | }; |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 481 | spi_prettyprint_status_register_sst25(status); |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 482 | printf_debug("Resulting block protection : %s\n", |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 483 | bpt[(status & 0x1c) >> 2]); |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 484 | } |
| 485 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 486 | void spi_prettyprint_status_register(struct flashchip *flash) |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 487 | { |
| 488 | uint8_t status; |
| 489 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 490 | status = spi_read_status_register(); |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 491 | printf_debug("Chip status register is %02x\n", status); |
| 492 | switch (flash->manufacture_id) { |
| 493 | case ST_ID: |
Carl-Daniel Hailfinger | f43e642 | 2008-05-15 22:32:08 +0000 | [diff] [blame] | 494 | if (((flash->model_id & 0xff00) == 0x2000) || |
| 495 | ((flash->model_id & 0xff00) == 0x2500)) |
| 496 | spi_prettyprint_status_register_st_m25p(status); |
| 497 | break; |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 498 | case MX_ID: |
| 499 | if ((flash->model_id & 0xff00) == 0x2000) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 500 | spi_prettyprint_status_register_st_m25p(status); |
| 501 | break; |
| 502 | case SST_ID: |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 503 | switch (flash->model_id) { |
| 504 | case 0x2541: |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 505 | spi_prettyprint_status_register_sst25vf016(status); |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 506 | break; |
| 507 | case 0x8d: |
| 508 | case 0x258d: |
| 509 | spi_prettyprint_status_register_sst25vf040b(status); |
| 510 | break; |
Carl-Daniel Hailfinger | 5100a8a | 2009-05-13 22:51:27 +0000 | [diff] [blame] | 511 | default: |
Carl-Daniel Hailfinger | 1bfd6c9 | 2009-05-06 13:59:44 +0000 | [diff] [blame] | 512 | spi_prettyprint_status_register_sst25(status); |
| 513 | break; |
Peter Stuge | 5fecee4 | 2009-01-26 03:23:50 +0000 | [diff] [blame] | 514 | } |
Carl-Daniel Hailfinger | 9a3ec82 | 2007-12-29 10:15:58 +0000 | [diff] [blame] | 515 | break; |
| 516 | } |
| 517 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 518 | |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 519 | int spi_chip_erase_60(struct flashchip *flash) |
| 520 | { |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 521 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 522 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 523 | { |
| 524 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 525 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 526 | .readcnt = 0, |
| 527 | .readarr = NULL, |
| 528 | }, { |
| 529 | .writecnt = JEDEC_CE_60_OUTSIZE, |
| 530 | .writearr = (const unsigned char[]){ JEDEC_CE_60 }, |
| 531 | .readcnt = 0, |
| 532 | .readarr = NULL, |
| 533 | }, { |
| 534 | .writecnt = 0, |
| 535 | .writearr = NULL, |
| 536 | .readcnt = 0, |
| 537 | .readarr = NULL, |
| 538 | }}; |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 539 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 540 | result = spi_disable_blockprotect(); |
| 541 | if (result) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 542 | fprintf(stderr, "spi_disable_blockprotect failed\n"); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 543 | return result; |
| 544 | } |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 545 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 546 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 547 | if (result) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 548 | fprintf(stderr, "%s failed during command execution\n", |
| 549 | __func__); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 550 | return result; |
| 551 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 552 | /* Wait until the Write-In-Progress bit is cleared. |
| 553 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 554 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 555 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 556 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 557 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 558 | if (check_erased_range(flash, 0, flash->total_size * 1024)) { |
| 559 | fprintf(stderr, "ERASE FAILED!\n"); |
| 560 | return -1; |
| 561 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 562 | return 0; |
| 563 | } |
| 564 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 565 | int spi_chip_erase_c7(struct flashchip *flash) |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 566 | { |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 567 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 568 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 569 | { |
| 570 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 571 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 572 | .readcnt = 0, |
| 573 | .readarr = NULL, |
| 574 | }, { |
| 575 | .writecnt = JEDEC_CE_C7_OUTSIZE, |
| 576 | .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, |
| 577 | .readcnt = 0, |
| 578 | .readarr = NULL, |
| 579 | }, { |
| 580 | .writecnt = 0, |
| 581 | .writearr = NULL, |
| 582 | .readcnt = 0, |
| 583 | .readarr = NULL, |
| 584 | }}; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 585 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 586 | result = spi_disable_blockprotect(); |
| 587 | if (result) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 588 | fprintf(stderr, "spi_disable_blockprotect failed\n"); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 589 | return result; |
| 590 | } |
Carl-Daniel Hailfinger | 60d7118 | 2009-07-11 19:28:36 +0000 | [diff] [blame] | 591 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 592 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 593 | if (result) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 594 | fprintf(stderr, "%s failed during command execution\n", __func__); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 595 | return result; |
| 596 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 597 | /* Wait until the Write-In-Progress bit is cleared. |
| 598 | * This usually takes 1-85 s, so wait in 1 s steps. |
| 599 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 600 | /* FIXME: We assume spi_read_status_register will never fail. */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 601 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 602 | programmer_delay(1000 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 603 | if (check_erased_range(flash, 0, flash->total_size * 1024)) { |
| 604 | fprintf(stderr, "ERASE FAILED!\n"); |
| 605 | return -1; |
| 606 | } |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 607 | return 0; |
| 608 | } |
| 609 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 610 | int spi_chip_erase_60_c7(struct flashchip *flash) |
| 611 | { |
| 612 | int result; |
| 613 | result = spi_chip_erase_60(flash); |
| 614 | if (result) { |
| 615 | printf_debug("spi_chip_erase_60 failed, trying c7\n"); |
| 616 | result = spi_chip_erase_c7(flash); |
| 617 | } |
| 618 | return result; |
| 619 | } |
| 620 | |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 621 | int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 622 | { |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 623 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 624 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 625 | { |
| 626 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 627 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 628 | .readcnt = 0, |
| 629 | .readarr = NULL, |
| 630 | }, { |
| 631 | .writecnt = JEDEC_BE_52_OUTSIZE, |
| 632 | .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, |
| 633 | .readcnt = 0, |
| 634 | .readarr = NULL, |
| 635 | }, { |
| 636 | .writecnt = 0, |
| 637 | .writearr = NULL, |
| 638 | .readcnt = 0, |
| 639 | .readarr = NULL, |
| 640 | }}; |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 641 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 642 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 643 | if (result) { |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 644 | fprintf(stderr, "%s failed during command execution at address 0x%x\n", |
| 645 | __func__, addr); |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 646 | return result; |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 647 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 648 | /* Wait until the Write-In-Progress bit is cleared. |
| 649 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 650 | */ |
| 651 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 652 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 653 | if (check_erased_range(flash, addr, blocklen)) { |
| 654 | fprintf(stderr, "ERASE FAILED!\n"); |
| 655 | return -1; |
| 656 | } |
Carl-Daniel Hailfinger | 6afb613 | 2008-11-03 00:02:11 +0000 | [diff] [blame] | 657 | return 0; |
| 658 | } |
| 659 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 660 | /* Block size is usually |
| 661 | * 64k for Macronix |
| 662 | * 32k for SST |
| 663 | * 4-32k non-uniform for EON |
| 664 | */ |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 665 | int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 666 | { |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 667 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 668 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 669 | { |
| 670 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 671 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 672 | .readcnt = 0, |
| 673 | .readarr = NULL, |
| 674 | }, { |
| 675 | .writecnt = JEDEC_BE_D8_OUTSIZE, |
| 676 | .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, |
| 677 | .readcnt = 0, |
| 678 | .readarr = NULL, |
| 679 | }, { |
| 680 | .writecnt = 0, |
| 681 | .writearr = NULL, |
| 682 | .readcnt = 0, |
| 683 | .readarr = NULL, |
| 684 | }}; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 685 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 686 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 687 | if (result) { |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 688 | fprintf(stderr, "%s failed during command execution at address 0x%x\n", |
| 689 | __func__, addr); |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 690 | return result; |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 691 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 692 | /* Wait until the Write-In-Progress bit is cleared. |
| 693 | * This usually takes 100-4000 ms, so wait in 100 ms steps. |
| 694 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 695 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 696 | programmer_delay(100 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 697 | if (check_erased_range(flash, addr, blocklen)) { |
| 698 | fprintf(stderr, "ERASE FAILED!\n"); |
| 699 | return -1; |
| 700 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 701 | return 0; |
| 702 | } |
| 703 | |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 704 | int spi_chip_erase_d8(struct flashchip *flash) |
| 705 | { |
| 706 | int i, rc = 0; |
| 707 | int total_size = flash->total_size * 1024; |
| 708 | int erase_size = 64 * 1024; |
| 709 | |
| 710 | spi_disable_blockprotect(); |
| 711 | |
| 712 | printf("Erasing chip: \n"); |
| 713 | |
| 714 | for (i = 0; i < total_size / erase_size; i++) { |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 715 | rc = spi_block_erase_d8(flash, i * erase_size, erase_size); |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 716 | if (rc) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 717 | fprintf(stderr, "Error erasing block at 0x%x\n", i); |
Stefan Reinauer | 424ed22 | 2008-10-29 22:13:20 +0000 | [diff] [blame] | 718 | break; |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | printf("\n"); |
| 723 | |
| 724 | return rc; |
| 725 | } |
| 726 | |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 727 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */ |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 728 | int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 729 | { |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 730 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 731 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 732 | { |
| 733 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 734 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 735 | .readcnt = 0, |
| 736 | .readarr = NULL, |
| 737 | }, { |
| 738 | .writecnt = JEDEC_SE_OUTSIZE, |
| 739 | .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) }, |
| 740 | .readcnt = 0, |
| 741 | .readarr = NULL, |
| 742 | }, { |
| 743 | .writecnt = 0, |
| 744 | .writearr = NULL, |
| 745 | .readcnt = 0, |
| 746 | .readarr = NULL, |
| 747 | }}; |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 748 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 749 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 750 | if (result) { |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 751 | fprintf(stderr, "%s failed during command execution at address 0x%x\n", |
| 752 | __func__, addr); |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 753 | return result; |
Carl-Daniel Hailfinger | 39fa9b5 | 2009-07-11 22:26:52 +0000 | [diff] [blame] | 754 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 755 | /* Wait until the Write-In-Progress bit is cleared. |
| 756 | * This usually takes 15-800 ms, so wait in 10 ms steps. |
| 757 | */ |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 758 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 759 | programmer_delay(10 * 1000); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 760 | if (check_erased_range(flash, addr, blocklen)) { |
| 761 | fprintf(stderr, "ERASE FAILED!\n"); |
| 762 | return -1; |
| 763 | } |
Carl-Daniel Hailfinger | 5b1c6ed | 2007-10-22 16:15:28 +0000 | [diff] [blame] | 764 | return 0; |
| 765 | } |
| 766 | |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 767 | int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
| 768 | { |
| 769 | if ((addr != 0) || (blocklen != flash->total_size * 1024)) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 770 | fprintf(stderr, "%s called with incorrect arguments\n", |
| 771 | __func__); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 772 | return -1; |
| 773 | } |
| 774 | return spi_chip_erase_60(flash); |
| 775 | } |
| 776 | |
| 777 | int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) |
| 778 | { |
| 779 | if ((addr != 0) || (blocklen != flash->total_size * 1024)) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 780 | fprintf(stderr, "%s called with incorrect arguments\n", |
| 781 | __func__); |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 782 | return -1; |
| 783 | } |
| 784 | return spi_chip_erase_c7(flash); |
| 785 | } |
| 786 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 787 | int spi_write_status_enable(void) |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 788 | { |
| 789 | const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 790 | int result; |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 791 | |
| 792 | /* Send EWSR (Enable Write Status Register). */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 793 | result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 794 | |
| 795 | if (result) |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 796 | fprintf(stderr, "%s failed\n", __func__); |
Carl-Daniel Hailfinger | 1e63784 | 2009-05-15 00:56:22 +0000 | [diff] [blame] | 797 | |
| 798 | return result; |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 799 | } |
| 800 | |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 801 | /* |
| 802 | * This is according the SST25VF016 datasheet, who knows it is more |
| 803 | * generic that this... |
| 804 | */ |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 805 | int spi_write_status_register(int status) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 806 | { |
Carl-Daniel Hailfinger | fcbdbbc | 2009-07-22 20:09:28 +0000 | [diff] [blame] | 807 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 808 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | fcbdbbc | 2009-07-22 20:09:28 +0000 | [diff] [blame] | 809 | { |
Carl-Daniel Hailfinger | db53ec5 | 2009-12-22 23:54:10 +0000 | [diff] [blame] | 810 | /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ |
Carl-Daniel Hailfinger | fcbdbbc | 2009-07-22 20:09:28 +0000 | [diff] [blame] | 811 | .writecnt = JEDEC_EWSR_OUTSIZE, |
| 812 | .writearr = (const unsigned char[]){ JEDEC_EWSR }, |
| 813 | .readcnt = 0, |
| 814 | .readarr = NULL, |
| 815 | }, { |
| 816 | .writecnt = JEDEC_WRSR_OUTSIZE, |
| 817 | .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status }, |
| 818 | .readcnt = 0, |
| 819 | .readarr = NULL, |
| 820 | }, { |
| 821 | .writecnt = 0, |
| 822 | .writearr = NULL, |
| 823 | .readcnt = 0, |
| 824 | .readarr = NULL, |
| 825 | }}; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 826 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 827 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | fcbdbbc | 2009-07-22 20:09:28 +0000 | [diff] [blame] | 828 | if (result) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 829 | fprintf(stderr, "%s failed during command execution\n", |
| 830 | __func__); |
Carl-Daniel Hailfinger | fcbdbbc | 2009-07-22 20:09:28 +0000 | [diff] [blame] | 831 | } |
| 832 | return result; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 833 | } |
| 834 | |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 835 | int spi_byte_program(int addr, uint8_t byte) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 836 | { |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 837 | int result; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 838 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 839 | { |
| 840 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 841 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 842 | .readcnt = 0, |
| 843 | .readarr = NULL, |
| 844 | }, { |
| 845 | .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, |
| 846 | .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), byte }, |
| 847 | .readcnt = 0, |
| 848 | .readarr = NULL, |
| 849 | }, { |
| 850 | .writecnt = 0, |
| 851 | .writearr = NULL, |
| 852 | .readcnt = 0, |
| 853 | .readarr = NULL, |
| 854 | }}; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 855 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 856 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 857 | if (result) { |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 858 | fprintf(stderr, "%s failed during command execution at address 0x%x\n", |
| 859 | __func__, addr); |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 860 | } |
| 861 | return result; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 862 | } |
| 863 | |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 864 | int spi_nbyte_program(int addr, uint8_t *bytes, int len) |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 865 | { |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 866 | int result; |
| 867 | /* FIXME: Switch to malloc based on len unless that kills speed. */ |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 868 | unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { |
| 869 | JEDEC_BYTE_PROGRAM, |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 870 | (addr >> 16) & 0xff, |
| 871 | (addr >> 8) & 0xff, |
| 872 | (addr >> 0) & 0xff, |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 873 | }; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 874 | struct spi_command cmds[] = { |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 875 | { |
| 876 | .writecnt = JEDEC_WREN_OUTSIZE, |
| 877 | .writearr = (const unsigned char[]){ JEDEC_WREN }, |
| 878 | .readcnt = 0, |
| 879 | .readarr = NULL, |
| 880 | }, { |
| 881 | .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, |
| 882 | .writearr = cmd, |
| 883 | .readcnt = 0, |
| 884 | .readarr = NULL, |
| 885 | }, { |
| 886 | .writecnt = 0, |
| 887 | .writearr = NULL, |
| 888 | .readcnt = 0, |
| 889 | .readarr = NULL, |
| 890 | }}; |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 891 | |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 892 | if (!len) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 893 | fprintf(stderr, "%s called for zero-length write\n", __func__); |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 894 | return 1; |
| 895 | } |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 896 | if (len > 256) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 897 | fprintf(stderr, "%s called for too long a write\n", __func__); |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 898 | return 1; |
| 899 | } |
| 900 | |
| 901 | memcpy(&cmd[4], bytes, len); |
| 902 | |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 903 | result = spi_send_multicommand(cmds); |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 904 | if (result) { |
Carl-Daniel Hailfinger | 3efc51c | 2009-11-16 15:03:35 +0000 | [diff] [blame] | 905 | fprintf(stderr, "%s failed during command execution at address 0x%x\n", |
| 906 | __func__, addr); |
Carl-Daniel Hailfinger | 2f1b36f | 2009-07-12 12:06:18 +0000 | [diff] [blame] | 907 | } |
| 908 | return result; |
Paul Fox | eb3acef | 2009-06-12 08:10:33 +0000 | [diff] [blame] | 909 | } |
| 910 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 911 | int spi_disable_blockprotect(void) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 912 | { |
| 913 | uint8_t status; |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 914 | int result; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 915 | |
Peter Stuge | fa8c550 | 2008-05-10 23:07:52 +0000 | [diff] [blame] | 916 | status = spi_read_status_register(); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 917 | /* If there is block protection in effect, unprotect it first. */ |
| 918 | if ((status & 0x3c) != 0) { |
| 919 | printf_debug("Some block protection in effect, disabling\n"); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 920 | result = spi_write_status_register(status & ~0x3c); |
| 921 | if (result) { |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 922 | fprintf(stderr, "spi_write_status_register failed\n"); |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 923 | return result; |
| 924 | } |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 925 | } |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 926 | return 0; |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 927 | } |
| 928 | |
Carl-Daniel Hailfinger | 598ec58 | 2008-11-18 00:41:02 +0000 | [diff] [blame] | 929 | int spi_nbyte_read(int address, uint8_t *bytes, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 930 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 931 | const unsigned char cmd[JEDEC_READ_OUTSIZE] = { |
| 932 | JEDEC_READ, |
Carl-Daniel Hailfinger | d3568ad | 2008-01-22 14:37:31 +0000 | [diff] [blame] | 933 | (address >> 16) & 0xff, |
| 934 | (address >> 8) & 0xff, |
| 935 | (address >> 0) & 0xff, |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 936 | }; |
| 937 | |
| 938 | /* Send Read */ |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 939 | return spi_send_command(sizeof(cmd), len, cmd, bytes); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 940 | } |
| 941 | |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 942 | /* |
| 943 | * Read a complete flash chip. |
| 944 | * Each page is read separately in chunks with a maximum size of chunksize. |
| 945 | */ |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 946 | int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 947 | { |
| 948 | int rc = 0; |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 949 | int i, j, starthere, lenhere; |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 950 | int page_size = flash->page_size; |
| 951 | int toread; |
| 952 | |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 953 | /* Warning: This loop has a very unusual condition and body. |
| 954 | * The loop needs to go through each page with at least one affected |
| 955 | * byte. The lowest page number is (start / page_size) since that |
| 956 | * division rounds down. The highest page number we want is the page |
| 957 | * where the last byte of the range lives. That last byte has the |
| 958 | * address (start + len - 1), thus the highest page number is |
| 959 | * (start + len - 1) / page_size. Since we want to include that last |
| 960 | * page as well, the loop condition uses <=. |
| 961 | */ |
| 962 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 963 | /* Byte position of the first byte in the range in this page. */ |
| 964 | /* starthere is an offset to the base address of the chip. */ |
| 965 | starthere = max(start, i * page_size); |
| 966 | /* Length of bytes in the range in this page. */ |
| 967 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
| 968 | for (j = 0; j < lenhere; j += chunksize) { |
| 969 | toread = min(chunksize, lenhere - j); |
| 970 | rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread); |
Carl-Daniel Hailfinger | 38a059d | 2009-06-13 12:04:03 +0000 | [diff] [blame] | 971 | if (rc) |
| 972 | break; |
| 973 | } |
| 974 | if (rc) |
| 975 | break; |
| 976 | } |
| 977 | |
| 978 | return rc; |
| 979 | } |
| 980 | |
Carl-Daniel Hailfinger | cbf563c | 2009-06-16 08:55:44 +0000 | [diff] [blame] | 981 | int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 982 | { |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 983 | if (!spi_programmer[spi_controller].read) { |
| 984 | fprintf(stderr, "%s called, but SPI read is unsupported on this" |
| 985 | " hardware. Please report a bug.\n", __func__); |
| 986 | return 1; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 987 | } |
| 988 | |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 989 | return spi_programmer[spi_controller].read(flash, buf, start, len); |
Ronald Hoogenboom | 7ff530b | 2008-01-19 00:04:46 +0000 | [diff] [blame] | 990 | } |
| 991 | |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 992 | /* |
| 993 | * Program chip using byte programming. (SLOW!) |
| 994 | * This is for chips which can only handle one byte writes |
| 995 | * and for chips where memory mapped programming is impossible |
| 996 | * (e.g. due to size constraints in IT87* for over 512 kB) |
| 997 | */ |
| 998 | int spi_chip_write_1(struct flashchip *flash, uint8_t *buf) |
| 999 | { |
| 1000 | int total_size = 1024 * flash->total_size; |
Carl-Daniel Hailfinger | de75a5e | 2009-10-01 13:16:32 +0000 | [diff] [blame] | 1001 | int i, result = 0; |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 1002 | |
| 1003 | spi_disable_blockprotect(); |
Carl-Daniel Hailfinger | 116081a | 2009-08-10 02:29:21 +0000 | [diff] [blame] | 1004 | /* Erase first */ |
| 1005 | printf("Erasing flash before programming... "); |
Carl-Daniel Hailfinger | f38431a | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 1006 | if (erase_flash(flash)) { |
Carl-Daniel Hailfinger | 116081a | 2009-08-10 02:29:21 +0000 | [diff] [blame] | 1007 | fprintf(stderr, "ERASE FAILED!\n"); |
| 1008 | return -1; |
| 1009 | } |
| 1010 | printf("done.\n"); |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 1011 | for (i = 0; i < total_size; i++) { |
Carl-Daniel Hailfinger | de75a5e | 2009-10-01 13:16:32 +0000 | [diff] [blame] | 1012 | result = spi_byte_program(i, buf[i]); |
| 1013 | if (result) |
| 1014 | return 1; |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 1015 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 1016 | programmer_delay(10); |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 1017 | } |
| 1018 | |
| 1019 | return 0; |
| 1020 | } |
| 1021 | |
| 1022 | /* |
| 1023 | * Program chip using page (256 bytes) programming. |
| 1024 | * Some SPI masters can't do this, they use single byte programming instead. |
| 1025 | */ |
Carl-Daniel Hailfinger | 8d49701 | 2009-05-09 02:34:18 +0000 | [diff] [blame] | 1026 | int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) |
Carl-Daniel Hailfinger | bfe5b4a | 2008-05-13 23:03:12 +0000 | [diff] [blame] | 1027 | { |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1028 | if (!spi_programmer[spi_controller].write_256) { |
| 1029 | fprintf(stderr, "%s called, but SPI page write is unsupported " |
| 1030 | " on this hardware. Please report a bug.\n", __func__); |
| 1031 | return 1; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 1032 | } |
| 1033 | |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1034 | return spi_programmer[spi_controller].write_256(flash, buf); |
Carl-Daniel Hailfinger | 6b44496 | 2007-10-18 00:24:07 +0000 | [diff] [blame] | 1035 | } |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1036 | |
Carl-Daniel Hailfinger | 3e9dbea | 2009-05-13 11:40:08 +0000 | [diff] [blame] | 1037 | uint32_t spi_get_valid_read_addr(void) |
| 1038 | { |
| 1039 | /* Need to return BBAR for ICH chipsets. */ |
| 1040 | return 0; |
| 1041 | } |
| 1042 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 1043 | int spi_aai_write(struct flashchip *flash, uint8_t *buf) |
| 1044 | { |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1045 | uint32_t pos = 2, size = flash->total_size * 1024; |
| 1046 | unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 1047 | int result; |
| 1048 | |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 1049 | switch (spi_controller) { |
Carl-Daniel Hailfinger | 66ef4e5 | 2009-12-13 22:28:00 +0000 | [diff] [blame] | 1050 | #if INTERNAL_SUPPORT == 1 |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 1051 | case SPI_CONTROLLER_WBSIO: |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 1052 | fprintf(stderr, "%s: impossible with Winbond SPI masters," |
| 1053 | " degrading to byte program\n", __func__); |
Carl-Daniel Hailfinger | 96930c3 | 2009-05-09 02:30:21 +0000 | [diff] [blame] | 1054 | return spi_chip_write_1(flash, buf); |
Carl-Daniel Hailfinger | 66ef4e5 | 2009-12-13 22:28:00 +0000 | [diff] [blame] | 1055 | #endif |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 1056 | default: |
| 1057 | break; |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1058 | } |
Carl-Daniel Hailfinger | f38431a | 2009-09-05 02:30:58 +0000 | [diff] [blame] | 1059 | if (erase_flash(flash)) { |
Carl-Daniel Hailfinger | 3431bb7 | 2009-06-24 08:28:39 +0000 | [diff] [blame] | 1060 | fprintf(stderr, "ERASE FAILED!\n"); |
| 1061 | return -1; |
| 1062 | } |
Carl-Daniel Hailfinger | db53ec5 | 2009-12-22 23:54:10 +0000 | [diff] [blame] | 1063 | /* FIXME: This will fail on ICH/VIA SPI. */ |
Carl-Daniel Hailfinger | 03adbe1 | 2009-05-09 02:09:45 +0000 | [diff] [blame] | 1064 | result = spi_write_enable(); |
| 1065 | if (result) |
| 1066 | return result; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 1067 | spi_send_command(6, 0, w, NULL); |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1068 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 1069 | programmer_delay(5); /* SST25VF040B Tbp is max 10us */ |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1070 | while (pos < size) { |
| 1071 | w[1] = buf[pos++]; |
| 1072 | w[2] = buf[pos++]; |
Carl-Daniel Hailfinger | d047829 | 2009-07-10 21:08:55 +0000 | [diff] [blame] | 1073 | spi_send_command(3, 0, w, NULL); |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1074 | while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 1075 | programmer_delay(5); /* SST25VF040B Tbp is max 10us */ |
Peter Stuge | fd9217d | 2009-01-26 03:37:40 +0000 | [diff] [blame] | 1076 | } |
| 1077 | spi_write_disable(); |
| 1078 | return 0; |
| 1079 | } |