blob: bb09e58405b019b09013e68a7cd34b320eb0170c [file] [log] [blame]
Stefan Tauner6ee37e22012-12-29 15:03:51 +00001/*
2 * This file is part of the flashrom project.
3 * It handles everything related to status registers of the JEDEC family 25.
4 *
5 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
6 * Copyright (C) 2008 coresystems GmbH
7 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
8 * Copyright (C) 2012 Stefan Tauner
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Stefan Tauner6ee37e22012-12-29 15:03:51 +000018 */
19
20#include "flash.h"
21#include "chipdrivers.h"
22#include "spi.h"
23
24/* === Generic functions === */
Stefan Tauner6ee37e22012-12-29 15:03:51 +000025static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode)
26{
27 int result;
28 int i = 0;
29 /*
30 * WRSR requires either EWSR or WREN depending on chip type.
31 * The code below relies on the fact hat EWSR and WREN have the same
32 * INSIZE and OUTSIZE.
33 */
34 struct spi_command cmds[] = {
35 {
36 .writecnt = JEDEC_WREN_OUTSIZE,
37 .writearr = (const unsigned char[]){ enable_opcode },
38 .readcnt = 0,
39 .readarr = NULL,
40 }, {
41 .writecnt = JEDEC_WRSR_OUTSIZE,
42 .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
43 .readcnt = 0,
44 .readarr = NULL,
45 }, {
46 .writecnt = 0,
47 .writearr = NULL,
48 .readcnt = 0,
49 .readarr = NULL,
50 }};
51
52 result = spi_send_multicommand(flash, cmds);
53 if (result) {
54 msg_cerr("%s failed during command execution\n", __func__);
55 /* No point in waiting for the command to complete if execution
56 * failed.
57 */
58 return result;
59 }
60 /* WRSR performs a self-timed erase before the changes take effect.
61 * This may take 50-85 ms in most cases, and some chips apparently
62 * allow running RDSR only once. Therefore pick an initial delay of
63 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
64 */
65 programmer_delay(100 * 1000);
66 while (spi_read_status_register(flash) & SPI_SR_WIP) {
67 if (++i > 490) {
68 msg_cerr("Error: WIP bit after WRSR never cleared\n");
69 return TIMEOUT_ERROR;
70 }
71 programmer_delay(10 * 1000);
72 }
73 return 0;
74}
75
76int spi_write_status_register(struct flashctx *flash, int status)
77{
78 int feature_bits = flash->chip->feature_bits;
79 int ret = 1;
80
81 if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {
82 msg_cdbg("Missing status register write definition, assuming "
83 "EWSR is needed\n");
84 feature_bits |= FEATURE_WRSR_EWSR;
85 }
86 if (feature_bits & FEATURE_WRSR_WREN)
87 ret = spi_write_status_register_flag(flash, status, JEDEC_WREN);
88 if (ret && (feature_bits & FEATURE_WRSR_EWSR))
89 ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR);
90 return ret;
91}
92
93uint8_t spi_read_status_register(struct flashctx *flash)
94{
95 static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
96 /* FIXME: No workarounds for driver/hardware bugs in generic code. */
97 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
98 int ret;
99
100 /* Read Status Register */
101 ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
Nico Huber1f081532017-10-14 15:01:13 +0200102 if (ret) {
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000103 msg_cerr("RDSR failed!\n");
Nico Huber1f081532017-10-14 15:01:13 +0200104 /* FIXME: We should propagate the error. */
105 return 0;
106 }
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000107
108 return readarr[0];
109}
110
Stefan Tauner9530a022012-12-29 15:04:05 +0000111/* A generic block protection disable.
112 * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise.
113 * Tests if the register bits are locked with the lock_mask (lock_mask).
Stefan Taunercecb2c52013-06-20 22:55:41 +0000114 * Tests if a hardware protection is active (i.e. low pin/high bit value) with the write protection mask
115 * (wp_mask) and bails out in that case.
116 * If there are register lock bits set we try to disable them by unsetting those bits of the previous register
117 * contents that are set in the lock_mask. We then check if removing the lock bits has worked and continue as if
118 * they never had been engaged:
119 * If the lock bits are out of the way try to disable engaged protections.
120 * To support uncommon global unprotects (e.g. on most AT2[56]xx1(A)) unprotect_mask can be used to force
121 * bits to 0 additionally to those set in bp_mask and lock_mask. Only bits set in unprotect_mask are potentially
122 * preserved when doing the final unprotect.
123 *
124 * To sum up:
125 * bp_mask: set those bits that correspond to the bits in the status register that indicate an active protection
126 * (which should be unset after this function returns).
127 * lock_mask: set the bits that correspond to the bits that lock changing the bits above.
128 * wp_mask: set the bits that correspond to bits indicating non-software revocable protections.
129 * unprotect_mask: set the bits that should be preserved if possible when unprotecting.
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000130 */
Stefan Taunercecb2c52013-06-20 22:55:41 +0000131static int spi_disable_blockprotect_generic(struct flashctx *flash, uint8_t bp_mask, uint8_t lock_mask, uint8_t wp_mask, uint8_t unprotect_mask)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000132{
133 uint8_t status;
134 int result;
135
136 status = spi_read_status_register(flash);
Stefan Tauner9530a022012-12-29 15:04:05 +0000137 if ((status & bp_mask) == 0) {
138 msg_cdbg2("Block protection is disabled.\n");
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000139 return 0;
Stefan Tauner9530a022012-12-29 15:04:05 +0000140 }
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000141
142 msg_cdbg("Some block protection in effect, disabling... ");
Stefan Tauner9530a022012-12-29 15:04:05 +0000143 if ((status & lock_mask) != 0) {
144 msg_cdbg("\n\tNeed to disable the register lock first... ");
145 if (wp_mask != 0 && (status & wp_mask) == 0) {
146 msg_cerr("Hardware protection is active, disabling write protection is impossible.\n");
147 return 1;
148 }
149 /* All bits except the register lock bit (often called SPRL, SRWD, WPEN) are readonly. */
150 result = spi_write_status_register(flash, status & ~lock_mask);
151 if (result) {
152 msg_cerr("spi_write_status_register failed.\n");
153 return result;
154 }
Stefan Taunercecb2c52013-06-20 22:55:41 +0000155 status = spi_read_status_register(flash);
156 if ((status & lock_mask) != 0) {
157 msg_cerr("Unsetting lock bit(s) failed.\n");
158 return 1;
159 }
Stefan Tauner9530a022012-12-29 15:04:05 +0000160 msg_cdbg("done.\n");
161 }
162 /* Global unprotect. Make sure to mask the register lock bit as well. */
Stefan Taunercecb2c52013-06-20 22:55:41 +0000163 result = spi_write_status_register(flash, status & ~(bp_mask | lock_mask) & unprotect_mask);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000164 if (result) {
165 msg_cerr("spi_write_status_register failed.\n");
166 return result;
167 }
168 status = spi_read_status_register(flash);
Stefan Tauner9530a022012-12-29 15:04:05 +0000169 if ((status & bp_mask) != 0) {
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000170 msg_cerr("Block protection could not be disabled!\n");
Yuji Sasaki4af36092019-03-22 10:59:50 -0700171 if (flash->chip->printlock)
172 flash->chip->printlock(flash);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000173 return 1;
174 }
Stefan Tauner9530a022012-12-29 15:04:05 +0000175 msg_cdbg("disabled.\n");
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000176 return 0;
177}
178
Stefan Tauner9530a022012-12-29 15:04:05 +0000179/* A common block protection disable that tries to unset the status register bits masked by 0x3C. */
180int spi_disable_blockprotect(struct flashctx *flash)
181{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000182 return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF);
Stefan Tauner9530a022012-12-29 15:04:05 +0000183}
184
Wei Hu25584de2018-04-30 14:02:08 -0700185int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash)
186{
187 int result = spi_write_enable(flash);
188 if (result)
189 return result;
190
191 static const unsigned char cmd[] = { 0x98 }; /* ULBPR */
192 result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
193 if (result)
194 msg_cerr("ULBPR failed\n");
195 return result;
196}
197
Stefan Taunera60d4082014-06-04 16:17:03 +0000198/* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and
199 * protected/locked by bit #7. Useful when bits 4-5 may be non-0). */
200int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash)
201{
202 return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF);
203}
204
Stefan Tauner278ba6e2013-06-28 21:28:27 +0000205/* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and
206 * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly
207 * non-0). */
208int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash)
209{
210 return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF);
211}
212
213/* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and
214 * protected/locked by bit #7. */
215int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash)
216{
217 return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0, 0xFF);
218}
219
220/* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and
221 * protected/locked by bit #7. */
222int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash)
223{
224 return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
225}
Stefan Tauner9530a022012-12-29 15:04:05 +0000226
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000227static void spi_prettyprint_status_register_hex(uint8_t status)
228{
229 msg_cdbg("Chip status register is 0x%02x.\n", status);
230}
231
Stefan Taunerb6b00e92013-06-28 21:28:43 +0000232/* Common highest bit: Status Register Write Disable (SRWD) or Status Register Protect (SRP). */
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000233static void spi_prettyprint_status_register_srwd(uint8_t status)
234{
Stefan Taunerb6b00e92013-06-28 21:28:43 +0000235 msg_cdbg("Chip status register: Status Register Write Disable (SRWD, SRP, ...) is %sset\n",
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000236 (status & (1 << 7)) ? "" : "not ");
237}
238
239/* Common highest bit: Block Protect Write Disable (BPL). */
240static void spi_prettyprint_status_register_bpl(uint8_t status)
241{
242 msg_cdbg("Chip status register: Block Protect Write Disable (BPL) is %sset\n",
243 (status & (1 << 7)) ? "" : "not ");
244}
245
246/* Common lowest 2 bits: WEL and WIP. */
247static void spi_prettyprint_status_register_welwip(uint8_t status)
248{
249 msg_cdbg("Chip status register: Write Enable Latch (WEL) is %sset\n",
250 (status & (1 << 1)) ? "" : "not ");
251 msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is %sset\n",
252 (status & (1 << 0)) ? "" : "not ");
253}
254
255/* Common block protection (BP) bits. */
256static void spi_prettyprint_status_register_bp(uint8_t status, int bp)
257{
258 switch (bp) {
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000259 case 4:
260 msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n",
Stefan Tauner5c316f92015-02-08 21:57:52 +0000261 (status & (1 << 6)) ? "" : "not ");
Richard Hughesdb7482b2018-12-19 12:04:30 +0000262 /* Fall through. */
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000263 case 3:
264 msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
265 (status & (1 << 5)) ? "" : "not ");
Richard Hughesdb7482b2018-12-19 12:04:30 +0000266 /* Fall through. */
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000267 case 2:
268 msg_cdbg("Chip status register: Block Protect 2 (BP2) is %sset\n",
269 (status & (1 << 4)) ? "" : "not ");
Richard Hughesdb7482b2018-12-19 12:04:30 +0000270 /* Fall through. */
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000271 case 1:
272 msg_cdbg("Chip status register: Block Protect 1 (BP1) is %sset\n",
273 (status & (1 << 3)) ? "" : "not ");
Richard Hughesdb7482b2018-12-19 12:04:30 +0000274 /* Fall through. */
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000275 case 0:
276 msg_cdbg("Chip status register: Block Protect 0 (BP0) is %sset\n",
277 (status & (1 << 2)) ? "" : "not ");
278 }
279}
280
281/* Unnamed bits. */
Aidan Thorntondb4e87d2013-08-27 18:01:53 +0000282void spi_prettyprint_status_register_bit(uint8_t status, int bit)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000283{
284 msg_cdbg("Chip status register: Bit %i is %sset\n", bit, (status & (1 << bit)) ? "" : "not ");
285}
286
287int spi_prettyprint_status_register_plain(struct flashctx *flash)
288{
289 uint8_t status = spi_read_status_register(flash);
290 spi_prettyprint_status_register_hex(status);
291 return 0;
292}
293
Stefan Tauner278ba6e2013-06-28 21:28:27 +0000294/* Print the plain hex value and the welwip bits only. */
295int spi_prettyprint_status_register_default_welwip(struct flashctx *flash)
296{
297 uint8_t status = spi_read_status_register(flash);
298 spi_prettyprint_status_register_hex(status);
299
300 spi_prettyprint_status_register_welwip(status);
301 return 0;
302}
303
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000304/* Works for many chips of the
305 * AMIC A25L series
306 * and MX MX25L512
307 */
Stefan Tauner12f3d512014-05-27 21:27:27 +0000308int spi_prettyprint_status_register_bp1_srwd(struct flashctx *flash)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000309{
310 uint8_t status = spi_read_status_register(flash);
311 spi_prettyprint_status_register_hex(status);
312
313 spi_prettyprint_status_register_srwd(status);
314 spi_prettyprint_status_register_bit(status, 6);
315 spi_prettyprint_status_register_bit(status, 5);
316 spi_prettyprint_status_register_bit(status, 4);
317 spi_prettyprint_status_register_bp(status, 1);
318 spi_prettyprint_status_register_welwip(status);
319 return 0;
320}
321
322/* Works for many chips of the
323 * AMIC A25L series
Stefan Taunerf4451612013-04-19 01:59:15 +0000324 * PMC Pm25LD series
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000325 */
Stefan Tauner12f3d512014-05-27 21:27:27 +0000326int spi_prettyprint_status_register_bp2_srwd(struct flashctx *flash)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000327{
328 uint8_t status = spi_read_status_register(flash);
329 spi_prettyprint_status_register_hex(status);
330
331 spi_prettyprint_status_register_srwd(status);
332 spi_prettyprint_status_register_bit(status, 6);
333 spi_prettyprint_status_register_bit(status, 5);
334 spi_prettyprint_status_register_bp(status, 2);
335 spi_prettyprint_status_register_welwip(status);
336 return 0;
337}
338
339/* Works for many chips of the
340 * ST M25P series
341 * MX MX25L series
342 */
Stefan Tauner12f3d512014-05-27 21:27:27 +0000343int spi_prettyprint_status_register_bp3_srwd(struct flashctx *flash)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000344{
345 uint8_t status = spi_read_status_register(flash);
346 spi_prettyprint_status_register_hex(status);
347
348 spi_prettyprint_status_register_srwd(status);
349 spi_prettyprint_status_register_bit(status, 6);
350 spi_prettyprint_status_register_bp(status, 3);
351 spi_prettyprint_status_register_welwip(status);
352 return 0;
353}
354
Stefan Tauner12f3d512014-05-27 21:27:27 +0000355int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash)
Stefan Tauner278ba6e2013-06-28 21:28:27 +0000356{
357 uint8_t status = spi_read_status_register(flash);
358 spi_prettyprint_status_register_hex(status);
359
360 spi_prettyprint_status_register_srwd(status);
361 spi_prettyprint_status_register_bp(status, 4);
362 spi_prettyprint_status_register_welwip(status);
363 return 0;
364}
365
Stefan Tauner85f09f72014-05-27 21:27:14 +0000366int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash)
367{
368 uint8_t status = spi_read_status_register(flash);
369 spi_prettyprint_status_register_hex(status);
370
371 spi_prettyprint_status_register_bpl(status);
372 spi_prettyprint_status_register_bit(status, 6);
373 spi_prettyprint_status_register_bit(status, 5);
374 spi_prettyprint_status_register_bp(status, 2);
375 spi_prettyprint_status_register_welwip(status);
376 return 0;
377}
378
Ben Gardnerbcf61092015-11-22 02:23:31 +0000379int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash)
380{
381 uint8_t status = spi_read_status_register(flash);
382 spi_prettyprint_status_register_hex(status);
383
384 spi_prettyprint_status_register_bpl(status);
385 spi_prettyprint_status_register_bit(status, 6);
386 msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
387 spi_prettyprint_status_register_bp(status, 2);
388 spi_prettyprint_status_register_welwip(status);
389 return 0;
390}
391
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000392/* === Amic ===
393 * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using
Stefan Tauner12f3d512014-05-27 21:27:27 +0000394 * spi_prettyprint_status_register_bp1_srwd or
395 * spi_prettyprint_status_register_bp2_srwd.
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000396 * FIXME: spi_disable_blockprotect is incorrect and will fail for chips using
397 * spi_prettyprint_status_register_amic_a25l032 if those have locks controlled
398 * by the second status register.
399 */
400
401int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash)
402{
403 uint8_t status = spi_read_status_register(flash);
404 spi_prettyprint_status_register_hex(status);
405
406 spi_prettyprint_status_register_srwd(status);
407 msg_cdbg("Chip status register: Sector Protect Size (SEC) is %i KB\n", (status & (1 << 6)) ? 4 : 64);
408 msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
409 spi_prettyprint_status_register_bp(status, 2);
410 spi_prettyprint_status_register_welwip(status);
411 msg_cdbg("Chip status register 2 is NOT decoded!\n");
412 return 0;
413}
414
415/* === Atmel === */
416
417static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status)
418{
419 msg_cdbg("Chip status register: Write Protect Enable (WPEN) is %sset\n",
420 (status & (1 << 7)) ? "" : "not ");
421}
422
423static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status)
424{
425 msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) is %sset\n",
426 (status & (1 << 7)) ? "" : "not ");
427}
428
429static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status)
430{
431 msg_cdbg("Chip status register: Erase/Program Error (EPE) is %sset\n",
432 (status & (1 << 5)) ? "" : "not ");
433 msg_cdbg("Chip status register: WP# pin (WPP) is %sasserted\n",
434 (status & (1 << 4)) ? "not " : "");
435}
436
437static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status)
438{
439 msg_cdbg("Chip status register: Software Protection Status (SWP): ");
440 switch (status & (3 << 2)) {
441 case 0x0 << 2:
442 msg_cdbg("no sectors are protected\n");
443 break;
444 case 0x1 << 2:
445 msg_cdbg("some sectors are protected\n");
446 /* FIXME: Read individual Sector Protection Registers. */
447 break;
448 case 0x3 << 2:
449 msg_cdbg("all sectors are protected\n");
450 break;
451 default:
452 msg_cdbg("reserved for future use\n");
453 break;
454 }
455}
456
457int spi_prettyprint_status_register_at25df(struct flashctx *flash)
458{
459 uint8_t status = spi_read_status_register(flash);
460 spi_prettyprint_status_register_hex(status);
461
462 spi_prettyprint_status_register_atmel_at25_srpl(status);
463 spi_prettyprint_status_register_bit(status, 6);
464 spi_prettyprint_status_register_atmel_at25_epewpp(status);
465 spi_prettyprint_status_register_atmel_at25_swp(status);
466 spi_prettyprint_status_register_welwip(status);
467 return 0;
468}
469
470int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash)
471{
472 /* FIXME: We should check the security lockdown. */
473 msg_cdbg("Ignoring security lockdown (if present)\n");
474 msg_cdbg("Ignoring status register byte 2\n");
475 return spi_prettyprint_status_register_at25df(flash);
476}
477
Stefan Tauner57794ac2012-12-29 15:04:20 +0000478/* used for AT25F512, AT25F1024(A), AT25F2048 */
479int spi_prettyprint_status_register_at25f(struct flashctx *flash)
480{
481 uint8_t status;
482
483 status = spi_read_status_register(flash);
484 spi_prettyprint_status_register_hex(status);
485
486 spi_prettyprint_status_register_atmel_at25_wpen(status);
487 spi_prettyprint_status_register_bit(status, 6);
488 spi_prettyprint_status_register_bit(status, 5);
489 spi_prettyprint_status_register_bit(status, 4);
490 spi_prettyprint_status_register_bp(status, 1);
491 spi_prettyprint_status_register_welwip(status);
492 return 0;
493}
494
495int spi_prettyprint_status_register_at25f512a(struct flashctx *flash)
496{
497 uint8_t status;
498
499 status = spi_read_status_register(flash);
500 spi_prettyprint_status_register_hex(status);
501
502 spi_prettyprint_status_register_atmel_at25_wpen(status);
503 spi_prettyprint_status_register_bit(status, 6);
504 spi_prettyprint_status_register_bit(status, 5);
505 spi_prettyprint_status_register_bit(status, 4);
506 spi_prettyprint_status_register_bit(status, 3);
507 spi_prettyprint_status_register_bp(status, 0);
508 spi_prettyprint_status_register_welwip(status);
509 return 0;
510}
511
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000512int spi_prettyprint_status_register_at25f512b(struct flashctx *flash)
513{
514 uint8_t status = spi_read_status_register(flash);
515 spi_prettyprint_status_register_hex(status);
516
517 spi_prettyprint_status_register_atmel_at25_srpl(status);
518 spi_prettyprint_status_register_bit(status, 6);
519 spi_prettyprint_status_register_atmel_at25_epewpp(status);
520 spi_prettyprint_status_register_bit(status, 3);
521 spi_prettyprint_status_register_bp(status, 0);
522 spi_prettyprint_status_register_welwip(status);
523 return 0;
524}
525
Stefan Tauner57794ac2012-12-29 15:04:20 +0000526int spi_prettyprint_status_register_at25f4096(struct flashctx *flash)
527{
528 uint8_t status;
529
530 status = spi_read_status_register(flash);
531 spi_prettyprint_status_register_hex(status);
532
533 spi_prettyprint_status_register_atmel_at25_wpen(status);
534 spi_prettyprint_status_register_bit(status, 6);
535 spi_prettyprint_status_register_bit(status, 5);
536 spi_prettyprint_status_register_bp(status, 2);
537 spi_prettyprint_status_register_welwip(status);
538 return 0;
539}
540
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000541int spi_prettyprint_status_register_at25fs010(struct flashctx *flash)
542{
543 uint8_t status = spi_read_status_register(flash);
544 spi_prettyprint_status_register_hex(status);
545
546 spi_prettyprint_status_register_atmel_at25_wpen(status);
547 msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is "
548 "%sset\n", (status & (1 << 6)) ? "" : "not ");
549 msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
550 "%sset\n", (status & (1 << 5)) ? "" : "not ");
551 spi_prettyprint_status_register_bit(status, 4);
552 msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
553 "%sset\n", (status & (1 << 3)) ? "" : "not ");
554 msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
555 "%sset\n", (status & (1 << 2)) ? "" : "not ");
556 /* FIXME: Pretty-print detailed sector protection status. */
557 spi_prettyprint_status_register_welwip(status);
558 return 0;
559}
560
561int spi_prettyprint_status_register_at25fs040(struct flashctx *flash)
562{
563 uint8_t status = spi_read_status_register(flash);
564 spi_prettyprint_status_register_hex(status);
565
566 spi_prettyprint_status_register_atmel_at25_wpen(status);
567 spi_prettyprint_status_register_bp(status, 4);
568 /* FIXME: Pretty-print detailed sector protection status. */
569 spi_prettyprint_status_register_welwip(status);
570 return 0;
571}
572
573int spi_prettyprint_status_register_at26df081a(struct flashctx *flash)
574{
575 uint8_t status = spi_read_status_register(flash);
576 spi_prettyprint_status_register_hex(status);
577
578 spi_prettyprint_status_register_atmel_at25_srpl(status);
579 msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) is %sset\n",
580 (status & (1 << 6)) ? "" : "not ");
581 spi_prettyprint_status_register_atmel_at25_epewpp(status);
582 spi_prettyprint_status_register_atmel_at25_swp(status);
583 spi_prettyprint_status_register_welwip(status);
584 return 0;
585}
586
Stefan Taunercecb2c52013-06-20 22:55:41 +0000587/* Some Atmel DataFlash chips support per sector protection bits and the write protection bits in the status
588 * register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all
589 * sectors at once by writing 0 not only the protection bits (2 and 3) but also completely unrelated bits (4 and
590 * 5) which normally are not touched.
591 * Affected are all known Atmel chips matched by AT2[56]D[FLQ]..1A? but the AT26DF041. */
592int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000593{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000594 return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 1 << 4, 0x00);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000595}
596
Stefan Taunercecb2c52013-06-20 22:55:41 +0000597int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash)
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000598{
599 /* FIXME: We should check the security lockdown. */
600 msg_cinfo("Ignoring security lockdown (if present)\n");
Stefan Taunercecb2c52013-06-20 22:55:41 +0000601 return spi_disable_blockprotect_at2x_global_unprotect(flash);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000602}
603
Stefan Tauner57794ac2012-12-29 15:04:20 +0000604int spi_disable_blockprotect_at25f(struct flashctx *flash)
605{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000606 return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF);
Stefan Tauner57794ac2012-12-29 15:04:20 +0000607}
608
609int spi_disable_blockprotect_at25f512a(struct flashctx *flash)
610{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000611 return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 0, 0xFF);
Stefan Tauner57794ac2012-12-29 15:04:20 +0000612}
613
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000614int spi_disable_blockprotect_at25f512b(struct flashctx *flash)
615{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000616 return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 1 << 4, 0xFF);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000617}
618
619int spi_disable_blockprotect_at25fs010(struct flashctx *flash)
620{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000621 return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0, 0xFF);
Stefan Tauner9530a022012-12-29 15:04:05 +0000622 }
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000623
624int spi_disable_blockprotect_at25fs040(struct flashctx *flash)
625{
Stefan Taunercecb2c52013-06-20 22:55:41 +0000626 return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000627}
628
Nikolay Nikolaevd0e3ea12013-06-28 21:29:08 +0000629/* === Eon === */
630
631int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash)
632{
633 uint8_t status = spi_read_status_register(flash);
634 spi_prettyprint_status_register_hex(status);
635
636 spi_prettyprint_status_register_srwd(status);
637 msg_cdbg("Chip status register: WP# disable (WPDIS) is %sabled\n", (status & (1 << 6)) ? "en " : "dis");
638 spi_prettyprint_status_register_bp(status, 3);
639 spi_prettyprint_status_register_welwip(status);
640 return 0;
641}
642
Nikolay Nikolaevc80c4a32013-06-28 21:29:44 +0000643/* === Intel/Numonyx/Micron - Spansion === */
Stefan Tauner54aaa4a2012-12-29 15:04:12 +0000644
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000645int spi_disable_blockprotect_n25q(struct flashctx *flash)
646{
647 return spi_disable_blockprotect_generic(flash, 0x5C, 1 << 7, 0, 0xFF);
648}
649
650int spi_prettyprint_status_register_n25q(struct flashctx *flash)
651{
652 uint8_t status = spi_read_status_register(flash);
653 spi_prettyprint_status_register_hex(status);
654
655 spi_prettyprint_status_register_srwd(status);
656 if (flash->chip->total_size <= 32 / 8 * 1024) /* N25Q16 and N25Q32: reserved */
657 spi_prettyprint_status_register_bit(status, 6);
658 else
659 msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
660 (status & (1 << 6)) ? "" : "not ");
661 msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
662 spi_prettyprint_status_register_bp(status, 2);
663 spi_prettyprint_status_register_welwip(status);
664 return 0;
665}
666
Nikolay Nikolaevc80c4a32013-06-28 21:29:44 +0000667/* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */
Stefan Tauner54aaa4a2012-12-29 15:04:12 +0000668/* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */
Nikolay Nikolaevc80c4a32013-06-28 21:29:44 +0000669int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash)
Stefan Tauner54aaa4a2012-12-29 15:04:12 +0000670{
Stefan Tauner278ba6e2013-06-28 21:28:27 +0000671 return spi_disable_blockprotect_bp2_srwd(flash);
Stefan Tauner54aaa4a2012-12-29 15:04:12 +0000672}
673
Nikolay Nikolaevc80c4a32013-06-28 21:29:44 +0000674/* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */
675int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash)
Stefan Tauner54aaa4a2012-12-29 15:04:12 +0000676{
677 uint8_t status = spi_read_status_register(flash);
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000678 spi_prettyprint_status_register_hex(status);
Stefan Tauner54aaa4a2012-12-29 15:04:12 +0000679
680 spi_prettyprint_status_register_srwd(status);
681 msg_cdbg("Chip status register: Program Fail Flag (P_FAIL) is %sset\n",
682 (status & (1 << 6)) ? "" : "not ");
683 msg_cdbg("Chip status register: Erase Fail Flag (E_FAIL) is %sset\n",
684 (status & (1 << 5)) ? "" : "not ");
685 spi_prettyprint_status_register_bp(status, 2);
686 spi_prettyprint_status_register_welwip(status);
687 return 0;
688}
689
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000690/* === SST === */
691
692static void spi_prettyprint_status_register_sst25_common(uint8_t status)
693{
694 spi_prettyprint_status_register_hex(status);
695
696 spi_prettyprint_status_register_bpl(status);
697 msg_cdbg("Chip status register: Auto Address Increment Programming (AAI) is %sset\n",
698 (status & (1 << 6)) ? "" : "not ");
699 spi_prettyprint_status_register_bp(status, 3);
700 spi_prettyprint_status_register_welwip(status);
701}
702
703int spi_prettyprint_status_register_sst25(struct flashctx *flash)
704{
705 uint8_t status = spi_read_status_register(flash);
706 spi_prettyprint_status_register_sst25_common(status);
707 return 0;
708}
709
710int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash)
711{
712 static const char *const bpt[] = {
713 "none",
714 "1F0000H-1FFFFFH",
715 "1E0000H-1FFFFFH",
716 "1C0000H-1FFFFFH",
717 "180000H-1FFFFFH",
718 "100000H-1FFFFFH",
719 "all", "all"
720 };
721 uint8_t status = spi_read_status_register(flash);
722 spi_prettyprint_status_register_sst25_common(status);
723 msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]);
724 return 0;
725}
726
727int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash)
728{
729 static const char *const bpt[] = {
730 "none",
731 "0x70000-0x7ffff",
732 "0x60000-0x7ffff",
733 "0x40000-0x7ffff",
734 "all blocks", "all blocks", "all blocks", "all blocks"
735 };
736 uint8_t status = spi_read_status_register(flash);
737 spi_prettyprint_status_register_sst25_common(status);
738 msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]);
739 return 0;
740}