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Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the ITE IT87* SPI specific routines
24 */
25
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000026#include <string.h>
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +000027#include <stdlib.h>
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000028#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000029#include "chipdrivers.h"
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000030#include "spi.h"
31
32#define ITE_SUPERIO_PORT1 0x2e
33#define ITE_SUPERIO_PORT2 0x4e
34
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000035uint16_t it8716f_flashport = 0;
36/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
37int fast_spi = 1;
38
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000039/* Helper functions for most recent ITE IT87xx Super I/O chips */
40#define CHIP_ID_BYTE1_REG 0x20
41#define CHIP_ID_BYTE2_REG 0x21
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000042void enter_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0x87, port);
45 OUTB(0x01, port);
46 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000047 if (port == ITE_SUPERIO_PORT1)
Andriy Gapon65c1b862008-05-22 13:22:45 +000048 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000049 else
Andriy Gapon65c1b862008-05-22 13:22:45 +000050 OUTB(0xaa, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000051}
52
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000053void exit_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000054{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055 sio_write(port, 0x02, 0x02);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000056}
57
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000058uint16_t probe_id_ite(uint16_t port)
59{
60 uint16_t id;
61
62 enter_conf_mode_ite(port);
63 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
64 id |= sio_read(port, CHIP_ID_BYTE2_REG);
65 exit_conf_mode_ite(port);
66
67 return id;
68}
69
70struct superio probe_superio_ite(void)
71{
72 struct superio ret = {};
73 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
74 uint16_t *i = ite_ports;
75
76 ret.vendor = SUPERIO_VENDOR_ITE;
77 for (; *i; i++) {
78 ret.port = *i;
79 ret.model = probe_id_ite(ret.port);
80 switch (ret.model >> 8) {
81 case 0x82:
82 case 0x86:
83 case 0x87:
Uwe Hermann43959702010-03-13 17:28:29 +000084 msg_pinfo("Found ITE Super I/O, id %04hx\n",
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000085 ret.model);
86 return ret;
87 }
88 }
89
90 /* No good ID found. */
91 ret.vendor = SUPERIO_VENDOR_NONE;
92 ret.port = 0;
93 ret.model = 0;
94 return ret;
95}
96
97static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000098{
99 uint8_t tmp = 0;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000100 char *portpos = NULL;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000101 uint16_t flashport = 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000102
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000103 switch (id) {
104 case 0x8716:
105 case 0x8718:
106 enter_conf_mode_ite(port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000107 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000108 tmp = sio_read(port, 0x24) & 0xFE;
Sean Nelson01e532d2010-01-10 01:09:58 +0000109 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000110 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
Sean Nelson01e532d2010-01-10 01:09:58 +0000111 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000112 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
Sean Nelson01e532d2010-01-10 01:09:58 +0000113 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000114 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
Sean Nelson01e532d2010-01-10 01:09:58 +0000115 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000116 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
Sean Nelson01e532d2010-01-10 01:09:58 +0000117 msg_pdbg("LPC write to serial flash %sabled\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000118 (tmp & 1 << 4) ? "en" : "dis");
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000119 /* The LPC->SPI force write enable below only makes sense for
120 * non-programmer mode.
121 */
Carl-Daniel Hailfinger337df1d2008-05-16 00:19:52 +0000122 /* If any serial flash segment is enabled, enable writing. */
123 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
Sean Nelson01e532d2010-01-10 01:09:58 +0000124 msg_pdbg("Enabling LPC write to serial flash\n");
Carl-Daniel Hailfinger337df1d2008-05-16 00:19:52 +0000125 tmp |= 1 << 4;
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000126 sio_write(port, 0x24, tmp);
Carl-Daniel Hailfinger337df1d2008-05-16 00:19:52 +0000127 }
Sean Nelson01e532d2010-01-10 01:09:58 +0000128 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000129 /* LDN 0x7, reg 0x64/0x65 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000130 sio_write(port, 0x07, 0x7);
131 flashport = sio_read(port, 0x64) << 8;
132 flashport |= sio_read(port, 0x65);
Sean Nelson01e532d2010-01-10 01:09:58 +0000133 msg_pdbg("Serial flash port 0x%04x\n", flashport);
Carl-Daniel Hailfingeref58a9c2009-08-12 13:32:56 +0000134 if (programmer_param && !strlen(programmer_param)) {
135 free(programmer_param);
136 programmer_param = NULL;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000137 }
Carl-Daniel Hailfingeref58a9c2009-08-12 13:32:56 +0000138 if (programmer_param && (portpos = strstr(programmer_param, "port="))) {
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000139 portpos += 5;
140 flashport = strtol(portpos, (char **)NULL, 0);
Sean Nelson01e532d2010-01-10 01:09:58 +0000141 msg_pinfo("Forcing serial flash port 0x%04x\n", flashport);
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000142 sio_write(port, 0x64, (flashport >> 8));
143 sio_write(port, 0x65, (flashport & 0xff));
144 }
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000145 exit_conf_mode_ite(port);
146 break;
147 /* TODO: Handle more IT87xx if they support flash translation */
148 default:
Sean Nelson01e532d2010-01-10 01:09:58 +0000149 msg_pinfo("SuperI/O ID %04hx is not on the controller list.\n", id);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000150 }
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000151 return flashport;
152}
153
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000154int it87spi_common_init(void)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000155{
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000156 if (superio.vendor != SUPERIO_VENDOR_ITE)
157 return 1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000158
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000159 it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000160
161 if (it8716f_flashport)
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000162 spi_controller = SPI_CONTROLLER_IT87XX;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000163
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000164 return (!it8716f_flashport);
165}
166
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000167
168int it87spi_init(void)
169{
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000170 int ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000171
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000172 get_io_perms();
Uwe Hermann43959702010-03-13 17:28:29 +0000173 /* Probe for the Super I/O chip and fill global struct superio. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000174 probe_superio();
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000175 ret = it87spi_common_init();
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000176 if (!ret) {
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000177 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000178 } else {
179 buses_supported = CHIP_BUSTYPE_NONE;
180 }
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000181 return ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000182}
183
184int it87xx_probe_spi_flash(const char *name)
185{
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000186 int ret;
187
188 ret = it87spi_common_init();
189 if (!ret)
190 buses_supported |= CHIP_BUSTYPE_SPI;
191 return ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000192}
193
Uwe Hermann394131e2008-10-18 21:14:13 +0000194/*
195 * The IT8716F only supports commands with length 1,2,4,5 bytes including
196 * command byte and can not read more than 3 bytes from the device.
197 *
198 * This function expects writearr[0] to be the first byte sent to the device,
199 * whereas the IT8716F splits commands internally into address and non-address
200 * commands with the address in inverse wire order. That's why the register
201 * ordering in case 4 and 5 may seem strange.
202 */
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000203int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Uwe Hermann394131e2008-10-18 21:14:13 +0000204 const unsigned char *writearr, unsigned char *readarr)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000205{
206 uint8_t busy, writeenc;
207 int i;
208
209 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000210 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000211 } while (busy);
212 if (readcnt > 3) {
Sean Nelson01e532d2010-01-10 01:09:58 +0000213 msg_pinfo("%s called with unsupported readcnt %i.\n",
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000214 __func__, readcnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000215 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000216 }
217 switch (writecnt) {
218 case 1:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000219 OUTB(writearr[0], it8716f_flashport + 1);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000220 writeenc = 0x0;
221 break;
222 case 2:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000223 OUTB(writearr[0], it8716f_flashport + 1);
224 OUTB(writearr[1], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000225 writeenc = 0x1;
226 break;
227 case 4:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000228 OUTB(writearr[0], it8716f_flashport + 1);
229 OUTB(writearr[1], it8716f_flashport + 4);
230 OUTB(writearr[2], it8716f_flashport + 3);
231 OUTB(writearr[3], it8716f_flashport + 2);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000232 writeenc = 0x2;
233 break;
234 case 5:
Andriy Gapon65c1b862008-05-22 13:22:45 +0000235 OUTB(writearr[0], it8716f_flashport + 1);
236 OUTB(writearr[1], it8716f_flashport + 4);
237 OUTB(writearr[2], it8716f_flashport + 3);
238 OUTB(writearr[3], it8716f_flashport + 2);
239 OUTB(writearr[4], it8716f_flashport + 7);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000240 writeenc = 0x3;
241 break;
242 default:
Sean Nelson01e532d2010-01-10 01:09:58 +0000243 msg_pinfo("%s called with unsupported writecnt %i.\n",
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000244 __func__, writecnt);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000245 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000246 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000247 /*
248 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000249 * Note:
250 * We can't use writecnt directly, but have to use a strange encoding.
Uwe Hermann394131e2008-10-18 21:14:13 +0000251 */
252 OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
253 | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000254
255 if (readcnt > 0) {
256 do {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000257 busy = INB(it8716f_flashport) & 0x80;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000258 } while (busy);
259
Uwe Hermann394131e2008-10-18 21:14:13 +0000260 for (i = 0; i < readcnt; i++)
Andriy Gapon65c1b862008-05-22 13:22:45 +0000261 readarr[i] = INB(it8716f_flashport + 5 + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000262 }
263
264 return 0;
265}
266
267/* Page size is usually 256 bytes */
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000268static int it8716f_spi_page_program(struct flashchip *flash, int block, uint8_t *buf)
Uwe Hermann394131e2008-10-18 21:14:13 +0000269{
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000270 int i;
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000271 int result;
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000272 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000273
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000274 result = spi_write_enable();
275 if (result)
276 return result;
Carl-Daniel Hailfinger2f1b36f2009-07-12 12:06:18 +0000277 /* FIXME: The command below seems to be redundant or wrong. */
Uwe Hermann394131e2008-10-18 21:14:13 +0000278 OUTB(0x06, it8716f_flashport + 1);
Andriy Gapon65c1b862008-05-22 13:22:45 +0000279 OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000280 for (i = 0; i < 256; i++) {
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000281 chip_writeb(buf[256 * block + i], bios + 256 * block + i);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000282 }
Andriy Gapon65c1b862008-05-22 13:22:45 +0000283 OUTB(0, it8716f_flashport);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000284 /* Wait until the Write-In-Progress bit is cleared.
285 * This usually takes 1-10 ms, so wait in 1 ms steps.
286 */
287 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000288 programmer_delay(1000);
Carl-Daniel Hailfinger03adbe12009-05-09 02:09:45 +0000289 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000290}
291
292/*
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000293 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
294 * Need to read this big flash using firmware cycles 3 byte at a time.
295 */
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000296int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000297{
298 int total_size = 1024 * flash->total_size;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000299 fast_spi = 0;
300
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000301 if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) {
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000302 spi_read_chunked(flash, buf, start, len, 3);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000303 } else {
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000304 read_memmapped(flash, buf, start, len);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000305 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000306
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000307 return 0;
308}
309
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000310int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
Uwe Hermann394131e2008-10-18 21:14:13 +0000311{
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000312 int total_size = 1024 * flash->total_size;
313 int i;
Uwe Hermann394131e2008-10-18 21:14:13 +0000314
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000315 /*
316 * IT8716F only allows maximum of 512 kb SPI chip size for memory
317 * mapped access.
318 */
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000319 if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) {
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000320 spi_chip_write_1(flash, buf);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000321 } else {
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000322 spi_disable_blockprotect();
323 /* Erase first */
Sean Nelson01e532d2010-01-10 01:09:58 +0000324 msg_pinfo("Erasing flash before programming... ");
Carl-Daniel Hailfingerf38431a2009-09-05 02:30:58 +0000325 if (erase_flash(flash)) {
Sean Nelson01e532d2010-01-10 01:09:58 +0000326 msg_perr("ERASE FAILED!\n");
Carl-Daniel Hailfinger116081a2009-08-10 02:29:21 +0000327 return -1;
328 }
Sean Nelson01e532d2010-01-10 01:09:58 +0000329 msg_pinfo("done.\n");
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000330 for (i = 0; i < total_size / 256; i++) {
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000331 it8716f_spi_page_program(flash, i, buf);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000332 }
333 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000334
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000335 return 0;
336}