blob: bb6007e91e5604b7e2b269f10b3aa2a359843687 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Dominik Geyerb46acba2008-05-16 12:55:55 +00009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000023 */
24
25/*
26 * This module is designed for supporting the devices
27 * ST M25P40
28 * ST M25P80
29 * ST M25P16
30 * ST M25P32 already tested
31 * ST M25P64
32 * AT 25DF321 already tested
33 *
34 */
35
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000036#if defined(__i386__) || defined(__x86_64__)
37
Dominik Geyerb46acba2008-05-16 12:55:55 +000038#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000039#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000040#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000041#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000042#include "spi.h"
43
Stefan Reinauera9424d52008-06-27 16:28:34 +000044/* ICH9 controller register definition */
45#define ICH9_REG_FADDR 0x08 /* 32 Bits */
46#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
47
48#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000049#define SSFS_SCIP 0x00000001
50#define SSFS_CDS 0x00000004
51#define SSFS_FCERR 0x00000008
52#define SSFS_AEL 0x00000010
Stefan Reinauera9424d52008-06-27 16:28:34 +000053
54#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000055#define SSFC_SCGO 0x00000200
56#define SSFC_ACS 0x00000400
57#define SSFC_SPOP 0x00000800
58#define SSFC_COP 0x00001000
59#define SSFC_DBC 0x00010000
60#define SSFC_DS 0x00400000
61#define SSFC_SME 0x00800000
62#define SSFC_SCF 0x01000000
63#define SSFC_SCF_20MHZ 0x00000000
64#define SSFC_SCF_33MHZ 0x01000000
Stefan Reinauera9424d52008-06-27 16:28:34 +000065
66#define ICH9_REG_PREOP 0x94 /* 16 Bits */
67#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
68#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000069
70// ICH9R SPI commands
71#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
72#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
73#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
74#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
75
Stefan Reinauera9424d52008-06-27 16:28:34 +000076// ICH7 registers
77#define ICH7_REG_SPIS 0x00 /* 16 Bits */
78#define SPIS_SCIP 0x00000001
79#define SPIS_CDS 0x00000004
80#define SPIS_FCERR 0x00000008
81
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000082/* VIA SPI is compatible with ICH7, but maxdata
83 to transfer is 16 bytes.
84
85 DATA byte count on ICH7 is 8:13, on VIA 8:11
86
87 bit 12 is port select CS0 CS1
88 bit 13 is FAST READ enable
89 bit 7 is used with fast read and one shot controls CS de-assert?
90*/
91
Stefan Reinauera9424d52008-06-27 16:28:34 +000092#define ICH7_REG_SPIC 0x02 /* 16 Bits */
93#define SPIC_SCGO 0x0002
94#define SPIC_ACS 0x0004
95#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000096#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +000097
98#define ICH7_REG_SPIA 0x04 /* 32 Bits */
99#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
100#define ICH7_REG_PREOP 0x54 /* 16 Bits */
101#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
102#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
103
FENG yu ningc05a2952008-12-08 18:16:58 +0000104/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000105static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000106
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000107uint32_t ichspi_bbar = 0;
108
Michael Karchera4448d92010-07-22 18:04:15 +0000109static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000110
Dominik Geyerb46acba2008-05-16 12:55:55 +0000111typedef struct _OPCODE {
112 uint8_t opcode; //This commands spi opcode
113 uint8_t spi_type; //This commands spi type
114 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
115} OPCODE;
116
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000117/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000118 * Preop 1: Write Enable
119 * Preop 2: Write Status register enable
120 *
121 * OP 0: Write address
122 * OP 1: Read Address
123 * OP 2: ERASE block
124 * OP 3: Read Status register
125 * OP 4: Read ID
126 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000127 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000128 * OP 7: Chip erase
129 */
130typedef struct _OPCODES {
131 uint8_t preop[2];
132 OPCODE opcode[8];
133} OPCODES;
134
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000135static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000136
137/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000138static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000139{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000140 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000141}
142
Uwe Hermann09e04f72009-05-16 22:36:00 +0000143static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000144{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000145 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000146}
147
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000148#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X)
149#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X)
150#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000151
Dominik Geyerb46acba2008-05-16 12:55:55 +0000152/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000153static int find_opcode(OPCODES *op, uint8_t opcode);
154static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000155static int generate_opcodes(OPCODES * op);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000156static int program_opcodes(OPCODES * op);
Stefan Reinauer43119562008-11-02 19:51:50 +0000157static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000158 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000159
FENG yu ningf041e9b2008-12-15 02:32:11 +0000160/* for pairing opcodes with their required preop */
161struct preop_opcode_pair {
162 uint8_t preop;
163 uint8_t opcode;
164};
165
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000166/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000167const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000168 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
169 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
170 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
171 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
172 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
173 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000174 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
175 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000176 {JEDEC_EWSR, JEDEC_WRSR},
177 {0,}
178};
179
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000180/* Reasonable default configuration. Needs ad-hoc modifications if we
181 * encounter unlisted opcodes. Fun.
182 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000183static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000184 {
185 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000186 JEDEC_EWSR,
187 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000188 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000189 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000190 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000191 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000192 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000193 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000194 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000195 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000196 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
197 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198};
199
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000200static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000201
Uwe Hermann09e04f72009-05-16 22:36:00 +0000202static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000203{
204 int a;
205
206 for (a = 0; a < 8; a++) {
207 if (op->opcode[a].opcode == opcode)
208 return a;
209 }
210
211 return -1;
212}
213
Uwe Hermann09e04f72009-05-16 22:36:00 +0000214static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000215{
216 int a;
217
218 for (a = 0; a < 2; a++) {
219 if (op->preop[a] == preop)
220 return a;
221 }
222
223 return -1;
224}
225
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000226/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000227static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000228{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000229 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000230 uint16_t preop, optype;
231 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000232
233 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000234 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000235 return -1;
236 }
237
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000238 switch (spi_controller) {
239 case SPI_CONTROLLER_ICH7:
240 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000241 preop = REGREAD16(ICH7_REG_PREOP);
242 optype = REGREAD16(ICH7_REG_OPTYPE);
243 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
244 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
245 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000246 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000247 preop = REGREAD16(ICH9_REG_PREOP);
248 optype = REGREAD16(ICH9_REG_OPTYPE);
249 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
250 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
251 break;
252 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000253 msg_perr("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000254 return -1;
255 }
256
257 op->preop[0] = (uint8_t) preop;
258 op->preop[1] = (uint8_t) (preop >> 8);
259
260 for (a = 0; a < 8; a++) {
261 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
262 optype >>= 2;
263 }
264
265 for (a = 0; a < 4; a++) {
266 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
267 opmenu[0] >>= 8;
268 }
269
270 for (a = 4; a < 8; a++) {
271 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
272 opmenu[1] >>= 8;
273 }
274
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000275 /* No preopcodes used by default. */
276 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000277 op->opcode[a].atomic = 0;
278
FENG yu ningc05a2952008-12-08 18:16:58 +0000279 return 0;
280}
281
Dominik Geyerb46acba2008-05-16 12:55:55 +0000282int program_opcodes(OPCODES * op)
283{
284 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000285 uint16_t preop, optype;
286 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000287
288 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000289 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000290 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000291 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000292 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000293
Stefan Reinauera9424d52008-06-27 16:28:34 +0000294 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000295 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000296 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000297 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000298 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000299
Stefan Reinauera9424d52008-06-27 16:28:34 +0000300 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000301 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000302 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000303 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000304 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000305
Dominik Geyerb46acba2008-05-16 12:55:55 +0000306 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000307 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000308 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000309 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000310 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000311
Sean Nelson316a29f2010-05-07 20:09:04 +0000312 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000313 switch (spi_controller) {
314 case SPI_CONTROLLER_ICH7:
315 case SPI_CONTROLLER_VIA:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000316 REGWRITE16(ICH7_REG_PREOP, preop);
317 REGWRITE16(ICH7_REG_OPTYPE, optype);
318 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
319 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
320 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000321 case SPI_CONTROLLER_ICH9:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000322 REGWRITE16(ICH9_REG_PREOP, preop);
323 REGWRITE16(ICH9_REG_OPTYPE, optype);
324 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
325 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
326 break;
327 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000328 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000329 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000330 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000331
332 return 0;
333}
334
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000335/*
336 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
337 * it didn't stick.
338 */
339void ich_set_bbar(uint32_t minaddr)
340{
341 switch (spi_controller) {
342 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000343 mmio_writel(minaddr, ich_spibar + 0x50);
344 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000345 /* We don't have any option except complaining. */
346 if (ichspi_bbar != minaddr)
347 msg_perr("Setting BBAR failed!\n");
348 break;
349 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000350 mmio_writel(minaddr, ich_spibar + 0xA0);
351 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000352 /* We don't have any option except complaining. */
353 if (ichspi_bbar != minaddr)
354 msg_perr("Setting BBAR failed!\n");
355 break;
356 default:
357 /* Not sure if BBAR actually exists on VIA. */
358 msg_pdbg("Setting BBAR is not implemented for VIA yet.\n");
359 break;
360 }
361}
362
FENG yu ningf041e9b2008-12-15 02:32:11 +0000363/* This function generates OPCODES from or programs OPCODES to ICH according to
364 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000365 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000366 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000367 */
Michael Karchera4448d92010-07-22 18:04:15 +0000368static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000369{
370 int rc = 0;
371 OPCODES *curopcodes_done;
372
373 if (curopcodes)
374 return 0;
375
376 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000377 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000378 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000379 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000380 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000381 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000382 curopcodes_done = &O_ST_M25P;
383 rc = program_opcodes(curopcodes_done);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000384 /* Technically not part of opcode init, but it allows opcodes
385 * to run without transaction errors by setting the lowest
386 * allowed address to zero.
387 */
388 ich_set_bbar(0);
FENG yu ningc05a2952008-12-08 18:16:58 +0000389 }
390
391 if (rc) {
392 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000393 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000394 return 1;
395 } else {
396 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000397 msg_pdbg("done\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000398 return 0;
399 }
400}
401
Stefan Reinauer43119562008-11-02 19:51:50 +0000402static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000403 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000404{
405 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000406 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000407 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000408 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000409 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000410 uint64_t opmenu;
411 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000412
413 /* Is it a write command? */
414 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
415 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
416 write_cmd = 1;
417 }
418
419 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000420 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000421
422 /* Program data into FDATA0 to N */
423 if (write_cmd && (datalength != 0)) {
424 temp32 = 0;
425 for (a = 0; a < datalength; a++) {
426 if ((a % 4) == 0) {
427 temp32 = 0;
428 }
429
430 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
431
432 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000433 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
434 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000435 }
436 }
437 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000438 REGWRITE32(ICH7_REG_SPID0 +
439 ((a - 1) - ((a - 1) % 4)), temp32);
440 }
441
442 }
443
444 /* Assemble SPIS */
445 temp16 = 0;
446 /* clear error status registers */
447 temp16 |= (SPIS_CDS + SPIS_FCERR);
448 REGWRITE16(ICH7_REG_SPIS, temp16);
449
450 /* Assemble SPIC */
451 temp16 = 0;
452
453 if (datalength != 0) {
454 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000455 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000456 }
457
458 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000459 opmenu = REGREAD32(ICH7_REG_OPMENU);
460 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
461
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000462 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
463 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000464 break;
465 }
466 opmenu >>= 8;
467 }
468 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000469 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000470 return 1;
471 }
472 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000473
474 /* Handle Atomic */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000475 switch (op.atomic) {
476 case 2:
477 /* Select second preop. */
478 temp16 |= SPIC_SPOP;
479 /* And fall through. */
480 case 1:
481 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000482 temp16 |= SPIC_ACS;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000483 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000484 }
485
486 /* Start */
487 temp16 |= SPIC_SCGO;
488
489 /* write it */
490 REGWRITE16(ICH7_REG_SPIC, temp16);
491
492 /* wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000493 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauera9424d52008-06-27 16:28:34 +0000494 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000495 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000496 }
497 if (!timeout) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000498 msg_perr("timeout\n");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000499 }
500
Sean Nelson316a29f2010-05-07 20:09:04 +0000501 /* FIXME: make sure we do not needlessly cause transaction errors. */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000502 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000503 msg_pdbg("Transaction error!\n");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000504 return 1;
505 }
506
507 if ((!write_cmd) && (datalength != 0)) {
508 for (a = 0; a < datalength; a++) {
509 if ((a % 4) == 0) {
510 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
511 }
512
513 data[a] =
514 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
515 >> ((a % 4) * 8);
516 }
517 }
518
519 return 0;
520}
521
Stefan Reinauer43119562008-11-02 19:51:50 +0000522static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000523 uint8_t datalength, uint8_t * data)
524{
525 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000526 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000527 uint32_t temp32;
528 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000529 uint64_t opmenu;
530 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000531
532 /* Is it a write command? */
533 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
534 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
535 write_cmd = 1;
536 }
537
538 /* Programm Offset in Flash into FADDR */
539 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
540
541 /* Program data into FDATA0 to N */
542 if (write_cmd && (datalength != 0)) {
543 temp32 = 0;
544 for (a = 0; a < datalength; a++) {
545 if ((a % 4) == 0) {
546 temp32 = 0;
547 }
548
549 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
550
551 if ((a % 4) == 3) {
552 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
553 temp32);
554 }
555 }
556 if (((a - 1) % 4) != 3) {
557 REGWRITE32(ICH9_REG_FDATA0 +
558 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000559 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000560 }
561
562 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000563 /* keep reserved bits (23-19,7,0) */
564 temp32 = REGREAD32(ICH9_REG_SSFS);
565 temp32 &= 0xF8008100;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000566
567 /* clear error status registers */
568 temp32 |= (SSFS_CDS + SSFS_FCERR);
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000569 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000570 temp32 |= SSFC_SCF_20MHZ;
571
572 if (datalength != 0) {
573 uint32_t datatemp;
574 temp32 |= SSFC_DS;
575 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
576 temp32 |= datatemp;
577 }
578
579 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000580 opmenu = REGREAD32(ICH9_REG_OPMENU);
581 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
582
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000583 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
584 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000585 break;
586 }
587 opmenu >>= 8;
588 }
589 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000590 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000591 return 1;
592 }
593 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000594
595 /* Handle Atomic */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000596 switch (op.atomic) {
597 case 2:
598 /* Select second preop. */
599 temp32 |= SSFC_SPOP;
600 /* And fall through. */
601 case 1:
602 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000603 temp32 |= SSFC_ACS;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000604 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000605 }
606
607 /* Start */
608 temp32 |= SSFC_SCGO;
609
610 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000611 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000612
613 /*wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000614 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000615 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000616 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000617 }
618 if (!timeout) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000619 msg_perr("timeout\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000620 }
621
Sean Nelson316a29f2010-05-07 20:09:04 +0000622 /* FIXME make sure we do not needlessly cause transaction errors. */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000623 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000624 msg_pdbg("Transaction error!\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000625 return 1;
626 }
627
628 if ((!write_cmd) && (datalength != 0)) {
629 for (a = 0; a < datalength; a++) {
630 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000631 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000632 }
633
634 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000635 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
636 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000637 }
638 }
639
640 return 0;
641}
642
Stefan Reinauer43119562008-11-02 19:51:50 +0000643static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000644 uint8_t datalength, uint8_t * data)
645{
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000646 switch (spi_controller) {
647 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000648 if (datalength > 16) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000649 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000650 "opcode 0x%02x, got datalength=%i, want <=16\n",
651 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000652 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000653 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000654 return ich7_run_opcode(op, offset, datalength, data, 16);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000655 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000656 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000657 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000658 "opcode 0x%02x, got datalength=%i, want <=16\n",
659 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000660 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000661 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000662 return ich7_run_opcode(op, offset, datalength, data, 64);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000663 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000664 if (datalength > 64) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000665 msg_perr("%s: Internal command size error for "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000666 "opcode 0x%02x, got datalength=%i, want <=16\n",
667 __func__, op.opcode, datalength);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000668 return SPI_INVALID_LENGTH;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000669 }
Stefan Reinauer43119562008-11-02 19:51:50 +0000670 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000671 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000672 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000673 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000674
675 /* If we ever get here, something really weird happened */
676 return -1;
677}
678
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000679int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000680{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000681 int maxdata = 64;
682
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000683 if (spi_controller == SPI_CONTROLLER_VIA)
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000684 maxdata = 16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000685
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000686 return spi_read_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000687}
688
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000689int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000690{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000691 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000692
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000693 if (spi_controller == SPI_CONTROLLER_VIA)
694 maxdata = 16;
695
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000696 return spi_write_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000697}
698
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000699int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000700 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000701{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000702 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000703 int opcode_index = -1;
704 const unsigned char cmd = *writearr;
705 OPCODE *opcode;
706 uint32_t addr = 0;
707 uint8_t *data;
708 int count;
709
Dominik Geyerb46acba2008-05-16 12:55:55 +0000710 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000711 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000712 if (opcode_index == -1) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000713 /* FIXME: Reprogram opcodes if possible. Autodetect type of
714 * opcode by checking readcnt/writecnt.
715 */
Sean Nelson316a29f2010-05-07 20:09:04 +0000716 msg_pdbg("Invalid OPCODE 0x%02x\n", cmd);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000717 return SPI_INVALID_OPCODE;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000718 }
719
720 opcode = &(curopcodes->opcode[opcode_index]);
721
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000722 /* The following valid writecnt/readcnt combinations exist:
723 * writecnt = 4, readcnt >= 0
724 * writecnt = 1, readcnt >= 0
725 * writecnt >= 4, readcnt = 0
726 * writecnt >= 1, readcnt = 0
727 * writecnt >= 1 is guaranteed for all commands.
728 */
729 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
730 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000731 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000732 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
733 writecnt);
734 return SPI_INVALID_LENGTH;
735 }
736 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
737 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000738 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000739 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
740 writecnt);
741 return SPI_INVALID_LENGTH;
742 }
743 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
744 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000745 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000746 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
747 writecnt);
748 return SPI_INVALID_LENGTH;
749 }
750 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
751 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
752 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000753 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000754 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
755 readcnt);
756 return SPI_INVALID_LENGTH;
757 }
758
Dominik Geyerb46acba2008-05-16 12:55:55 +0000759 /* if opcode-type requires an address */
760 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
761 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000762 addr = (writearr[1] << 16) |
763 (writearr[2] << 8) | (writearr[3] << 0);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000764 switch (spi_controller) {
765 case SPI_CONTROLLER_ICH7:
766 case SPI_CONTROLLER_ICH9:
767 if (addr < ichspi_bbar) {
768 msg_perr("%s: Address 0x%06x below allowed "
769 "range 0x%06x-0xffffff\n", __func__,
770 addr, ichspi_bbar);
771 return SPI_INVALID_ADDRESS;
772 }
773 break;
774 default:
775 break;
776 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000777 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000778
Dominik Geyerb46acba2008-05-16 12:55:55 +0000779 /* translate read/write array/count */
780 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000781 data = (uint8_t *) (writearr + 1);
782 count = writecnt - 1;
783 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
784 data = (uint8_t *) (writearr + 4);
785 count = writecnt - 4;
786 } else {
787 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000788 count = readcnt;
789 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000790
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000791 result = run_opcode(*opcode, addr, count, data);
792 if (result) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000793 msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000794 }
795
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000796 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000797}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000798
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000799int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000800{
801 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000802 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000803 int oppos, preoppos;
804 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000805 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000806 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000807 preoppos = find_preop(curopcodes, cmds->writearr[0]);
808 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000809 if ((oppos == -1) && (preoppos != -1)) {
810 /* Current command is listed as preopcode in
811 * ICH struct OPCODES, but next command is not
812 * listed as opcode in that struct.
813 * Check for command sanity, then
814 * try to reprogram the ICH opcode list.
815 */
816 if (find_preop(curopcodes,
817 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000818 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000819 "preopcodes 0x%02x and 0x%02x, "
820 "ignoring the first.\n",
821 __func__, cmds->writearr[0],
822 (cmds + 1)->writearr[0]);
823 continue;
824 }
825 /* If the chipset is locked down, we'll fail
826 * during execution of the next command anyway.
827 * No need to bother with fixups.
828 */
829 if (!ichspi_lock) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000830 msg_pdbg("%s: FIXME: Add on-the-fly"
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000831 " reprogramming of the "
832 "chipset opcode list.\n",
833 __func__);
834 /* FIXME: Reprogram opcode menu.
835 * Find a less-useful opcode, replace it
836 * with the wanted opcode, detect optype
837 * and reprogram the opcode menu.
838 * Update oppos so the next if-statement
839 * can do something useful.
840 */
841 //curopcodes.opcode[lessusefulindex] = (cmds + 1)->writearr[0]);
842 //update_optypes(curopcodes);
843 //program_opcodes(curopcodes);
844 //oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
845 continue;
846 }
847 }
848 if ((oppos != -1) && (preoppos != -1)) {
849 /* Current command is listed as preopcode in
850 * ICH struct OPCODES and next command is listed
851 * as opcode in that struct. Match them up.
852 */
853 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000854 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000855 }
856 /* If none of the above if-statements about oppos or
857 * preoppos matched, this is a normal opcode.
858 */
859 }
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000860 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
861 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000862 /* Reset the type of all opcodes to non-atomic. */
863 for (i = 0; i < 8; i++)
864 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000865 }
866 return ret;
867}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000868
Michael Karchera4448d92010-07-22 18:04:15 +0000869#define ICH_BMWAG(x) ((x >> 24) & 0xff)
870#define ICH_BMRAG(x) ((x >> 16) & 0xff)
871#define ICH_BRWA(x) ((x >> 8) & 0xff)
872#define ICH_BRRA(x) ((x >> 0) & 0xff)
873
874#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff)
875#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff)
876
877static void do_ich9_spi_frap(uint32_t frap, int i)
878{
879 const char *access_names[4] = {
880 "locked", "read-only", "write-only", "read-write"
881 };
882 const char *region_names[5] = {
883 "Flash Descriptor", "BIOS", "Management Engine",
884 "Gigabit Ethernet", "Platform Data"
885 };
886 uint32_t base, limit;
887 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
888 (((ICH_BRRA(frap) >> i) & 1) << 0);
889 int offset = 0x54 + i * 4;
890 uint32_t freg = mmio_readl(ich_spibar + offset);
891
892 msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n",
893 offset, freg, i, region_names[i]);
894
895 base = ICH_FREG_BASE(freg);
896 limit = ICH_FREG_LIMIT(freg);
897 if (base == 0x1fff && limit == 0) {
898 /* this FREG is disabled */
899 msg_pdbg("%s region is unused.\n", region_names[i]);
900 return;
901 }
902
903 msg_pdbg("0x%08x-0x%08x is %s\n",
904 (base << 12), (limit << 12) | 0x0fff,
905 access_names[rwperms]);
906}
907
908int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
909 int ich_generation)
910{
911 int i;
912 uint8_t old, new;
913 uint16_t spibar_offset, tmp2;
914 uint32_t tmp;
915
916 buses_supported |= CHIP_BUSTYPE_SPI;
917 switch (ich_generation) {
918 case 7:
919 spi_controller = SPI_CONTROLLER_ICH7;
920 spibar_offset = 0x3020;
921 break;
922 case 8:
923 spi_controller = SPI_CONTROLLER_ICH9;
924 spibar_offset = 0x3020;
925 break;
926 case 9:
927 case 10:
928 default: /* Future version might behave the same */
929 spi_controller = SPI_CONTROLLER_ICH9;
930 spibar_offset = 0x3800;
931 break;
932 }
933
934 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
935 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
936
937 /* Assign Virtual Address */
938 ich_spibar = rcrb + spibar_offset;
939
940 switch (spi_controller) {
941 case SPI_CONTROLLER_ICH7:
942 msg_pdbg("0x00: 0x%04x (SPIS)\n",
943 mmio_readw(ich_spibar + 0));
944 msg_pdbg("0x02: 0x%04x (SPIC)\n",
945 mmio_readw(ich_spibar + 2));
946 msg_pdbg("0x04: 0x%08x (SPIA)\n",
947 mmio_readl(ich_spibar + 4));
948 for (i = 0; i < 8; i++) {
949 int offs;
950 offs = 8 + (i * 8);
951 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
952 mmio_readl(ich_spibar + offs), i);
953 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
954 mmio_readl(ich_spibar + offs + 4), i);
955 }
956 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
957 msg_pdbg("0x50: 0x%08x (BBAR)\n",
958 ichspi_bbar);
959 msg_pdbg("0x54: 0x%04x (PREOP)\n",
960 mmio_readw(ich_spibar + 0x54));
961 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
962 mmio_readw(ich_spibar + 0x56));
963 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
964 mmio_readl(ich_spibar + 0x58));
965 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
966 mmio_readl(ich_spibar + 0x5c));
967 for (i = 0; i < 4; i++) {
968 int offs;
969 offs = 0x60 + (i * 4);
970 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
971 mmio_readl(ich_spibar + offs), i);
972 }
973 msg_pdbg("\n");
974 if (mmio_readw(ich_spibar) & (1 << 15)) {
975 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
976 ichspi_lock = 1;
977 }
978 ich_init_opcodes();
979 break;
980 case SPI_CONTROLLER_ICH9:
981 tmp2 = mmio_readw(ich_spibar + 4);
982 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
983 msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
984 msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
985 msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
986 msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
987 msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
988 msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
989 msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
990 msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
991
992 tmp = mmio_readl(ich_spibar + 0x50);
993 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
994 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
995 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
996 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
997 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
998
999 /* print out the FREGx registers along with FRAP access bits */
1000 for(i = 0; i < 5; i++)
1001 do_ich9_spi_frap(tmp, i);
1002
1003 msg_pdbg("0x74: 0x%08x (PR0)\n",
1004 mmio_readl(ich_spibar + 0x74));
1005 msg_pdbg("0x78: 0x%08x (PR1)\n",
1006 mmio_readl(ich_spibar + 0x78));
1007 msg_pdbg("0x7C: 0x%08x (PR2)\n",
1008 mmio_readl(ich_spibar + 0x7C));
1009 msg_pdbg("0x80: 0x%08x (PR3)\n",
1010 mmio_readl(ich_spibar + 0x80));
1011 msg_pdbg("0x84: 0x%08x (PR4)\n",
1012 mmio_readl(ich_spibar + 0x84));
1013 msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n",
1014 mmio_readl(ich_spibar + 0x90));
1015 msg_pdbg("0x94: 0x%04x (PREOP)\n",
1016 mmio_readw(ich_spibar + 0x94));
1017 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
1018 mmio_readw(ich_spibar + 0x96));
1019 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
1020 mmio_readl(ich_spibar + 0x98));
1021 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
1022 mmio_readl(ich_spibar + 0x9C));
1023 ichspi_bbar = mmio_readl(ich_spibar + 0xA0);
1024 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1025 ichspi_bbar);
1026 msg_pdbg("0xB0: 0x%08x (FDOC)\n",
1027 mmio_readl(ich_spibar + 0xB0));
1028 if (tmp2 & (1 << 15)) {
1029 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1030 ichspi_lock = 1;
1031 }
1032 ich_init_opcodes();
1033 break;
1034 default:
1035 /* Nothing */
1036 break;
1037 }
1038
1039 old = pci_read_byte(dev, 0xdc);
1040 msg_pdbg("SPI Read Configuration: ");
1041 new = (old >> 2) & 0x3;
1042 switch (new) {
1043 case 0:
1044 case 1:
1045 case 2:
1046 msg_pdbg("prefetching %sabled, caching %sabled, ",
1047 (new & 0x2) ? "en" : "dis",
1048 (new & 0x1) ? "dis" : "en");
1049 break;
1050 default:
1051 msg_pdbg("invalid prefetching/caching settings, ");
1052 break;
1053 }
1054 return 0;
1055}
1056
1057int via_init_spi(struct pci_dev *dev)
1058{
1059 uint32_t mmio_base;
1060
1061 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1062 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1063 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1064
1065 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1066 mmio_readw(ich_spibar + 0x6c));
1067
1068 /* Not sure if it speaks all these bus protocols. */
1069 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
1070 spi_controller = SPI_CONTROLLER_VIA;
1071 ich_init_opcodes();
1072
1073 return 0;
1074}
1075
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001076#endif