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Rudolf Marek525339c2009-05-17 19:46:43 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Rudolf Marek525339c2009-05-17 19:46:43 +000015 */
16
17/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
18
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000019#include "programmer.h"
Thomas Heijligen74b4aa02021-12-14 17:52:30 +010020#include "hwaccess_physmap.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010021#include "platform/pci.h"
Rudolf Marek525339c2009-05-17 19:46:43 +000022
23#define PCI_VENDOR_ID_SII 0x1095
24
David Hendricks8bb20212011-06-14 01:35:36 +000025#define SATASII_MEMMAP_SIZE 0x100
26
Stefan Tauner61b4cfa2012-08-25 02:07:20 +000027static uint8_t *sii_bar;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000028static uint16_t id;
Rudolf Marek525339c2009-05-17 19:46:43 +000029
Thomas Heijligencc853d82021-05-04 15:32:17 +020030static const struct dev_entry satas_sii[] = {
Michael Karcher84486392010-02-24 00:04:40 +000031 {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},
32 {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},
33 {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},
Uwe Hermannc2521ab2010-07-29 22:39:47 +000034 {0x1095, 0x3124, OK, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},
Michael Karcher84486392010-02-24 00:04:40 +000035 {0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},
Carl-Daniel Hailfinger9017cec2010-09-04 23:37:40 +000036 {0x1095, 0x3512, OK, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"},
Uwe Hermanneaefb482009-05-17 22:57:34 +000037
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000038 {0},
Rudolf Marek525339c2009-05-17 19:46:43 +000039};
40
Stefan Tauner61b4cfa2012-08-25 02:07:20 +000041static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
42static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000043static const struct par_master par_master_satasii = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020044 .chip_readb = satasii_chip_readb,
45 .chip_readw = fallback_chip_readw,
46 .chip_readl = fallback_chip_readl,
47 .chip_readn = fallback_chip_readn,
48 .chip_writeb = satasii_chip_writeb,
49 .chip_writew = fallback_chip_writew,
50 .chip_writel = fallback_chip_writel,
51 .chip_writen = fallback_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000052};
53
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +000054static uint32_t satasii_wait_done(void)
55{
56 uint32_t ctrl_reg;
57 int i = 0;
58 while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) {
59 if (++i > 10000) {
60 msg_perr("%s: control register stuck at %08x, ignoring.\n",
61 __func__, pci_mmio_readl(sii_bar));
62 break;
63 }
64 }
65 return ctrl_reg;
66}
67
Thomas Heijligencc853d82021-05-04 15:32:17 +020068static int satasii_init(void)
Rudolf Marek525339c2009-05-17 19:46:43 +000069{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000070 struct pci_dev *dev = NULL;
Rudolf Marek525339c2009-05-17 19:46:43 +000071 uint32_t addr;
72 uint16_t reg_offset;
73
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000074 dev = pcidev_init(satas_sii, PCI_BASE_ADDRESS_0);
75 if (!dev)
76 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000077
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000078 id = dev->device_id;
Rudolf Marek525339c2009-05-17 19:46:43 +000079
80 if ((id == 0x3132) || (id == 0x3124)) {
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000081 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000082 if (!addr)
83 return 1;
Rudolf Marek525339c2009-05-17 19:46:43 +000084 reg_offset = 0x70;
85 } else {
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000086 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
Niklas Söderlund89edf362013-08-23 23:29:23 +000087 if (!addr)
88 return 1;
Rudolf Marek525339c2009-05-17 19:46:43 +000089 reg_offset = 0x50;
90 }
91
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000092 sii_bar = rphysmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE);
93 if (sii_bar == ERROR_PTR)
94 return 1;
95 sii_bar += reg_offset;
Rudolf Marek525339c2009-05-17 19:46:43 +000096
Uwe Hermanneaefb482009-05-17 22:57:34 +000097 /* Check if ROM cycle are OK. */
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000098 if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +000099 msg_pwarn("Warning: Flash seems unconnected.\n");
Rudolf Marek525339c2009-05-17 19:46:43 +0000100
Anastasia Klimchukc1f2a472021-08-27 15:47:46 +1000101 return register_par_master(&par_master_satasii, BUS_PARALLEL, NULL);
Rudolf Marek525339c2009-05-17 19:46:43 +0000102}
103
Stefan Tauner61b4cfa2012-08-25 02:07:20 +0000104static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Rudolf Marek525339c2009-05-17 19:46:43 +0000105{
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000106 uint32_t data_reg;
107 uint32_t ctrl_reg = satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000108
Uwe Hermanneaefb482009-05-17 22:57:34 +0000109 /* Mask out unused/reserved bits, set writes and start transaction. */
Rudolf Marek525339c2009-05-17 19:46:43 +0000110 ctrl_reg &= 0xfcf80000;
111 ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
112
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000113 data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
114 pci_mmio_writel(data_reg, (sii_bar + 4));
115 pci_mmio_writel(ctrl_reg, sii_bar);
Rudolf Marek525339c2009-05-17 19:46:43 +0000116
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000117 satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000118}
119
Stefan Tauner61b4cfa2012-08-25 02:07:20 +0000120static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr)
Rudolf Marek525339c2009-05-17 19:46:43 +0000121{
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000122 uint32_t ctrl_reg = satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000123
Uwe Hermanneaefb482009-05-17 22:57:34 +0000124 /* Mask out unused/reserved bits, set reads and start transaction. */
Rudolf Marek525339c2009-05-17 19:46:43 +0000125 ctrl_reg &= 0xfcf80000;
126 ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
127
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000128 pci_mmio_writel(ctrl_reg, sii_bar);
Rudolf Marek525339c2009-05-17 19:46:43 +0000129
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000130 satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000131
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000132 return (pci_mmio_readl(sii_bar + 4)) & 0xff;
Rudolf Marek525339c2009-05-17 19:46:43 +0000133}
Thomas Heijligencc853d82021-05-04 15:32:17 +0200134
135const struct programmer_entry programmer_satasii = {
136 .name = "satasii",
137 .type = PCI,
138 .devs.dev = satas_sii,
139 .init = satasii_init,
140 .map_flash_region = fallback_map,
141 .unmap_flash_region = fallback_unmap,
142 .delay = internal_delay,
143};