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Rudolf Marek525339c2009-05-17 19:46:43 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Rudolf Marek525339c2009-05-17 19:46:43 +000015 */
16
17/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
18
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000019#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000020#include "hwaccess.h"
Rudolf Marek525339c2009-05-17 19:46:43 +000021
22#define PCI_VENDOR_ID_SII 0x1095
23
David Hendricks8bb20212011-06-14 01:35:36 +000024#define SATASII_MEMMAP_SIZE 0x100
25
Stefan Tauner61b4cfa2012-08-25 02:07:20 +000026static uint8_t *sii_bar;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000027static uint16_t id;
Rudolf Marek525339c2009-05-17 19:46:43 +000028
Thomas Heijligencc853d82021-05-04 15:32:17 +020029static const struct dev_entry satas_sii[] = {
Michael Karcher84486392010-02-24 00:04:40 +000030 {0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},
31 {0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},
32 {0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},
Uwe Hermannc2521ab2010-07-29 22:39:47 +000033 {0x1095, 0x3124, OK, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},
Michael Karcher84486392010-02-24 00:04:40 +000034 {0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},
Carl-Daniel Hailfinger9017cec2010-09-04 23:37:40 +000035 {0x1095, 0x3512, OK, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"},
Uwe Hermanneaefb482009-05-17 22:57:34 +000036
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000037 {0},
Rudolf Marek525339c2009-05-17 19:46:43 +000038};
39
Stefan Tauner61b4cfa2012-08-25 02:07:20 +000040static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
41static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000042static const struct par_master par_master_satasii = {
Thomas Heijligen43040f22022-06-23 14:38:35 +020043 .chip_readb = satasii_chip_readb,
44 .chip_readw = fallback_chip_readw,
45 .chip_readl = fallback_chip_readl,
46 .chip_readn = fallback_chip_readn,
47 .chip_writeb = satasii_chip_writeb,
48 .chip_writew = fallback_chip_writew,
49 .chip_writel = fallback_chip_writel,
50 .chip_writen = fallback_chip_writen,
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000051};
52
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +000053static uint32_t satasii_wait_done(void)
54{
55 uint32_t ctrl_reg;
56 int i = 0;
57 while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) {
58 if (++i > 10000) {
59 msg_perr("%s: control register stuck at %08x, ignoring.\n",
60 __func__, pci_mmio_readl(sii_bar));
61 break;
62 }
63 }
64 return ctrl_reg;
65}
66
Thomas Heijligencc853d82021-05-04 15:32:17 +020067static int satasii_init(void)
Rudolf Marek525339c2009-05-17 19:46:43 +000068{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000069 struct pci_dev *dev = NULL;
Rudolf Marek525339c2009-05-17 19:46:43 +000070 uint32_t addr;
71 uint16_t reg_offset;
72
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000073 if (rget_io_perms())
74 return 1;
Rudolf Marek525339c2009-05-17 19:46:43 +000075
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000076 dev = pcidev_init(satas_sii, PCI_BASE_ADDRESS_0);
77 if (!dev)
78 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000079
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000080 id = dev->device_id;
Rudolf Marek525339c2009-05-17 19:46:43 +000081
82 if ((id == 0x3132) || (id == 0x3124)) {
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000083 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000084 if (!addr)
85 return 1;
Rudolf Marek525339c2009-05-17 19:46:43 +000086 reg_offset = 0x70;
87 } else {
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000088 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
Niklas Söderlund89edf362013-08-23 23:29:23 +000089 if (!addr)
90 return 1;
Rudolf Marek525339c2009-05-17 19:46:43 +000091 reg_offset = 0x50;
92 }
93
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000094 sii_bar = rphysmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE);
95 if (sii_bar == ERROR_PTR)
96 return 1;
97 sii_bar += reg_offset;
Rudolf Marek525339c2009-05-17 19:46:43 +000098
Uwe Hermanneaefb482009-05-17 22:57:34 +000099 /* Check if ROM cycle are OK. */
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000100 if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000101 msg_pwarn("Warning: Flash seems unconnected.\n");
Rudolf Marek525339c2009-05-17 19:46:43 +0000102
Anastasia Klimchukc1f2a472021-08-27 15:47:46 +1000103 return register_par_master(&par_master_satasii, BUS_PARALLEL, NULL);
Rudolf Marek525339c2009-05-17 19:46:43 +0000104}
105
Stefan Tauner61b4cfa2012-08-25 02:07:20 +0000106static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Rudolf Marek525339c2009-05-17 19:46:43 +0000107{
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000108 uint32_t data_reg;
109 uint32_t ctrl_reg = satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000110
Uwe Hermanneaefb482009-05-17 22:57:34 +0000111 /* Mask out unused/reserved bits, set writes and start transaction. */
Rudolf Marek525339c2009-05-17 19:46:43 +0000112 ctrl_reg &= 0xfcf80000;
113 ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
114
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000115 data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
116 pci_mmio_writel(data_reg, (sii_bar + 4));
117 pci_mmio_writel(ctrl_reg, sii_bar);
Rudolf Marek525339c2009-05-17 19:46:43 +0000118
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000119 satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000120}
121
Stefan Tauner61b4cfa2012-08-25 02:07:20 +0000122static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr)
Rudolf Marek525339c2009-05-17 19:46:43 +0000123{
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000124 uint32_t ctrl_reg = satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000125
Uwe Hermanneaefb482009-05-17 22:57:34 +0000126 /* Mask out unused/reserved bits, set reads and start transaction. */
Rudolf Marek525339c2009-05-17 19:46:43 +0000127 ctrl_reg &= 0xfcf80000;
128 ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
129
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000130 pci_mmio_writel(ctrl_reg, sii_bar);
Rudolf Marek525339c2009-05-17 19:46:43 +0000131
Carl-Daniel Hailfinger250c3212012-08-29 03:41:57 +0000132 satasii_wait_done();
Rudolf Marek525339c2009-05-17 19:46:43 +0000133
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000134 return (pci_mmio_readl(sii_bar + 4)) & 0xff;
Rudolf Marek525339c2009-05-17 19:46:43 +0000135}
Thomas Heijligencc853d82021-05-04 15:32:17 +0200136
137const struct programmer_entry programmer_satasii = {
138 .name = "satasii",
139 .type = PCI,
140 .devs.dev = satas_sii,
141 .init = satasii_init,
142 .map_flash_region = fallback_map,
143 .unmap_flash_region = fallback_unmap,
144 .delay = internal_delay,
145};