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Uwe Hermannb4dcb712009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000021#if defined(__i386__) || defined(__x86_64__)
22
Uwe Hermannb4dcb712009-05-13 11:36:06 +000023#include <stdlib.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000024#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000025#include "programmer.h"
Uwe Hermannb4dcb712009-05-13 11:36:06 +000026
27#define BIOS_ROM_ADDR 0x04
28#define BIOS_ROM_DATA 0x08
29#define INT_STATUS 0x0e
Uwe Hermann8403ccb2009-05-16 21:39:19 +000030#define INTERNAL_CONFIG 0x00
Uwe Hermannb4dcb712009-05-13 11:36:06 +000031#define SELECT_REG_WINDOW 0x800
32
Uwe Hermannb4dcb712009-05-13 11:36:06 +000033#define PCI_VENDOR_ID_3COM 0x10b7
34
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000035static uint32_t internal_conf;
36static uint16_t id;
Uwe Hermann8403ccb2009-05-16 21:39:19 +000037
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000038const struct pcidev_status nics_3com[] = {
Uwe Hermannb4dcb712009-05-13 11:36:06 +000039 /* 3C90xB */
Michael Karcher84486392010-02-24 00:04:40 +000040 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
41 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
42 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
43 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
44 {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
45 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
46 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
47 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000048
49 /* 3C905C */
Michael Karcher84486392010-02-24 00:04:40 +000050 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000051
52 /* 3C980C */
Michael Karcher84486392010-02-24 00:04:40 +000053 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000054
55 {},
56};
57
58int nic3com_init(void)
59{
Uwe Hermanna0869322009-05-14 20:41:57 +000060 get_io_perms();
Uwe Hermannb4dcb712009-05-13 11:36:06 +000061
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000062 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com);
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000063
Uwe Hermann8403ccb2009-05-16 21:39:19 +000064 id = pcidev_dev->device_id;
65
66 /* 3COM 3C90xB cards need a special fixup. */
67 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +000068 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +000069 /* Select register window 3 and save the receiver status. */
70 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
71 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
72
73 /* Set receiver type to MII for full BIOS ROM access. */
74 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
75 }
Uwe Hermannb4dcb712009-05-13 11:36:06 +000076
77 /*
78 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
79 * cards form a 'register window' into one of multiple (usually 8)
80 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
81 */
82 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
83
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000084 buses_supported = CHIP_BUSTYPE_PARALLEL;
Peter Stuge02d0c1e2010-06-17 00:01:56 +000085 max_rom_decode.parallel = 128 * 1024;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000086
Uwe Hermannb4dcb712009-05-13 11:36:06 +000087 return 0;
88}
89
90int nic3com_shutdown(void)
91{
Uwe Hermann8403ccb2009-05-16 21:39:19 +000092 /* 3COM 3C90xB cards need a special fixup. */
93 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +000094 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +000095 /* Select register window 3 and restore the receiver status. */
96 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
97 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
98 }
99
Christian Ruppert0cdb0312009-05-14 18:57:26 +0000100 pci_cleanup(pacc);
Carl-Daniel Hailfingerdb41c592009-08-09 21:50:24 +0000101 release_io_perms();
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000102 return 0;
103}
104
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000105void nic3com_chip_writeb(uint8_t val, chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000106{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000107 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000108 OUTB(val, io_base_addr + BIOS_ROM_DATA);
109}
110
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000111uint8_t nic3com_chip_readb(const chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000112{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000113 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannc7e8a0c2009-05-19 14:14:21 +0000114 return INB(io_base_addr + BIOS_ROM_DATA);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000115}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000116
117#else
118#error PCI port I/O access is not supported on this architecture yet.
119#endif