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Ronald G. Minnichb1934902002-06-11 19:15:55 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnichb1934902002-06-11 19:15:55 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Ronald G. Minnichb1934902002-06-11 19:15:55 +00005 *
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000010 *
Uwe Hermannd1107642007-08-29 17:52:32 +000011 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ronald G. Minnichb1934902002-06-11 19:15:55 +000015 *
Uwe Hermannd1107642007-08-29 17:52:32 +000016 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnichb1934902002-06-11 19:15:55 +000019 */
20
21#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include "chipdrivers.h"
Ronald G. Minnichb1934902002-06-11 19:15:55 +000023
Michael Karcher1c296ca2009-11-27 17:49:42 +000024/* WARNING!
25 This chip uses the standard JEDEC Addresses in 16-bit mode as word
26 addresses. In byte mode, 0xAAA has to be used instead of 0x555 and
27 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC
28 functions. */
29
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000030void write_page_m29f400bt(chipaddr bios, uint8_t *src,
31 chipaddr dst, int page_size)
Uwe Hermann51582f22007-08-23 10:20:40 +000032{
33 int i;
34
35 for (i = 0; i < page_size; i++) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000036 chip_writeb(0xAA, bios + 0xAAA);
37 chip_writeb(0x55, bios + 0x555);
38 chip_writeb(0xA0, bios + 0xAAA);
Uwe Hermann51582f22007-08-23 10:20:40 +000039
40 /* transfer data from source to destination */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000041 chip_writeb(*src, dst);
Uwe Hermannfd374142007-08-23 15:20:38 +000042 toggle_ready_jedec(dst);
Sean Nelsoned479d22010-03-24 23:14:32 +000043 msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000044 (dst - bios), chip_readb(dst), *src);
Uwe Hermann51582f22007-08-23 10:20:40 +000045 dst++;
46 src++;
47 }
48}
49
Ollie Lho761bf1b2004-03-20 16:46:10 +000050int probe_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000051{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000052 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +000053 uint8_t id1, id2;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000054
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000055 chip_writeb(0xAA, bios + 0xAAA);
56 chip_writeb(0x55, bios + 0x555);
57 chip_writeb(0x90, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000058
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000059 programmer_delay(10);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000060
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000061 id1 = chip_readb(bios);
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +000062 /* The data sheet says id2 is at (bios + 0x01) and id2 listed in
63 * flash.h does not match. It should be possible to use JEDEC probe.
64 */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000065 id2 = chip_readb(bios + 0x02);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000066
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000067 chip_writeb(0xAA, bios + 0xAAA);
68 chip_writeb(0x55, bios + 0x555);
69 chip_writeb(0xF0, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000070
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000071 programmer_delay(10);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000072
Sean Nelsoned479d22010-03-24 23:14:32 +000073 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Ronald G. Minnichd4228fd2003-02-28 17:21:38 +000074
Ronald G. Minnichb1934902002-06-11 19:15:55 +000075 if (id1 == flash->manufacture_id && id2 == flash->model_id)
76 return 1;
77
78 return 0;
79}
80
Ollie Lho761bf1b2004-03-20 16:46:10 +000081int erase_m29f400bt(struct flashchip *flash)
Ronald G. Minnichb1934902002-06-11 19:15:55 +000082{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000083 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +000084
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000085 chip_writeb(0xAA, bios + 0xAAA);
86 chip_writeb(0x55, bios + 0x555);
87 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000088
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000089 chip_writeb(0xAA, bios + 0xAAA);
90 chip_writeb(0x55, bios + 0x555);
91 chip_writeb(0x10, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +000092
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000093 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +000094 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000095
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000096 if (check_erased_range(flash, 0, flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +000097 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +000098 return -1;
99 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000100 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000101}
102
Sean Nelson6b11ad22009-12-23 17:05:59 +0000103int block_erase_m29f400bt(struct flashchip *flash, unsigned int start, unsigned int len)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000104{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000105 chipaddr bios = flash->virtual_memory;
106 chipaddr dst = bios + start;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000107
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000108 chip_writeb(0xAA, bios + 0xAAA);
109 chip_writeb(0x55, bios + 0x555);
110 chip_writeb(0x80, bios + 0xAAA);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000111
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000112 chip_writeb(0xAA, bios + 0xAAA);
113 chip_writeb(0x55, bios + 0x555);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000114 chip_writeb(0x30, dst);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000115
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000116 programmer_delay(10);
Uwe Hermannfd374142007-08-23 15:20:38 +0000117 toggle_ready_jedec(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000118
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000119 if (check_erased_range(flash, start, len)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000120 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000121 return -1;
122 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000123 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000124}
125
Sean Nelson6b11ad22009-12-23 17:05:59 +0000126int block_erase_chip_m29f400bt(struct flashchip *flash, unsigned int address, unsigned int blocklen)
127{
128 if ((address != 0) || (blocklen != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000129 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson6b11ad22009-12-23 17:05:59 +0000130 __func__);
131 return -1;
132 }
133 return erase_m29f400bt(flash);
134}
135
Ollie Lho184a4042005-11-26 21:55:36 +0000136int write_m29f400bt(struct flashchip *flash, uint8_t *buf)
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000137{
138 int i;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000139 int total_size = flash->total_size * 1024;
140 int page_size = flash->page_size;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000141 chipaddr bios = flash->virtual_memory;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000142
Ollie Lho761bf1b2004-03-20 16:46:10 +0000143 for (i = 0; i < (total_size / page_size) - 1; i++) {
Ollie Lho761bf1b2004-03-20 16:46:10 +0000144 write_page_m29f400bt(bios, buf + i * page_size,
145 bios + i * page_size, page_size);
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000146 }
147
Uwe Hermanna7e05482007-05-09 10:17:44 +0000148 write_page_m29f400bt(bios, buf + 0x70000, bios + 0x70000, 32 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000149
Uwe Hermanna7e05482007-05-09 10:17:44 +0000150 write_page_m29f400bt(bios, buf + 0x78000, bios + 0x78000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000151
Uwe Hermanna7e05482007-05-09 10:17:44 +0000152 write_page_m29f400bt(bios, buf + 0x7a000, bios + 0x7a000, 8 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000153
Uwe Hermanna7e05482007-05-09 10:17:44 +0000154 write_page_m29f400bt(bios, buf + 0x7c000, bios + 0x7c000, 16 * 1024);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000155
Uwe Hermannffec5f32007-08-23 16:08:21 +0000156 return 0;
Ronald G. Minnichb1934902002-06-11 19:15:55 +0000157}