blob: 76e48615c28c7dcea58bea09911535e78be77c08 [file] [log] [blame]
Donald Huang44ebb042011-02-22 17:16:34 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
6 * Copyright (C) 2008 coresystems GmbH
7 * Copyright (C) 2010 Google Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23/*
24 * Contains the ITE IT85* SPI specific routines
25 */
26
27#if defined(__i386__) || defined(__x86_64__)
28
29#include <string.h>
David Hendricks4e748392011-02-28 23:58:15 +000030#include <stdio.h>
Donald Huang44ebb042011-02-22 17:16:34 +000031#include <stdlib.h>
32#include "flash.h"
33#include "chipdrivers.h"
34#include "spi.h"
35#include "programmer.h"
36
David Hendricks4e748392011-02-28 23:58:15 +000037#define MAX_TIMEOUT 100000
38#define MAX_TRY 5
39
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000040/* Constants for I/O ports */
Donald Huang44ebb042011-02-22 17:16:34 +000041#define ITE_SUPERIO_PORT1 0x2e
42#define ITE_SUPERIO_PORT2 0x4e
43
44/* Legacy I/O */
David Hendricks4e748392011-02-28 23:58:15 +000045#define LEGACY_KBC_PORT_DATA 0x60
46#define LEGACY_KBC_PORT_CMD 0x64
Donald Huang44ebb042011-02-22 17:16:34 +000047
48/* Constants for Logical Device registers */
49#define LDNSEL 0x07
Donald Huang44ebb042011-02-22 17:16:34 +000050
51/* These are standard Super I/O 16-bit base address registers */
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000052#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */
53#define SHM_IO_BAR1 0x61
Donald Huang44ebb042011-02-22 17:16:34 +000054
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000055/* The 8042 keyboard controller uses an input buffer and an output buffer to
56 * communicate with the host CPU. Both buffers are 1-byte depth. That means
57 * IBF is set to 1 when the host CPU sends a command to the input buffer
58 * of the EC. IBF is cleared to 0 once the command is read by the EC.
59 */
David Hendricks4e748392011-02-28 23:58:15 +000060#define KB_IBF (1 << 1) /* Input Buffer Full */
61#define KB_OBF (1 << 0) /* Output Buffer Full */
62
Donald Huang44ebb042011-02-22 17:16:34 +000063/* IT8502 supports two access modes:
64 * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode)
65 * LPC_IO: through I/O port (so called indirect memory)
66 */
67#undef LPC_MEMORY
68#define LPC_IO
69
70#ifdef LPC_IO
71/* macro to fill in indirect-access registers. */
72#define INDIRECT_A0(base, value) OUTB(value, (base) + 0) /* little-endian */
73#define INDIRECT_A1(base, value) OUTB(value, (base) + 1)
74#define INDIRECT_A2(base, value) OUTB(value, (base) + 2)
75#define INDIRECT_A3(base, value) OUTB(value, (base) + 3)
76#define INDIRECT_READ(base) INB((base) + 4)
77#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4)
78#endif /* LPC_IO */
79
80#ifdef LPC_IO
81unsigned int shm_io_base;
82#endif
83unsigned char *ce_high, *ce_low;
84static int it85xx_scratch_rom_reenter = 0;
85
David Hendricks4e748392011-02-28 23:58:15 +000086/* This function will poll the keyboard status register until either
87 * an expected value shows up, or
88 * timeout reaches.
89 *
90 * Returns: 0 -- the expected value has shown.
91 * 1 -- timeout reached.
92 */
Uwe Hermann91f4afa2011-07-28 08:13:25 +000093static int wait_for(const unsigned int mask, const unsigned int expected_value,
94 const int timeout /* in usec */, const char *error_message,
95 const char *function_name, const int lineno)
96{
David Hendricks4e748392011-02-28 23:58:15 +000097 int time_passed;
98
99 for (time_passed = 0;; ++time_passed) {
100 if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value)
101 return 0;
102 if (time_passed >= timeout)
103 break;
104 programmer_delay(1);
105 }
106 if (error_message)
107 msg_perr("%s():%d %s", function_name, lineno, error_message);
108 return 1;
109}
110
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000111/* IT8502 employs a scratch RAM when flash is being updated. Call the following
David Hendricks4e748392011-02-28 23:58:15 +0000112 * two functions before/after flash erase/program. */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000113void it85xx_enter_scratch_rom(void)
Donald Huang44ebb042011-02-22 17:16:34 +0000114{
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000115 int ret, tries;
David Hendricks4e748392011-02-28 23:58:15 +0000116
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000117 msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000118 if (it85xx_scratch_rom_reenter > 0)
119 return;
David Hendricks4e748392011-02-28 23:58:15 +0000120
121#if 0
122 /* FIXME: this a workaround for the bug that SMBus signal would
123 * interfere the EC firmware update. Should be removed if
124 * we find out the root cause. */
125 ret = system("stop powerd >&2");
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000126 if (ret)
David Hendricks4e748392011-02-28 23:58:15 +0000127 msg_perr("Cannot stop powerd.\n");
David Hendricks4e748392011-02-28 23:58:15 +0000128#endif
129
130 for (tries = 0; tries < MAX_TRY; ++tries) {
131 /* Wait until IBF (input buffer) is not full. */
132 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
133 "* timeout at waiting for IBF==0.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000134 __func__, __LINE__))
David Hendricks4e748392011-02-28 23:58:15 +0000135 continue;
136
137 /* Copy EC firmware to SRAM. */
138 OUTB(0xb4, LEGACY_KBC_PORT_CMD);
139
140 /* Confirm EC has taken away the command. */
141 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
142 "* timeout at taking command.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000143 __func__, __LINE__))
David Hendricks4e748392011-02-28 23:58:15 +0000144 continue;
145
146 /* Waiting for OBF (output buffer) has data.
147 * Note sometimes the replied command might be stolen by kernel
148 * ISR so that it is okay as long as the command is 0xFA. */
149 if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0))
150 msg_pdbg("%s():%d * timeout at waiting for OBF.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000151 __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000152 if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) {
153 break;
154 } else {
155 msg_perr("%s():%d * not run on SRAM ret=%d\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000156 __func__, __LINE__, ret);
David Hendricks4e748392011-02-28 23:58:15 +0000157 continue;
158 }
159 }
160
161 if (tries < MAX_TRY) {
162 /* EC already runs on SRAM */
163 it85xx_scratch_rom_reenter++;
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000164 msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000165 } else {
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000166 msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000167 }
Donald Huang44ebb042011-02-22 17:16:34 +0000168}
169
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000170void it85xx_exit_scratch_rom(void)
Donald Huang44ebb042011-02-22 17:16:34 +0000171{
David Hendricks4e748392011-02-28 23:58:15 +0000172#if 0
173 int ret;
174#endif
175 int tries;
176
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000177 msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000178 if (it85xx_scratch_rom_reenter <= 0)
179 return;
David Hendricks4e748392011-02-28 23:58:15 +0000180
181 for (tries = 0; tries < MAX_TRY; ++tries) {
182 /* Wait until IBF (input buffer) is not full. */
183 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
184 "* timeout at waiting for IBF==0.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000185 __func__, __LINE__))
David Hendricks4e748392011-02-28 23:58:15 +0000186 continue;
187
188 /* Exit SRAM. Run on flash. */
189 OUTB(0xFE, LEGACY_KBC_PORT_CMD);
190
191 /* Confirm EC has taken away the command. */
192 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
193 "* timeout at taking command.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000194 __func__, __LINE__)) {
David Hendricks4e748392011-02-28 23:58:15 +0000195 /* We cannot ensure if EC has exited update mode.
196 * If EC is in normal mode already, a further 0xFE
197 * command will reboot system. So, exit loop here. */
198 tries = MAX_TRY;
199 break;
200 }
201
202 break;
203 }
204
205 if (tries < MAX_TRY) {
206 it85xx_scratch_rom_reenter = 0;
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000207 msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000208 } else {
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000209 msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000210 }
211
212#if 0
213 /* FIXME: this a workaround for the bug that SMBus signal would
214 * interfere the EC firmware update. Should be removed if
215 * we find out the root cause. */
216 ret = system("start powerd >&2");
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000217 if (ret)
David Hendricks4e748392011-02-28 23:58:15 +0000218 msg_perr("Cannot start powerd again.\n");
David Hendricks4e748392011-02-28 23:58:15 +0000219#endif
Donald Huang44ebb042011-02-22 17:16:34 +0000220}
221
David Hendricks8bb20212011-06-14 01:35:36 +0000222static int it85xx_shutdown(void *data)
223{
224 msg_pdbg("%s():%d\n", __func__, __LINE__);
225 it85xx_exit_scratch_rom();
226
227 return 0; /* FIXME: Should probably return something meaningful */
228}
229
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000230static int it85xx_spi_common_init(struct superio s)
Donald Huang44ebb042011-02-22 17:16:34 +0000231{
232 chipaddr base;
233
234 msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000235 s.vendor);
Donald Huang44ebb042011-02-22 17:16:34 +0000236
David Hendricks8bb20212011-06-14 01:35:36 +0000237 if (register_shutdown(it85xx_shutdown, NULL))
238 return 1;
239
Donald Huang44ebb042011-02-22 17:16:34 +0000240#ifdef LPC_IO
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000241 /* Get LPCPNP of SHM. That's big-endian. */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000242 sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
243 shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
244 sio_read(s.port, SHM_IO_BAR1);
Donald Huang44ebb042011-02-22 17:16:34 +0000245 msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
246 shm_io_base);
247
248 /* These pointers are not used directly. They will be send to EC's
249 * register for indirect access. */
250 base = 0xFFFFF000;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000251 ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
252 ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
Donald Huang44ebb042011-02-22 17:16:34 +0000253
254 /* pre-set indirect-access registers since in most of cases they are
255 * 0xFFFFxx00. */
256 INDIRECT_A0(shm_io_base, base & 0xFF);
257 INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
258 INDIRECT_A3(shm_io_base, (base >> 24));
259#endif
260#ifdef LPC_MEMORY
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +0000261 base = (chipaddr)programmer_map_flash_region("it85 communication",
262 0xFFFFF000, 0x1000);
Donald Huang44ebb042011-02-22 17:16:34 +0000263 msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
264 (unsigned int)base);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000265 ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
266 ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
Donald Huang44ebb042011-02-22 17:16:34 +0000267#endif
268
Donald Huang44ebb042011-02-22 17:16:34 +0000269 return 0;
270}
271
Michael Karcherb9dbe482011-05-11 17:07:07 +0000272static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
273 const unsigned char *writearr, unsigned char *readarr);
274
275static const struct spi_programmer spi_programmer_it85xx = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000276 .type = SPI_CONTROLLER_IT85XX,
277 .max_data_read = 64,
278 .max_data_write = 64,
279 .command = it85xx_spi_send_command,
280 .multicommand = default_spi_send_multicommand,
281 .read = default_spi_read,
282 .write_256 = default_spi_write_256,
Michael Karcherb9dbe482011-05-11 17:07:07 +0000283};
284
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000285int it85xx_spi_init(struct superio s)
Donald Huang44ebb042011-02-22 17:16:34 +0000286{
287 int ret;
288
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000289 if (!(buses_supported & BUS_FWH)) {
Donald Huang44ebb042011-02-22 17:16:34 +0000290 msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
291 return 1;
292 }
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000293 ret = it85xx_spi_common_init(s);
Donald Huang44ebb042011-02-22 17:16:34 +0000294 msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
295 if (!ret) {
296 msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
297 buses_supported);
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000298 if (buses_supported & BUS_FWH)
Donald Huang44ebb042011-02-22 17:16:34 +0000299 msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000300 /* Really leave FWH enabled? */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000301 /* Set this as SPI controller. */
Michael Karcherb9dbe482011-05-11 17:07:07 +0000302 register_spi_programmer(&spi_programmer_it85xx);
Donald Huang44ebb042011-02-22 17:16:34 +0000303 }
304 return ret;
305}
306
Donald Huang44ebb042011-02-22 17:16:34 +0000307/* According to ITE 8502 document, the procedure to follow mode is following:
308 * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
309 * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
310 * with data)
311 * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
312 * data from MISO)
313 */
Michael Karcherb9dbe482011-05-11 17:07:07 +0000314static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Donald Huang44ebb042011-02-22 17:16:34 +0000315 const unsigned char *writearr, unsigned char *readarr)
316{
317 int i;
318
319 it85xx_enter_scratch_rom();
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000320 /* exit scratch ROM ONLY when programmer shuts down. Otherwise, the
Donald Huang44ebb042011-02-22 17:16:34 +0000321 * temporary flash state may halt EC. */
322
323#ifdef LPC_IO
324 INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
325 INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
326 INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff);
327#endif
328#ifdef LPC_MEMORY
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +0000329 mmio_writeb(0, ce_high);
Donald Huang44ebb042011-02-22 17:16:34 +0000330#endif
331 for (i = 0; i < writecnt; ++i) {
332#ifdef LPC_IO
333 INDIRECT_WRITE(shm_io_base, writearr[i]);
334#endif
335#ifdef LPC_MEMORY
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +0000336 mmio_writeb(writearr[i], ce_low);
Donald Huang44ebb042011-02-22 17:16:34 +0000337#endif
338 }
339 for (i = 0; i < readcnt; ++i) {
340#ifdef LPC_IO
341 readarr[i] = INDIRECT_READ(shm_io_base);
342#endif
343#ifdef LPC_MEMORY
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +0000344 readarr[i] = mmio_readb(ce_low);
Donald Huang44ebb042011-02-22 17:16:34 +0000345#endif
346 }
David Hendricks4e748392011-02-28 23:58:15 +0000347#ifdef LPC_IO
348 INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
349 INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
350#endif
351#ifdef LPC_MEMORY
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +0000352 mmio_writeb(0, ce_high);
David Hendricks4e748392011-02-28 23:58:15 +0000353#endif
354
Donald Huang44ebb042011-02-22 17:16:34 +0000355 return 0;
356}
357
Donald Huang44ebb042011-02-22 17:16:34 +0000358#endif