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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Dominik Geyerb46acba2008-05-16 12:55:55 +00008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000022 */
23
24/*
25 * This module is designed for supporting the devices
26 * ST M25P40
27 * ST M25P80
28 * ST M25P16
29 * ST M25P32 already tested
30 * ST M25P64
31 * AT 25DF321 already tested
32 *
33 */
34
Dominik Geyerb46acba2008-05-16 12:55:55 +000035#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000036#include "flash.h"
37#include "spi.h"
38
Stefan Reinauera9424d52008-06-27 16:28:34 +000039/* ICH9 controller register definition */
40#define ICH9_REG_FADDR 0x08 /* 32 Bits */
41#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
42
43#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000044#define SSFS_SCIP 0x00000001
45#define SSFS_CDS 0x00000004
46#define SSFS_FCERR 0x00000008
47#define SSFS_AEL 0x00000010
Stefan Reinauera9424d52008-06-27 16:28:34 +000048
49#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000050#define SSFC_SCGO 0x00000200
51#define SSFC_ACS 0x00000400
52#define SSFC_SPOP 0x00000800
53#define SSFC_COP 0x00001000
54#define SSFC_DBC 0x00010000
55#define SSFC_DS 0x00400000
56#define SSFC_SME 0x00800000
57#define SSFC_SCF 0x01000000
58#define SSFC_SCF_20MHZ 0x00000000
59#define SSFC_SCF_33MHZ 0x01000000
Stefan Reinauera9424d52008-06-27 16:28:34 +000060
61#define ICH9_REG_PREOP 0x94 /* 16 Bits */
62#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
63#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +000064
65// ICH9R SPI commands
66#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
67#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
68#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
69#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
70
Stefan Reinauera9424d52008-06-27 16:28:34 +000071// ICH7 registers
72#define ICH7_REG_SPIS 0x00 /* 16 Bits */
73#define SPIS_SCIP 0x00000001
74#define SPIS_CDS 0x00000004
75#define SPIS_FCERR 0x00000008
76
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000077/* VIA SPI is compatible with ICH7, but maxdata
78 to transfer is 16 bytes.
79
80 DATA byte count on ICH7 is 8:13, on VIA 8:11
81
82 bit 12 is port select CS0 CS1
83 bit 13 is FAST READ enable
84 bit 7 is used with fast read and one shot controls CS de-assert?
85*/
86
Stefan Reinauera9424d52008-06-27 16:28:34 +000087#define ICH7_REG_SPIC 0x02 /* 16 Bits */
88#define SPIC_SCGO 0x0002
89#define SPIC_ACS 0x0004
90#define SPIC_SPOP 0x0008
Rudolf Marek3fdbccf2008-06-30 21:38:30 +000091#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +000092
93#define ICH7_REG_SPIA 0x04 /* 32 Bits */
94#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
95#define ICH7_REG_PREOP 0x54 /* 16 Bits */
96#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
97#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
98
FENG yu ningc05a2952008-12-08 18:16:58 +000099/* ICH SPI configuration lock-down. May be set during chipset enabling. */
100int ichspi_lock = 0;
101
Dominik Geyerb46acba2008-05-16 12:55:55 +0000102typedef struct _OPCODE {
103 uint8_t opcode; //This commands spi opcode
104 uint8_t spi_type; //This commands spi type
105 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
106} OPCODE;
107
108/* Opcode definition:
109 * Preop 1: Write Enable
110 * Preop 2: Write Status register enable
111 *
112 * OP 0: Write address
113 * OP 1: Read Address
114 * OP 2: ERASE block
115 * OP 3: Read Status register
116 * OP 4: Read ID
117 * OP 5: Write Status register
118 * OP 6: chip private (read JDEC id)
119 * OP 7: Chip erase
120 */
121typedef struct _OPCODES {
122 uint8_t preop[2];
123 OPCODE opcode[8];
124} OPCODES;
125
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000126static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000127
128/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000129static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000130{
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000131 return mmio_readl(spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000132}
133
Uwe Hermann09e04f72009-05-16 22:36:00 +0000134static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000135{
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000136 return mmio_readw(spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000137}
138
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000139#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X)
140#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X)
141#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000142
Dominik Geyerb46acba2008-05-16 12:55:55 +0000143/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000144static int find_opcode(OPCODES *op, uint8_t opcode);
145static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000146static int generate_opcodes(OPCODES * op);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000147static int program_opcodes(OPCODES * op);
Stefan Reinauer43119562008-11-02 19:51:50 +0000148static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000149 uint8_t datalength, uint8_t * data);
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000150static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000151 int offset, int maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000152
FENG yu ningf041e9b2008-12-15 02:32:11 +0000153/* for pairing opcodes with their required preop */
154struct preop_opcode_pair {
155 uint8_t preop;
156 uint8_t opcode;
157};
158
159struct preop_opcode_pair pops[] = {
160 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
161 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
162 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
163 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
164 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
165 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
166 {JEDEC_EWSR, JEDEC_WRSR},
167 {0,}
168};
169
Dominik Geyerb46acba2008-05-16 12:55:55 +0000170OPCODES O_ST_M25P = {
171 {
172 JEDEC_WREN,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000173 0},
Dominik Geyerb46acba2008-05-16 12:55:55 +0000174 {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000175 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
176 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
177 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
178 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000179 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000180 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
181 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
182 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
183 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000184};
185
FENG yu ningc05a2952008-12-08 18:16:58 +0000186OPCODES O_EXISTING = {};
187
Uwe Hermann09e04f72009-05-16 22:36:00 +0000188static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000189{
190 int a;
191
192 for (a = 0; a < 8; a++) {
193 if (op->opcode[a].opcode == opcode)
194 return a;
195 }
196
197 return -1;
198}
199
Uwe Hermann09e04f72009-05-16 22:36:00 +0000200static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000201{
202 int a;
203
204 for (a = 0; a < 2; a++) {
205 if (op->preop[a] == preop)
206 return a;
207 }
208
209 return -1;
210}
211
FENG yu ningf041e9b2008-12-15 02:32:11 +0000212static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000213{
FENG yu ningf041e9b2008-12-15 02:32:11 +0000214 int a, b, i;
FENG yu ningc05a2952008-12-08 18:16:58 +0000215 uint16_t preop, optype;
216 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000217
218 if (op == NULL) {
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000219 printf_debug("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000220 return -1;
221 }
222
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000223 switch (spi_controller) {
224 case SPI_CONTROLLER_ICH7:
225 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000226 preop = REGREAD16(ICH7_REG_PREOP);
227 optype = REGREAD16(ICH7_REG_OPTYPE);
228 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
229 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
230 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000231 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000232 preop = REGREAD16(ICH9_REG_PREOP);
233 optype = REGREAD16(ICH9_REG_OPTYPE);
234 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
235 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
236 break;
237 default:
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000238 printf_debug("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000239 return -1;
240 }
241
242 op->preop[0] = (uint8_t) preop;
243 op->preop[1] = (uint8_t) (preop >> 8);
244
245 for (a = 0; a < 8; a++) {
246 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
247 optype >>= 2;
248 }
249
250 for (a = 0; a < 4; a++) {
251 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
252 opmenu[0] >>= 8;
253 }
254
255 for (a = 4; a < 8; a++) {
256 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
257 opmenu[1] >>= 8;
258 }
259
260 /* atomic (link opcode with required pre-op) */
261 for (a = 4; a < 8; a++)
262 op->opcode[a].atomic = 0;
263
FENG yu ningf041e9b2008-12-15 02:32:11 +0000264 for (i = 0; pops[i].opcode; i++) {
265 a = find_opcode(op, pops[i].opcode);
266 b = find_preop(op, pops[i].preop);
267 if ((a != -1) && (b != -1))
268 op->opcode[a].atomic = (uint8_t) ++b;
FENG yu ningc05a2952008-12-08 18:16:58 +0000269 }
270
271 return 0;
272}
273
Dominik Geyerb46acba2008-05-16 12:55:55 +0000274int program_opcodes(OPCODES * op)
275{
276 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000277 uint16_t preop, optype;
278 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000279
280 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000281 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000282 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000283 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000284 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000285
Stefan Reinauera9424d52008-06-27 16:28:34 +0000286 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000287 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000289 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000290 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000291
Stefan Reinauera9424d52008-06-27 16:28:34 +0000292 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000293 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000294 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000295 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000296 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000297
Dominik Geyerb46acba2008-05-16 12:55:55 +0000298 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000299 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000300 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000301 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000302 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000303
Peter Stuge016d4e12009-01-15 02:13:18 +0000304 printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000305 switch (spi_controller) {
306 case SPI_CONTROLLER_ICH7:
307 case SPI_CONTROLLER_VIA:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000308 REGWRITE16(ICH7_REG_PREOP, preop);
309 REGWRITE16(ICH7_REG_OPTYPE, optype);
310 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
311 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
312 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000313 case SPI_CONTROLLER_ICH9:
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000314 REGWRITE16(ICH9_REG_PREOP, preop);
315 REGWRITE16(ICH9_REG_OPTYPE, optype);
316 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
317 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
318 break;
319 default:
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000320 printf_debug("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000321 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000322 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000323
324 return 0;
325}
326
FENG yu ningf041e9b2008-12-15 02:32:11 +0000327/* This function generates OPCODES from or programs OPCODES to ICH according to
328 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000329 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000330 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000331 */
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000332int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000333{
334 int rc = 0;
335 OPCODES *curopcodes_done;
336
337 if (curopcodes)
338 return 0;
339
340 if (ichspi_lock) {
341 printf_debug("Generating OPCODES... ");
342 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000343 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000344 } else {
345 printf_debug("Programming OPCODES... ");
346 curopcodes_done = &O_ST_M25P;
347 rc = program_opcodes(curopcodes_done);
348 }
349
350 if (rc) {
351 curopcodes = NULL;
352 printf_debug("failed\n");
353 return 1;
354 } else {
355 curopcodes = curopcodes_done;
356 printf_debug("done\n");
357 return 0;
358 }
359}
360
Stefan Reinauer43119562008-11-02 19:51:50 +0000361static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000362 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000363{
364 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000365 int timeout;
Peter Stuge7e2c0792008-06-29 01:30:41 +0000366 uint32_t temp32 = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000367 uint16_t temp16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000368 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000369 uint64_t opmenu;
370 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000371
372 /* Is it a write command? */
373 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
374 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
375 write_cmd = 1;
376 }
377
378 /* Programm Offset in Flash into FADDR */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000379 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000380
381 /* Program data into FDATA0 to N */
382 if (write_cmd && (datalength != 0)) {
383 temp32 = 0;
384 for (a = 0; a < datalength; a++) {
385 if ((a % 4) == 0) {
386 temp32 = 0;
387 }
388
389 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
390
391 if ((a % 4) == 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000392 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
393 temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000394 }
395 }
396 if (((a - 1) % 4) != 3) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000397 REGWRITE32(ICH7_REG_SPID0 +
398 ((a - 1) - ((a - 1) % 4)), temp32);
399 }
400
401 }
402
403 /* Assemble SPIS */
404 temp16 = 0;
405 /* clear error status registers */
406 temp16 |= (SPIS_CDS + SPIS_FCERR);
407 REGWRITE16(ICH7_REG_SPIS, temp16);
408
409 /* Assemble SPIC */
410 temp16 = 0;
411
412 if (datalength != 0) {
413 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000414 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000415 }
416
417 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000418 opmenu = REGREAD32(ICH7_REG_OPMENU);
419 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
420
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000421 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
422 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000423 break;
424 }
425 opmenu >>= 8;
426 }
427 if (opcode_index == 8) {
428 printf_debug("Opcode %x not found.\n", op.opcode);
429 return 1;
430 }
431 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000432
433 /* Handle Atomic */
434 if (op.atomic != 0) {
435 /* Select atomic command */
436 temp16 |= SPIC_ACS;
Carl-Daniel Hailfinger738fdff2008-11-18 00:43:14 +0000437 /* Select prefix opcode */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000438 if ((op.atomic - 1) == 1) {
439 /*Select prefix opcode 2 */
440 temp16 |= SPIC_SPOP;
441 }
442 }
443
444 /* Start */
445 temp16 |= SPIC_SCGO;
446
447 /* write it */
448 REGWRITE16(ICH7_REG_SPIC, temp16);
449
450 /* wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000451 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauera9424d52008-06-27 16:28:34 +0000452 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000453 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000454 }
455 if (!timeout) {
456 printf_debug("timeout\n");
457 }
458
459 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
460 printf_debug("Transaction error!\n");
461 return 1;
462 }
463
464 if ((!write_cmd) && (datalength != 0)) {
465 for (a = 0; a < datalength; a++) {
466 if ((a % 4) == 0) {
467 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
468 }
469
470 data[a] =
471 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
472 >> ((a % 4) * 8);
473 }
474 }
475
476 return 0;
477}
478
Stefan Reinauer43119562008-11-02 19:51:50 +0000479static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000480 uint8_t datalength, uint8_t * data)
481{
482 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000484 uint32_t temp32;
485 uint32_t a;
Stefan Reinauer43119562008-11-02 19:51:50 +0000486 uint64_t opmenu;
487 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000488
489 /* Is it a write command? */
490 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
491 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
492 write_cmd = 1;
493 }
494
495 /* Programm Offset in Flash into FADDR */
496 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
497
498 /* Program data into FDATA0 to N */
499 if (write_cmd && (datalength != 0)) {
500 temp32 = 0;
501 for (a = 0; a < datalength; a++) {
502 if ((a % 4) == 0) {
503 temp32 = 0;
504 }
505
506 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
507
508 if ((a % 4) == 3) {
509 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
510 temp32);
511 }
512 }
513 if (((a - 1) % 4) != 3) {
514 REGWRITE32(ICH9_REG_FDATA0 +
515 ((a - 1) - ((a - 1) % 4)), temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000516 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000517 }
518
519 /* Assemble SSFS + SSFC */
520 temp32 = 0;
521
522 /* clear error status registers */
523 temp32 |= (SSFS_CDS + SSFS_FCERR);
524 /* USE 20 MhZ */
525 temp32 |= SSFC_SCF_20MHZ;
526
527 if (datalength != 0) {
528 uint32_t datatemp;
529 temp32 |= SSFC_DS;
530 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
531 temp32 |= datatemp;
532 }
533
534 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000535 opmenu = REGREAD32(ICH9_REG_OPMENU);
536 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
537
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000538 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
539 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000540 break;
541 }
542 opmenu >>= 8;
543 }
544 if (opcode_index == 8) {
545 printf_debug("Opcode %x not found.\n", op.opcode);
546 return 1;
547 }
548 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000549
550 /* Handle Atomic */
551 if (op.atomic != 0) {
552 /* Select atomic command */
553 temp32 |= SSFC_ACS;
554 /* Selct prefix opcode */
555 if ((op.atomic - 1) == 1) {
556 /*Select prefix opcode 2 */
557 temp32 |= SSFC_SPOP;
558 }
559 }
560
561 /* Start */
562 temp32 |= SSFC_SCGO;
563
564 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000565 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000566
567 /*wait for cycle complete */
Carl-Daniel Hailfinger4c24ad42009-05-09 07:24:23 +0000568 timeout = 100 * 1000 * 60; // 60s is a looong timeout.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000569 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000570 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000571 }
572 if (!timeout) {
573 printf_debug("timeout\n");
Dominik Geyerb46acba2008-05-16 12:55:55 +0000574 }
575
Stefan Reinauera9424d52008-06-27 16:28:34 +0000576 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000577 printf_debug("Transaction error!\n");
578 return 1;
579 }
580
581 if ((!write_cmd) && (datalength != 0)) {
582 for (a = 0; a < datalength; a++) {
583 if ((a % 4) == 0) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000584 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
Dominik Geyerb46acba2008-05-16 12:55:55 +0000585 }
586
587 data[a] =
Stefan Reinauera9424d52008-06-27 16:28:34 +0000588 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
589 >> ((a % 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000590 }
591 }
592
593 return 0;
594}
595
Stefan Reinauer43119562008-11-02 19:51:50 +0000596static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000597 uint8_t datalength, uint8_t * data)
598{
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000599 switch (spi_controller) {
600 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000601 if (datalength > 16)
602 return SPI_INVALID_LENGTH;
Stefan Reinauer43119562008-11-02 19:51:50 +0000603 return ich7_run_opcode(op, offset, datalength, data, 16);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000604 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000605 if (datalength > 64)
606 return SPI_INVALID_LENGTH;
Stefan Reinauer43119562008-11-02 19:51:50 +0000607 return ich7_run_opcode(op, offset, datalength, data, 64);
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000608 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000609 if (datalength > 64)
610 return SPI_INVALID_LENGTH;
Stefan Reinauer43119562008-11-02 19:51:50 +0000611 return ich9_run_opcode(op, offset, datalength, data);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000612 default:
Uwe Hermann04aa59a2009-09-02 22:09:00 +0000613 printf_debug("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000614 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000615
616 /* If we ever get here, something really weird happened */
617 return -1;
618}
619
Dominik Geyerb46acba2008-05-16 12:55:55 +0000620static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000621 int offset, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000622{
623 int page_size = flash->page_size;
624 uint32_t remaining = page_size;
Carl-Daniel Hailfingerd1680572009-06-17 10:13:42 +0000625 int towrite;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000626
Stefan Reinauera9424d52008-06-27 16:28:34 +0000627 printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
628 offset, page_size, bytes);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000629
Carl-Daniel Hailfingerd1680572009-06-17 10:13:42 +0000630 for (; remaining > 0; remaining -= towrite) {
631 towrite = min(remaining, maxdata);
632 if (spi_nbyte_program(offset + (page_size - remaining),
633 &bytes[page_size - remaining], towrite)) {
634 printf_debug("Error writing");
635 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000636 }
637 }
638
639 return 0;
640}
641
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000642int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000643{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000644 int maxdata = 64;
645
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000646 if (spi_controller == SPI_CONTROLLER_VIA)
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000647 maxdata = 16;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000648
Carl-Daniel Hailfingercbf563c2009-06-16 08:55:44 +0000649 return spi_read_chunked(flash, buf, start, len, maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000650}
651
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000652int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000653{
654 int i, j, rc = 0;
655 int total_size = flash->total_size * 1024;
656 int page_size = flash->page_size;
657 int erase_size = 64 * 1024;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000658 int maxdata = 64;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000659
660 spi_disable_blockprotect();
661
662 printf("Programming page: \n");
663
664 for (i = 0; i < total_size / erase_size; i++) {
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000665 /* FIMXE: call the chip-specific spi_block_erase_XX instead.
666 * For this, we need to add a block erase function to
667 * struct flashchip.
668 */
Carl-Daniel Hailfinger3431bb72009-06-24 08:28:39 +0000669 rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000670 if (rc) {
671 printf("Error erasing block at 0x%x\n", i);
672 break;
673 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000674
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000675 if (spi_controller == SPI_CONTROLLER_VIA)
Peter Stuge6a214162008-07-07 05:14:06 +0000676 maxdata = 16;
677
Dominik Geyerb46acba2008-05-16 12:55:55 +0000678 for (j = 0; j < erase_size / page_size; j++) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000679 ich_spi_write_page(flash,
680 (void *)(buf + (i * erase_size) + (j * page_size)),
681 (i * erase_size) + (j * page_size), maxdata);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000682 }
683 }
684
685 printf("\n");
686
687 return rc;
688}
689
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +0000690int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000691 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000692{
693 int a;
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000694 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000695 int opcode_index = -1;
696 const unsigned char cmd = *writearr;
697 OPCODE *opcode;
698 uint32_t addr = 0;
699 uint8_t *data;
700 int count;
701
Dominik Geyerb46acba2008-05-16 12:55:55 +0000702 /* find cmd in opcodes-table */
703 for (a = 0; a < 8; a++) {
704 if ((curopcodes->opcode[a]).opcode == cmd) {
705 opcode_index = a;
706 break;
707 }
708 }
709
710 /* unknown / not programmed command */
711 if (opcode_index == -1) {
712 printf_debug("Invalid OPCODE 0x%02x\n", cmd);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000713 return SPI_INVALID_OPCODE;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000714 }
715
716 opcode = &(curopcodes->opcode[opcode_index]);
717
718 /* if opcode-type requires an address */
719 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
720 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000721 addr = (writearr[1] << 16) |
722 (writearr[2] << 8) | (writearr[3] << 0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000723 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000724
Dominik Geyerb46acba2008-05-16 12:55:55 +0000725 /* translate read/write array/count */
726 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000727 data = (uint8_t *) (writearr + 1);
728 count = writecnt - 1;
729 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
730 data = (uint8_t *) (writearr + 4);
731 count = writecnt - 4;
732 } else {
733 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000734 count = readcnt;
735 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000736
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000737 result = run_opcode(*opcode, addr, count, data);
738 if (result) {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000739 printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000740 }
741
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000742 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000743}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000744
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000745int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000746{
747 int ret = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000748 int oppos, preoppos;
749 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
750 /* Is the next command valid or a terminator? */
751 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
752 preoppos = find_preop(curopcodes, cmds->writearr[0]);
753 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
754 /* Is the opcode of the current command listed in the
755 * ICH struct OPCODES as associated preopcode for the
756 * opcode of the next command?
757 */
758 if ((oppos != -1) && (preoppos != -1) &&
Carl-Daniel Hailfinger0709a782009-10-22 15:07:30 +0000759 ((curopcodes->opcode[oppos].atomic - 1) == preoppos))
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000760 continue;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +0000761 }
762
763 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
764 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +0000765 }
766 return ret;
767}