Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Andrew Morgan | a074383 | 2011-07-25 22:07:05 +0000 | [diff] [blame] | 17 | #if defined(__i386__) || defined(__x86_64__) |
| 18 | |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 19 | #include <stdlib.h> |
| 20 | #include <string.h> |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 21 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 22 | #include "programmer.h" |
Patrick Georgi | 32508eb | 2012-07-20 20:35:14 +0000 | [diff] [blame] | 23 | #include "hwaccess.h" |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 24 | |
| 25 | #define BIOS_ROM_ADDR 0x90 |
| 26 | #define BIOS_ROM_DATA 0x94 |
| 27 | |
| 28 | #define REG_FLASH_ACCESS 0x58 |
| 29 | |
| 30 | #define PCI_VENDOR_ID_HPT 0x1103 |
| 31 | |
Stefan Tauner | 0ccec8f | 2014-06-01 23:49:03 +0000 | [diff] [blame] | 32 | static uint32_t io_base_addr = 0; |
| 33 | |
Stefan Tauner | 4b24a2d | 2012-12-27 18:40:36 +0000 | [diff] [blame] | 34 | const struct dev_entry ata_hpt[] = { |
Michael Karcher | 8448639 | 2010-02-24 00:04:40 +0000 | [diff] [blame] | 35 | {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, |
| 36 | {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, |
| 37 | {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"}, |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 38 | |
Carl-Daniel Hailfinger | 1c6d2ff | 2012-08-27 00:44:42 +0000 | [diff] [blame] | 39 | {0}, |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 40 | }; |
| 41 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 42 | static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val, |
| 43 | chipaddr addr); |
| 44 | static uint8_t atahpt_chip_readb(const struct flashctx *flash, |
| 45 | const chipaddr addr); |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 46 | static const struct par_master par_master_atahpt = { |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 47 | .chip_readb = atahpt_chip_readb, |
| 48 | .chip_readw = fallback_chip_readw, |
| 49 | .chip_readl = fallback_chip_readl, |
| 50 | .chip_readn = fallback_chip_readn, |
| 51 | .chip_writeb = atahpt_chip_writeb, |
| 52 | .chip_writew = fallback_chip_writew, |
| 53 | .chip_writel = fallback_chip_writel, |
| 54 | .chip_writen = fallback_chip_writen, |
| 55 | }; |
| 56 | |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 57 | int atahpt_init(void) |
| 58 | { |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 59 | struct pci_dev *dev = NULL; |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 60 | uint32_t reg32; |
| 61 | |
Carl-Daniel Hailfinger | d6bb828 | 2012-07-21 17:27:08 +0000 | [diff] [blame] | 62 | if (rget_io_perms()) |
| 63 | return 1; |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 64 | |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 65 | dev = pcidev_init(ata_hpt, PCI_BASE_ADDRESS_4); |
| 66 | if (!dev) |
| 67 | return 1; |
| 68 | |
| 69 | io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4); |
Niklas Söderlund | 89edf36 | 2013-08-23 23:29:23 +0000 | [diff] [blame] | 70 | if (!io_base_addr) |
| 71 | return 1; |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 72 | |
| 73 | /* Enable flash access. */ |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 74 | reg32 = pci_read_long(dev, REG_FLASH_ACCESS); |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 75 | reg32 |= (1 << 24); |
Carl-Daniel Hailfinger | a2faddf | 2013-01-05 23:52:45 +0000 | [diff] [blame] | 76 | rpci_write_long(dev, REG_FLASH_ACCESS, reg32); |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 77 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 78 | register_par_master(&par_master_atahpt, BUS_PARALLEL); |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 79 | |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 80 | return 0; |
| 81 | } |
| 82 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 83 | static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val, |
| 84 | chipaddr addr) |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 85 | { |
| 86 | OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); |
| 87 | OUTB(val, io_base_addr + BIOS_ROM_DATA); |
| 88 | } |
| 89 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 90 | static uint8_t atahpt_chip_readb(const struct flashctx *flash, |
| 91 | const chipaddr addr) |
Uwe Hermann | ddd5c9e | 2010-02-21 21:17:00 +0000 | [diff] [blame] | 92 | { |
| 93 | OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); |
| 94 | return INB(io_base_addr + BIOS_ROM_DATA); |
| 95 | } |
Andrew Morgan | a074383 | 2011-07-25 22:07:05 +0000 | [diff] [blame] | 96 | |
| 97 | #else |
| 98 | #error PCI port I/O access is not supported on this architecture yet. |
| 99 | #endif |